mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / southbridge / intel / i82801ix / fadt.c
blob795a4c48a78a4567831d36c595938b525030f009
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/pci_ops.h>
4 #include <acpi/acpi.h>
5 #include <southbridge/intel/common/pmutil.h>
7 void acpi_fill_fadt(acpi_fadt_t *fadt)
9 u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe;
12 fadt->pm1a_evt_blk = pmbase;
13 fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
14 fadt->pm2_cnt_blk = pmbase + PM2_CNT;
15 fadt->pm_tmr_blk = pmbase + PM1_TMR;
16 fadt->gpe0_blk = pmbase + GPE0_STS;
18 fadt->pm1_evt_len = 4;
19 fadt->pm1_cnt_len = 2; /* Upper word is reserved and
20 Linux complains about 32 bit. */
21 fadt->pm2_cnt_len = 1;
22 fadt->pm_tmr_len = 4;
23 fadt->gpe0_blk_len = 16;
24 fadt->p_lvl2_lat = 1;
25 fadt->p_lvl3_lat = 0x39;
26 fadt->duty_offset = 1;
27 fadt->duty_width = 3;
29 fill_fadt_extended_pm_io(fadt);
31 fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE;
32 fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
33 ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE |
34 ACPI_FADT_DOCKING_SUPPORTED | ACPI_FADT_PLATFORM_CLOCK;