src/southbridge/intel/i82801ix/sata.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/io.h>
   4 #include <device/mmio.h>
   5 #include <device/pci_ops.h>
   6 #include <console/console.h>
   7 #include <device/device.h>
   8 #include <device/pci.h>
   9 #include <device/pci_ids.h>
  10 #include <option.h>
  11 #include <types.h>
  12
  13 #include "chip.h"
  14 #include "i82801ix.h"
  15
  16 typedef struct southbridge_intel_i82801ix_config config_t;
  17
  18 static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map,
  19                                   const int is_mobile)
  20 {
  21         int i;
  22         u32 reg32;
  23         struct resource *res;
  24
  25         /* Initialize AHCI memory-mapped space */
  26         res = probe_resource(dev, PCI_BASE_ADDRESS_5);
  27         if (!res)
  28                 return;
  29
  30         u8 *abar = res2mmio(res, 0, 0);
  31         printk(BIOS_DEBUG, "ABAR: %p\n", abar);
  32
  33         /* Set AHCI access mode.
  34            No other ABAR registers should be accessed before this. */
  35         reg32 = read32(abar + 0x04);
  36         reg32 |= 1 << 31;
  37         write32(abar + 0x04, reg32);
  38
  39         /* CAP (HBA Capabilities) : enable power management */
  40         reg32 = read32(abar + 0x00);
  41         /* CCCS must be set. */
  42         reg32 |= 0x0c006080;  /* set CCCS+PSC+SSC+SALP+SSS */
  43         reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
  44         write32(abar + 0x00, reg32);
  45
  46         /* PI (Ports implemented) */
  47         write32(abar + 0x0c, port_map);
  48         /* PCH code reads back twice, do we need it, too? */
  49         (void)read32(abar + 0x0c); /* Read back 1 */
  50         (void)read32(abar + 0x0c); /* Read back 2 */
  51
  52         /* VSP (Vendor Specific Register) */
  53         reg32 = read32(abar + 0xa0);
  54         reg32 &= ~0x00000001; /* clear SLPD */
  55         write32(abar + 0xa0, reg32);
  56
  57         /* Lock R/WO bits in Port command registers. */
  58         for (i = 0; i < 6; ++i) {
  59                 if (((i == 2) || (i == 3)) && is_mobile)
  60                         continue;
  61                 u8 *addr = abar + 0x118 + (i * 0x80);
  62                 write32(addr, read32(addr));
  63         }
  64 }
  65
  66 static void sata_program_indexed(struct device *const dev, const int is_mobile)
  67 {
  68         u32 reg32;
  69
  70         pci_write_config8(dev, D31F2_SIDX, 0x18);
  71         reg32 = pci_read_config32(dev, D31F2_SDAT);
  72         reg32 &= ~((7 << 6) | (7 << 3) | (7 << 0));
  73         reg32 |= (3 << 3) | (3 << 0);
  74         pci_write_config32(dev, D31F2_SDAT, reg32);
  75
  76         pci_write_config8(dev, D31F2_SIDX, 0x28);
  77         pci_write_config32(dev, D31F2_SDAT, 0x00cc2080);
  78
  79         pci_write_config8(dev, D31F2_SIDX, 0x40);
  80         pci_write_config8(dev, D31F2_SDAT + 2, 0x22);
  81
  82         pci_write_config8(dev, D31F2_SIDX, 0x78);
  83         pci_write_config8(dev, D31F2_SDAT + 2, 0x22);
  84
  85         if (!is_mobile) {
  86                 pci_write_config8(dev, D31F2_SIDX, 0x84);
  87                 reg32 = pci_read_config32(dev, D31F2_SDAT);
  88                 reg32 &= ~((7 << 3) | (7 << 0));
  89                 reg32 |= (3 << 3) | (3 << 0);
  90                 pci_write_config32(dev, D31F2_SDAT, reg32);
  91         }
  92
  93         pci_write_config8(dev, D31F2_SIDX, 0x88);
  94         reg32 = pci_read_config32(dev, D31F2_SDAT);
  95         if (!is_mobile)
  96                 reg32 &= ~((7 << 27) | (7 << 24) | (7 << 11) | (7 << 8));
  97         reg32 &= ~((7 << 19) | (7 << 16) | (7 << 3) | (7 << 0));
  98         if (!is_mobile)
  99                 reg32 |= (4 << 27) | (4 << 24) | (2 << 11) | (2 << 8);
 100         reg32 |= (4 << 19) | (4 << 16) | (2 << 3) | (2 << 0);
 101         pci_write_config32(dev, D31F2_SDAT, reg32);
 102
 103         pci_write_config8(dev, D31F2_SIDX, 0x8c);
 104         reg32 = pci_read_config32(dev, D31F2_SDAT);
 105         if (!is_mobile)
 106                 reg32 &= ~((7 << 27) | (7 << 24));
 107         reg32 &= ~((7 << 19) | (7 << 16) | 0xffff);
 108         if (!is_mobile)
 109                 reg32 |= (2 << 27) | (2 << 24);
 110         reg32 |= (2 << 19) | (2 << 16) | 0x00aa;
 111         pci_write_config32(dev, D31F2_SDAT, reg32);
 112
 113         pci_write_config8(dev, D31F2_SIDX, 0x94);
 114         pci_write_config32(dev, D31F2_SDAT, 0x00000022);
 115
 116         pci_write_config8(dev, D31F2_SIDX, 0xa0);
 117         reg32 = pci_read_config32(dev, D31F2_SDAT);
 118         reg32 &= ~((7 << 3) | (7 << 0));
 119         reg32 |= (3 << 3) | (3 << 0);
 120         pci_write_config32(dev, D31F2_SDAT, reg32);
 121
 122         pci_write_config8(dev, D31F2_SIDX, 0xa8);
 123         reg32 = pci_read_config32(dev, D31F2_SDAT);
 124         reg32 &= ~((7 << 19) | (7 << 16) | (7 << 3) | (7 << 0));
 125         reg32 |= (4 << 19) | (4 << 16) | (2 << 3) | (2 << 0);
 126         pci_write_config32(dev, D31F2_SDAT, reg32);
 127
 128         pci_write_config8(dev, D31F2_SIDX, 0xac);
 129         reg32 = pci_read_config32(dev, D31F2_SDAT);
 130         reg32 &= ~((7 << 19) | (7 << 16) | 0xffff);
 131         reg32 |= (2 << 19) | (2 << 16) | 0x000a;
 132         pci_write_config32(dev, D31F2_SDAT, reg32);
 133 }
 134
 135 static void sata_init(struct device *const dev)
 136 {
 137         u16 reg16;
 138
 139         /* Get the chip configuration */
 140         const config_t *const config = dev->chip_info;
 141
 142         const u16 devid = pci_read_config16(dev, PCI_DEVICE_ID);
 143         const int is_mobile = (devid == PCI_DID_INTEL_82801IBM_IEM_SATA_IDE_P01) ||
 144                               (devid == PCI_DID_INTEL_82801IBM_IEM_SATA_AHCI_P0145);
 145
 146         printk(BIOS_DEBUG, "i82801ix_sata: initializing...\n");
 147
 148         if (config == NULL) {
 149                 printk(BIOS_ERR, "i82801ix_sata: error: "
 150                                  "device not in devicetree.cb!\n");
 151                 return;
 152         }
 153
 154         /* Default to AHCI */
 155         u8 sata_mode = get_uint_option("sata_mode", 0);
 156
 157         /*
 158          * TODO: In contrast to ICH7 and PCH code we don't set
 159          * timings, dma and IDE-I/O settings here. Looks like they
 160          * became obsolete with the fading of real IDE ports.
 161          * Maybe we can safely remove those settings from PCH code and
 162          * even ICH7 code if it doesn't use the feature to combine the
 163          * IDE and SATA controllers.
 164          */
 165
 166         pci_write_config16(dev, PCI_COMMAND,
 167                         PCI_COMMAND_MASTER |
 168                         PCI_COMMAND_MEMORY | /* read-only in IDE modes */
 169                         PCI_COMMAND_IO);
 170         if (sata_mode != 0)
 171                 /* No AHCI: clear AHCI base */
 172                 pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000);
 173
 174         if (sata_mode == 0) {
 175                 printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
 176         } else {
 177                 printk(BIOS_DEBUG, "SATA controller in native mode.\n");
 178
 179                 /* Enable native mode on both primary and secondary. */
 180                 pci_write_config8(dev, PCI_CLASS_PROG, 0x8f);
 181         }
 182
 183         /* Looks like we should only enable decoding here. */
 184         pci_write_config16(dev, D31F2_IDE_TIM_PRI, (1 << 15));
 185         pci_write_config16(dev, D31F2_IDE_TIM_SEC, (1 << 15));
 186
 187         /* Port enable. For AHCI, it's managed in memory mapped space. */
 188         reg16 = pci_read_config16(dev, 0x92);
 189         reg16 &= ~0x3f;
 190         reg16 |= (1 << 15) | ((sata_mode == 0) ? 0x3f : config->sata_port_map);
 191         pci_write_config16(dev, 0x92, reg16);
 192
 193         /* SATA clock settings */
 194         u32 sclkcg = 0;
 195         if (config->sata_clock_request &&
 196                         !(inb(DEFAULT_GPIOBASE + 0x30) & (1 << (35 - 32))))
 197                 sclkcg |= 1 << 30; /* Enable SATA clock request. */
 198         /* Disable unused ports. */
 199         sclkcg |= ((~config->sata_port_map) & 0x3f) << 24;
 200         /* Must be programmed. */
 201         sclkcg |= 0x193;
 202         pci_write_config32(dev, 0x94, sclkcg);
 203
 204         if (is_mobile && config->sata_traffic_monitor) {
 205                 struct device *const lpc_dev = pcidev_on_root(0x1f, 0);
 206                 if (((pci_read_config8(lpc_dev, D31F0_CxSTATE_CNF) >> 3) & 3) == 3) {
 207                         u8 reg8 = pci_read_config8(dev, 0x9c);
 208                         reg8 &= ~(0x1f << 2);
 209                         reg8 |= 3 << 2;
 210                         pci_write_config8(dev, 0x9c, reg8);
 211                 }
 212         }
 213
 214         if (sata_mode == 0)
 215                 sata_enable_ahci_mmap(dev, config->sata_port_map, is_mobile);
 216
 217         sata_program_indexed(dev, is_mobile);
 218 }
 219
 220 static void sata_enable(struct device *dev)
 221 {
 222         /* Get the chip configuration */
 223         const config_t *const config = dev->chip_info;
 224
 225         u16 map = 0;
 226
 227         if (!config)
 228                 return;
 229
 230         u8 sata_mode = get_uint_option("sata_mode", 0);
 231
 232         /*
 233          * Set SATA controller mode early so the resource allocator can
 234          * properly assign IO/Memory resources for the controller.
 235          */
 236         if (sata_mode == 0)
 237                 map = 0x0040 | 0x0020; /* SATA mode + all ports on D31:F2 */
 238
 239         map |= (config->sata_port_map ^ 0x3f) << 8;
 240
 241         pci_write_config16(dev, 0x90, map);
 242 }
 243
 244 static struct device_operations sata_ops = {
 245         .read_resources         = pci_dev_read_resources,
 246         .set_resources          = pci_dev_set_resources,
 247         .enable_resources       = pci_dev_enable_resources,
 248         .init                   = sata_init,
 249         .enable                 = sata_enable,
 250         .ops_pci                = &pci_dev_ops_pci,
 251 };
 252
 253 static const unsigned short pci_device_ids[] = {
 254         PCI_DID_INTEL_82801IB_SATA_P0123,
 255         PCI_DID_INTEL_82801IB_SATA_P01,
 256         PCI_DID_INTEL_82801IB_SATA_AHCI1,
 257         PCI_DID_INTEL_82801IB_SATA_AHCI2,
 258         PCI_DID_INTEL_82801IBM_IEM_SATA_IDE_P01,
 259         PCI_DID_INTEL_82801IBM_IEM_SATA_AHCI_P0145,
 260         0,
 261 };
 262
 263 static const struct pci_driver pch_sata __pci_driver = {
 264         .ops     = &sata_ops,
 265         .vendor  = PCI_VID_INTEL,
 266         .devices = pci_device_ids,
 267 };