mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / southbridge / intel / i82801ix / smbus.c
blob8f60408433f5cdbe95d8358f1049e3471a49a772
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/device.h>
4 #include <device/smbus.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <device/pci_ops.h>
8 #include <device/smbus_host.h>
9 #include <southbridge/intel/common/smbus_ops.h>
10 #include "i82801ix.h"
12 static void pch_smbus_init(struct device *dev)
14 /* Enable clock gating */
15 pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)));
18 static struct device_operations smbus_ops = {
19 .read_resources = smbus_read_resources,
20 .set_resources = pci_dev_set_resources,
21 .enable_resources = pci_dev_enable_resources,
22 .scan_bus = scan_smbus,
23 .init = pch_smbus_init,
24 .ops_smbus_bus = &lops_smbus_bus,
25 .ops_pci = &pci_dev_ops_pci,
28 static const struct pci_driver pch_smbus __pci_driver = {
29 .ops = &smbus_ops,
30 .vendor = PCI_VID_INTEL,
31 .device = PCI_DID_INTEL_82801IB_SMB,