src/soc/intel/xeon_sp/cpx/Makefile.mk

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2
   3 ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y)
   4
   5 subdirs-y += ../../../../cpu/intel/turbo
   6 subdirs-y += ../../../../cpu/intel/microcode
   7
   8 romstage-y += romstage.c ddr.c soc_util.c
   9 romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
  10 romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
  11
  12 ramstage-y += chip.c cpu.c soc_util.c soc_acpi.c
  13 ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
  14 ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
  15
  16 CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx
  17 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cooperlake_sp
  18
  19 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-0b
  20
  21 endif ## CONFIG_SOC_INTEL_COOPERLAKE_SP