1 chip soc
/intel
/tigerlake
3 # Enable Enhanced Intel SpeedStep
4 register
"eist_enable" = "true"
7 #
Not used but timings left
for reference
8 # register
"panel_cfg" = "{
9 # .up_delay_ms = 2000, // T3
10 # .backlight_on_delay_ms = 0, // T7
11 # .backlight_off_delay_ms = 2000, // T9
12 # .down_delay_ms = 500, // T10
13 # .cycle_delay_ms = 500, // T12
14 # .backlight_pwm_hz = 200, // PWM
18 register
"CnviBtCore" = "true"
19 register
"CnviBtAudioOffload" = "1"
20 register
"enable_c6dram" = "1"
21 register
"SaGv" = "SaGv_Enabled"
25 register
"SerialIoI2cMode" = "{
26 [PchSerialIoIndexI2C0] = PchSerialIoPci,
27 [PchSerialIoIndexI2C4] = PchSerialIoSkipInit,
30 register
"SerialIoUartMode" = "{
31 [PchSerialIoIndexUART2] = PchSerialIoSkipInit,
35 register
"PchPmSlpS3MinAssert" = "2" #
50ms
36 register
"PchPmSlpS4MinAssert" = "3" #
1s
37 register
"PchPmSlpSusMinAssert" = "3" #
500ms
38 register
"PchPmSlpAMinAssert" = "3" #
2s
42 # Note that GPE events called out in ASL code rely on this
43 # route. i.e.
If this route changes
then the affected GPE
44 # offset bits also need
to be changed.
45 # sudo devmem2
0xfe001920 (pmc_bar
+ GPIO_GPE_CFG
)
46 register
"pmc_gpe0_dw0" = "GPP_B"
47 register
"pmc_gpe0_dw1" = "GPP_C"
48 register
"pmc_gpe0_dw2" = "GPP_E"
50 # Enable the correct decode ranges on the LPC bus.
51 register
"lpc_ioe" = "LPC_IOE_EC_4E_4F |
52 LPC_IOE_SUPERIO_2E_2F |
58 register
"PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
59 register
"PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
60 register
"PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED"
61 register
"PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED"
62 register
"PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
63 register
"PcieClkSrcClkReq[6]" = "PCIE_CLK_NOTUSED"
67 device ref igpu on
end
68 device ref dptf on
end
69 device ref tbt_pcie_rp0 on
end
71 device ref crashlog on
end
72 device ref north_xhci on
73 register
"UsbTcPortEn" = "1"
74 register
"TcssXhciEn" = "1"
75 register
"TcssAuxOri" = "0"
77 device ref tbt_dma0 on
78 chip drivers
/intel
/usb4
/retimer
79 register
"dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)"
80 use tcss_usb3_port1
as dfp
[0].typec_port
81 device generic
0 on
end
84 device ref south_xhci on
85 # Motherboard USB
Type C
86 register
"usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"
87 register
"tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
90 register
"usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"
91 register
"usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"
93 # Daughterboard USB
3.0
94 register
"usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"
95 register
"usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"
97 # Daughterboard SD Card
98 register
"usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"
101 register
"usb2_ports[CONFIG_CCD_PORT]" = "USB2_PORT_MID(OC_SKIP)"
104 register
"usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"
106 device ref shared_ram on
end
107 device ref cnvi_wifi on
108 chip drivers
/wifi
/generic
109 register
"wake" = "GPE0_PME_B0"
110 device generic
0 on
end
115 register
"generic.hid" = ""STAR0001
""
116 register
"generic.desc" = ""Touchpad
""
117 register
"generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)"
118 register
"generic.detect" = "1"
119 register
"hid_desc_reg_offset" = "0x20"
123 device ref heci1 on
end
125 register
"SataSalpSupport" = "1"
127 register
"SataPortsEnable[1]" = "1"
128 register
"SataPortsDevSlp[1]" = "1"
130 device ref i2c4 on
end
131 device ref uart2 on
end
132 device ref pcie_rp9 on
133 register
"HybridStorageMode" = "0"
134 register
"PcieRpLtrEnable[8]" = "1"
135 register
"PcieClkSrcUsage[3]" = "0x08"
136 register
"PcieClkSrcClkReq[3]" = "3"
137 register
"PcieRpSlotImplemented[8]" = "1"
138 smbios_slot_desc
"SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
139 chip soc
/intel
/common
/block
/pcie
/rtd3
140 register
"enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
141 register
"reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
142 register
"srcclk_pin" = "3"
143 device generic
0 on
end
146 device ref gspi1 on
end
147 device ref pch_espi on
148 register
"gen1_dec" = "0x000c1641"
149 register
"gen2_dec" = "0x000c0681"
150 register
"gen3_dec" = "0x000c0081"
151 chip drivers
/pc80
/tpm
152 device pnp
0c31.0 on
end
155 chip ec
/starlabs
/merlin
157 device pnp
4e
.00 on
end # IO Interface
158 device pnp
4e
.01 off
end # Com
1
159 device pnp
4e
.02 off
end # Com
2
160 device pnp
4e
.04 off
end # System Wake
-Up
161 device pnp
4e
.05 off
end # PS
/2 Mouse
162 device pnp
4e
.06 on # PS
/2 Keyboard
167 device pnp
4e
.0a off
end # Consumer IR
168 device pnp
4e
.0f off
end # Shared Memory
/Flash Interface
169 device pnp
4e
.10 off
end # RTC
-like Timer
170 device pnp
4e
.11 off
end # Power Management Channel
1
171 device pnp
4e
.12 off
end # Power Management Channel
2
172 device pnp
4e
.13 off
end # Serial Peripheral Interface
173 device pnp
4e
.14 off
end # Platform EC Interface
174 device pnp
4e
.17 off
end # Power Management Channel
3
175 device pnp
4e
.18 off
end # Power Management Channel
4
176 device pnp
4e
.19 off
end # Power Management Channel
5
179 device ref p2sb on
end
180 device ref pmc hidden
181 chip drivers
/intel
/pmc_mux
183 chip drivers
/intel
/pmc_mux
/conn
184 use usb2_port1
as usb2_port
185 use tcss_usb3_port1
as usb3_port
186 device generic
0 alias conn0 on
end
192 subsystemid
0x10ec 0x1200
193 register
"PchHdaAudioLinkHdaEnable" = "1"
195 device ref smbus on
end