src/soc/intel/jasperlake/Kconfig

   1 config SOC_INTEL_JASPERLAKE
   2         bool
   3         select ACPI_INTEL_HARDWARE_SLEEP_VALUES
   4         select ARCH_X86
   5         select BOOT_DEVICE_SUPPORTS_WRITES
   6         select CACHE_MRC_SETTINGS
   7         select CPU_INTEL_COMMON
   8         select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
   9         select CPU_SUPPORTS_PM_TIMER_EMULATION
  10         select COS_MAPPED_TO_MSB
  11         select DISPLAY_FSP_VERSION_INFO_2
  12         select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
  13         select FSP_COMPRESS_FSP_S_LZ4
  14         select FSP_M_XIP
  15         select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
  16         select GENERIC_GPIO_LIB
  17         select HAVE_DPTF_EISA_HID
  18         select HAVE_FSP_GOP
  19         select INTEL_DESCRIPTOR_MODE_CAPABLE
  20         select HAVE_SMI_HANDLER
  21         select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT
  22         select IDT_IN_EVERY_STAGE
  23         select INTEL_CAR_NEM_ENHANCED
  24         select INTEL_GMA_ACPI
  25         select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
  26         select MP_SERVICES_PPI_V1
  27         select MRC_SETTINGS_PROTECT
  28         select PARALLEL_MP_AP_WORK
  29         select PLATFORM_USES_FSP2_2
  30         select PMC_GLOBAL_RESET_ENABLE_LOCK
  31         select SOC_INTEL_COMMON
  32         select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
  33         select SOC_INTEL_COMMON_BLOCK
  34         select SOC_INTEL_COMMON_BLOCK_ACPI
  35         select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
  36         select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
  37         select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
  38         select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
  39         select SOC_INTEL_COMMON_BLOCK_CAR
  40         select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
  41         select SOC_INTEL_COMMON_BLOCK_CNVI
  42         select SOC_INTEL_COMMON_BLOCK_CPU
  43         select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
  44         select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE
  45         select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
  46         select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
  47         select SOC_INTEL_COMMON_BLOCK_HDA
  48         select SOC_INTEL_COMMON_BLOCK_ME_SPEC_13
  49         select SOC_INTEL_COMMON_BLOCK_SA
  50         select SOC_INTEL_COMMON_BLOCK_SCS
  51         select SOC_INTEL_COMMON_BLOCK_SMM
  52         select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
  53         select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
  54         select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
  55         select SOC_INTEL_COMMON_FSP_RESET
  56         select SOC_INTEL_COMMON_PCH_CLIENT
  57         select SOC_INTEL_COMMON_RESET
  58         select SOC_INTEL_CSE_SEND_EOP_LATE
  59         select SOC_INTEL_CSE_SET_EOP
  60         select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
  61         select SSE2
  62         select SUPPORT_CPU_UCODE_IN_CBFS
  63         select TSC_MONOTONIC_TIMER
  64         select UDELAY_TSC
  65         select UDK_202005_BINDING
  66         select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
  67         select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
  68         select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
  69         select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU
  70         help
  71           Intel Jasperlake support
  72
  73 if SOC_INTEL_JASPERLAKE
  74
  75 config DCACHE_RAM_BASE
  76         default 0xfef00000
  77
  78 config DCACHE_RAM_SIZE
  79         default 0x80000
  80         help
  81           The size of the cache-as-ram region required during bootblock
  82           and/or romstage.
  83
  84 config DCACHE_BSP_STACK_SIZE
  85         hex
  86         default 0x30400
  87         help
  88           The amount of anticipated stack usage in CAR by bootblock and
  89           other stages. In the case of FSP_USES_CB_STACK default value
  90           will be sum of FSP-M stack requirement(192 KiB) and CB romstage
  91           stack requirement(~1KiB).
  92
  93 config FSP_TEMP_RAM_SIZE
  94         hex
  95         default 0x20000
  96         help
  97           The amount of anticipated heap usage in CAR by FSP.
  98           Refer to Platform FSP integration guide document to know
  99           the exact FSP requirement for Heap setup.
 100
 101 config IFD_CHIPSET
 102         string
 103         default "jsl"
 104
 105 config IED_REGION_SIZE
 106         hex
 107         default 0x400000
 108
 109 config MAX_ROOT_PORTS
 110         int
 111         default 8
 112
 113 config MAX_PCIE_CLOCK_SRC
 114         int
 115         default 6
 116
 117 config SMM_TSEG_SIZE
 118         hex
 119         default 0x800000
 120
 121 config SMM_RESERVED_SIZE
 122         hex
 123         default 0x200000
 124
 125 config PCR_BASE_ADDRESS
 126         hex
 127         default 0xfd000000
 128         help
 129           This option allows you to select MMIO Base Address of sideband bus.
 130
 131 config ECAM_MMCONF_BASE_ADDRESS
 132         default 0xc0000000
 133
 134 config CPU_BCLK_MHZ
 135         int
 136         default 100
 137
 138 config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 139         int
 140         default 120
 141
 142 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 143         int
 144         default 133
 145
 146 config CPU_XTAL_HZ
 147         default 38400000
 148
 149 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
 150         int
 151         default 3
 152
 153 config SOC_INTEL_I2C_DEV_MAX
 154         int
 155         default 6
 156
 157 config SOC_INTEL_UART_DEV_MAX
 158         int
 159         default 3
 160
 161 config CONSOLE_UART_BASE_ADDRESS
 162         hex
 163         default 0xfe032000
 164         depends on INTEL_LPSS_UART_FOR_CONSOLE
 165
 166 # Clock divider parameters for 115200 baud rate
 167 # Baudrate = (UART source clock * M) /(N *16)
 168 # JSL UART source clock: 100MHz
 169 config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
 170         hex
 171         default 0x30
 172
 173 config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
 174         hex
 175         default 0xc35
 176
 177 config VBOOT
 178         select VBOOT_MUST_REQUEST_DISPLAY
 179         select VBOOT_STARTS_IN_BOOTBLOCK
 180         select VBOOT_VBNV_CMOS
 181         select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
 182
 183 config CBFS_SIZE
 184         default 0x200000
 185
 186 config FSP_HEADER_PATH
 187         default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/"
 188
 189 config FSP_FD_PATH
 190         default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd"
 191
 192 config SOC_INTEL_JASPERLAKE_DEBUG_CONSENT
 193         int "Debug Consent for JSL"
 194         # USB DBC is more common for developers so make this default to 3 if
 195         # SOC_INTEL_DEBUG_CONSENT=y
 196         default 3 if SOC_INTEL_DEBUG_CONSENT
 197         default 0
 198         help
 199           This is to control debug interface on SOC.
 200           Setting non-zero value will allow to use DBC or DCI to debug SOC.
 201           PlatformDebugConsent in FspmUpd.h has the details.
 202
 203           Desired platform debug type are
 204           0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
 205           3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
 206           6:Enable (2-wire DCI OOB), 7:Manual
 207
 208 config PRERAM_CBMEM_CONSOLE_SIZE
 209         hex
 210         default 0x1400
 211
 212 config INTEL_GMA_BCLV_OFFSET
 213         default 0xc8258
 214
 215 config INTEL_GMA_BCLV_WIDTH
 216         default 32
 217
 218 config INTEL_GMA_BCLM_OFFSET
 219         default 0xc8254
 220
 221 config INTEL_GMA_BCLM_WIDTH
 222         default 32
 223 endif