src/soc/intel/meteorlake/finalize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <bootstate.h>
   5 #include <console/console.h>
   6 #include <cpu/x86/smm.h>
   7 #include <delay.h>
   8 #include <device/pci.h>
   9 #include <gpio.h>
  10 #include <intelblocks/cse.h>
  11 #include <intelblocks/lpc_lib.h>
  12 #include <intelblocks/pcr.h>
  13 #include <intelblocks/pmclib.h>
  14 #include <intelblocks/systemagent.h>
  15 #include <intelblocks/tco.h>
  16 #include <intelblocks/thermal.h>
  17 #include <spi-generic.h>
  18 #include <intelpch/lockdown.h>
  19 #include <soc/p2sb.h>
  20 #include <soc/pci_devs.h>
  21 #include <soc/pcr_ids.h>
  22 #include <soc/pm.h>
  23 #include <soc/smbus.h>
  24 #include <soc/soc_chip.h>
  25 #include <soc/systemagent.h>
  26 #include <timer.h>
  27
  28 static void pch_handle_sideband(config_t *config)
  29 {
  30
  31 }
  32
  33 static void pch_finalize(void)
  34 {
  35         config_t *config = config_of_soc();
  36
  37         /* TCO Lock down */
  38         tco_lockdown();
  39
  40         /* TODO: Add Thermal Configuration */
  41
  42         pch_handle_sideband(config);
  43
  44         pmc_clear_pmcon_sts();
  45 }
  46
  47 static void tbt_finalize(void)
  48 {
  49         int i;
  50         const struct device *dev;
  51
  52         /* Disable Thunderbolt PCIe root ports bus master */
  53         for (i = 0; i < NUM_TBT_FUNCTIONS; i++) {
  54                 dev = pcidev_path_on_root(PCI_DEVFN_TBT(i));
  55                 if (dev)
  56                         pci_dev_disable_bus_master(dev);
  57         }
  58 }
  59
  60 static void sa_finalize(void)
  61 {
  62         if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT)
  63                 sa_lock_pam();
  64 }
  65
  66 static void heci_finalize(void)
  67 {
  68         heci_set_to_d0i3();
  69         if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
  70                 heci1_disable();
  71 }
  72
  73 static void soc_finalize(void *unused)
  74 {
  75         printk(BIOS_DEBUG, "Finalizing chipset.\n");
  76
  77         pch_finalize();
  78         apm_control(APM_CNT_FINALIZE);
  79         tbt_finalize();
  80         sa_finalize();
  81         if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) &&
  82                          CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
  83                 heci_finalize();
  84
  85         /* Indicate finalize step with post code */
  86         post_code(POSTCODE_OS_BOOT);
  87 }
  88
  89 BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
  90 /*
  91  * The purpose of this change is to accommodate more time to push out sending
  92  * CSE EOP messages at post.
  93  */
  94 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, soc_finalize, NULL);