src/arch/arm/armv7/cache.c

   1 /* SPDX-License-Identifier: BSD-3-Clause */
   2 /*
   3  * cache.c: Cache maintenance routines for ARMv7-A and ARMv7-R
   4  *
   5  * Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition
   6  */
   7
   8 #include <stdint.h>
   9
  10 #include <arch/cache.h>
  11 #include <program_loading.h>
  12
  13 void tlb_invalidate_all(void)
  14 {
  15         /* TLBIALL includes dTLB and iTLB on systems that have them. */
  16         tlbiall();
  17         dsb();
  18         isb();
  19 }
  20
  21 enum dcache_op {
  22         OP_DCCSW,
  23         OP_DCCISW,
  24         OP_DCISW,
  25         OP_DCCIMVAC,
  26         OP_DCCMVAC,
  27         OP_DCIMVAC,
  28 };
  29
  30 unsigned int dcache_line_bytes(void)
  31 {
  32         uint32_t ccsidr;
  33         static unsigned int line_bytes = 0;
  34
  35         if (line_bytes)
  36                 return line_bytes;
  37
  38         ccsidr = read_ccsidr();
  39         /* [2:0] - Indicates (Log2(number of words in cache line)) - 2 */
  40         line_bytes = 1 << ((ccsidr & 0x7) + 2); /* words per line */
  41         line_bytes *= sizeof(unsigned int);     /* bytes per line */
  42
  43         return line_bytes;
  44 }
  45
  46 /*
  47  * Do a dcache operation by modified virtual address. This is useful for
  48  * maintaining coherency in drivers which do DMA transfers and only need to
  49  * perform cache maintenance on a particular memory range rather than the
  50  * entire cache.
  51  */
  52 static void dcache_op_mva(void const *addr, size_t len, enum dcache_op op)
  53 {
  54         unsigned long line, linesize;
  55
  56         linesize = dcache_line_bytes();
  57         line = (uint32_t)addr & ~(linesize - 1);
  58
  59         dsb();
  60         while ((void *)line < addr + len) {
  61                 switch (op) {
  62                 case OP_DCCIMVAC:
  63                         dccimvac(line);
  64                         break;
  65                 case OP_DCCMVAC:
  66                         dccmvac(line);
  67                         break;
  68                 case OP_DCIMVAC:
  69                         dcimvac(line);
  70                         break;
  71                 default:
  72                         break;
  73                 }
  74                 line += linesize;
  75         }
  76         isb();
  77 }
  78
  79 void dcache_clean_by_mva(void const *addr, size_t len)
  80 {
  81         dcache_op_mva(addr, len, OP_DCCMVAC);
  82 }
  83
  84 void dcache_clean_invalidate_by_mva(void const *addr, size_t len)
  85 {
  86         dcache_op_mva(addr, len, OP_DCCIMVAC);
  87 }
  88
  89 void dcache_invalidate_by_mva(void const *addr, size_t len)
  90 {
  91         dcache_op_mva(addr, len, OP_DCIMVAC);
  92 }
  93
  94 /*
  95  * CAUTION: This implementation assumes that coreboot never uses non-identity
  96  * page tables for pages containing executed code. If you ever want to violate
  97  * this assumption, have fun figuring out the associated problems on your own.
  98  */
  99 void dcache_mmu_disable(void)
 100 {
 101         uint32_t sctlr;
 102
 103         dcache_clean_invalidate_all();
 104         sctlr = read_sctlr();
 105         sctlr &= ~(SCTLR_C | SCTLR_M);
 106         write_sctlr(sctlr);
 107 }
 108
 109 void dcache_mmu_enable(void)
 110 {
 111         uint32_t sctlr;
 112
 113         sctlr = read_sctlr();
 114         sctlr |= SCTLR_C | SCTLR_M;
 115         write_sctlr(sctlr);
 116 }
 117
 118 void cache_sync_instructions(void)
 119 {
 120         uint32_t sctlr;
 121
 122         sctlr = read_sctlr();
 123
 124         if (sctlr & SCTLR_C)
 125                 dcache_clean_all();
 126         else if (sctlr & SCTLR_I)
 127                 dcache_clean_invalidate_all();
 128
 129         iciallu();              /* includes BPIALLU (architecturally) */
 130         dsb();
 131         isb();
 132 }
 133
 134 /*
 135  * For each segment of a program loaded this function is called
 136  * to invalidate caches for the addresses of the loaded segment
 137  */
 138 void arch_segment_loaded(uintptr_t start, size_t size, int flags)
 139 {
 140         cache_sync_instructions();
 141 }