src/arch/x86/mpspec.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <arch/ioapic.h>
   5 #include <arch/smp/mpspec.h>
   6 #include <console/console.h>
   7 #include <cpu/cpu.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <device/device.h>
  10 #include <device/pci_def.h>
  11 #include <device/pci_ids.h>
  12 #include <identity.h>
  13 #include <string.h>
  14 #include <types.h>
  15
  16 /* Initialize the specified "mc" struct with initial values. */
  17 void mptable_init(struct mp_config_table *mc)
  18 {
  19         int i;
  20         u32 lapic_addr = cpu_get_lapic_addr();
  21
  22         memset(mc, 0, sizeof(*mc));
  23
  24         memcpy(mc->mpc_signature, MPC_SIGNATURE, 4);
  25
  26         mc->mpc_length = sizeof(*mc);   /* Initially just the header size. */
  27         mc->mpc_spec = 0x04;            /* MultiProcessor specification 1.4 */
  28         mc->mpc_checksum = 0;           /* Not yet computed. */
  29         mc->mpc_oemptr = 0;
  30         mc->mpc_oemsize = 0;
  31         mc->mpc_entry_count = 0;        /* No entries yet... */
  32         mc->mpc_lapic = lapic_addr;
  33         mc->mpe_length = 0;
  34         mc->mpe_checksum = 0;
  35         mc->reserved = 0;
  36
  37         strncpy(mc->mpc_oem, mainboard_vendor, 8);
  38         strncpy(mc->mpc_productid, mainboard_part_number, 12);
  39
  40         /*
  41          * The oem/productid fields are exactly 8/12 bytes long. If the resp.
  42          * entry is shorter, the remaining bytes are filled with spaces.
  43          */
  44         for (i = MIN(strlen(mainboard_vendor), 8); i < 8; i++)
  45                 mc->mpc_oem[i] = ' ';
  46         for (i = MIN(strlen(mainboard_part_number), 12); i < 12; i++)
  47                 mc->mpc_productid[i] = ' ';
  48 }
  49
  50 static unsigned char smp_compute_checksum(void *v, int len)
  51 {
  52         unsigned char *bytes;
  53         unsigned char checksum;
  54         int i;
  55         bytes = v;
  56         checksum = 0;
  57         for (i = 0; i < len; i++)
  58                 checksum -= bytes[i];
  59         return checksum;
  60 }
  61
  62 static void *smp_write_floating_table_physaddr(uintptr_t addr,
  63         uintptr_t mpf_physptr, unsigned int virtualwire)
  64 {
  65         struct intel_mp_floating *mf;
  66         void *v;
  67
  68         v = (void *)addr;
  69         mf = v;
  70         mf->mpf_signature[0] = '_';
  71         mf->mpf_signature[1] = 'M';
  72         mf->mpf_signature[2] = 'P';
  73         mf->mpf_signature[3] = '_';
  74         mf->mpf_physptr = mpf_physptr;
  75         mf->mpf_length = 1;
  76         mf->mpf_specification = 4;
  77         mf->mpf_checksum = 0;
  78         mf->mpf_feature1 = 0;
  79         mf->mpf_feature2 = virtualwire?MP_FEATURE_PIC:MP_FEATURE_VIRTUALWIRE;
  80         mf->mpf_feature3 = 0;
  81         mf->mpf_feature4 = 0;
  82         mf->mpf_feature5 = 0;
  83         mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16);
  84         return v;
  85 }
  86
  87 void *smp_write_floating_table(unsigned long addr, unsigned int virtualwire)
  88 {
  89         /* 16 byte align the table address */
  90         addr = (addr + 0xf) & (~0xf);
  91         return smp_write_floating_table_physaddr(addr, addr
  92                 + SMP_FLOATING_TABLE_LEN, virtualwire);
  93 }
  94
  95 void *smp_next_mpc_entry(struct mp_config_table *mc)
  96 {
  97         void *v;
  98         v = (void *)(((char *)mc) + mc->mpc_length);
  99
 100         return v;
 101 }
 102 static void smp_add_mpc_entry(struct mp_config_table *mc, u16 length)
 103 {
 104         mc->mpc_length += length;
 105         mc->mpc_entry_count++;
 106 }
 107
 108 void *smp_next_mpe_entry(struct mp_config_table *mc)
 109 {
 110         void *v;
 111         v = (void *)(((char *)mc) + mc->mpc_length + mc->mpe_length);
 112
 113         return v;
 114 }
 115 static void smp_add_mpe_entry(struct mp_config_table *mc, mpe_t mpe)
 116 {
 117         mc->mpe_length += mpe->mpe_length;
 118 }
 119
 120 /*
 121  * Type 0: Processor Entries:
 122  * Entry Type, LAPIC ID, LAPIC Version, CPU Flags EN/BP,
 123  * CPU Signature (Stepping, Model, Family), Feature Flags
 124  */
 125 void smp_write_processor(struct mp_config_table *mc,
 126         u8 apicid, u8 apicver, u8 cpuflag,
 127         u32 cpufeature, u32 featureflag)
 128 {
 129         struct mpc_config_processor *mpc;
 130         mpc = smp_next_mpc_entry(mc);
 131         memset(mpc, '\0', sizeof(*mpc));
 132         mpc->mpc_type = MP_PROCESSOR;
 133         mpc->mpc_apicid = apicid;
 134         mpc->mpc_apicver = apicver;
 135         mpc->mpc_cpuflag = cpuflag;
 136         mpc->mpc_cpufeature = cpufeature;
 137         mpc->mpc_featureflag = featureflag;
 138         smp_add_mpc_entry(mc, sizeof(*mpc));
 139 }
 140
 141 /*
 142  * If we assume a symmetric processor configuration we can
 143  * get all of the information we need to write the processor
 144  * entry from the bootstrap processor.
 145  * Plus I don't think linux really even cares.
 146  * Having the proper apicid's in the table so the non-bootstrap
 147  *  processors can be woken up should be enough.
 148  */
 149 void smp_write_processors(struct mp_config_table *mc)
 150 {
 151         int boot_apic_id;
 152         int order_id;
 153         unsigned int apic_version;
 154         unsigned int cpu_features;
 155         unsigned int cpu_feature_flags;
 156         struct device *cpu;
 157
 158         boot_apic_id = lapicid();
 159         apic_version = lapic_read(LAPIC_LVR) & 0xff;
 160         cpu_features = cpu_get_cpuid();
 161         cpu_feature_flags = cpu_get_feature_flags_edx();
 162         /* order the output of the cpus to fix a bug in kernel 2.6.11 */
 163         for (order_id = 0; order_id < 256; order_id++) {
 164                 for (cpu = all_devices; cpu; cpu = cpu->next) {
 165                         unsigned long cpu_flag;
 166                         if (!is_enabled_cpu(cpu))
 167                                 continue;
 168
 169                         cpu_flag = MPC_CPU_ENABLED;
 170
 171                         if (boot_apic_id == cpu->path.apic.apic_id)
 172                                 cpu_flag = MPC_CPU_ENABLED
 173                                         | MPC_CPU_BOOTPROCESSOR;
 174
 175                         if (cpu->path.apic.apic_id == order_id) {
 176                                 smp_write_processor(mc,
 177                                         cpu->path.apic.apic_id, apic_version,
 178                                         cpu_flag, cpu_features,
 179                                         cpu_feature_flags
 180                                 );
 181                                 break;
 182                         }
 183                 }
 184         }
 185 }
 186
 187 /*
 188  * Type 1: Bus Entries:
 189  * Entry Type, Bus ID, Bus Type
 190  */
 191 static void smp_write_bus(struct mp_config_table *mc,
 192         u8 id, const char *bustype)
 193 {
 194         struct mpc_config_bus *mpc;
 195         mpc = smp_next_mpc_entry(mc);
 196         memset(mpc, '\0', sizeof(*mpc));
 197         mpc->mpc_type = MP_BUS;
 198         mpc->mpc_busid = id;
 199         memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
 200         smp_add_mpc_entry(mc, sizeof(*mpc));
 201 }
 202
 203 /*
 204  * Type 2: I/O APIC Entries:
 205  * Entry Type, APIC ID, Version,
 206  * APIC Flags:EN, Address
 207  */
 208 static void smp_write_ioapic(struct mp_config_table *mc,
 209         u8 id, u8 ver, uintptr_t apicaddr)
 210 {
 211         struct mpc_config_ioapic *mpc;
 212         mpc = smp_next_mpc_entry(mc);
 213         memset(mpc, '\0', sizeof(*mpc));
 214         mpc->mpc_type = MP_IOAPIC;
 215         mpc->mpc_apicid = id;
 216         mpc->mpc_apicver = ver;
 217         mpc->mpc_flags = MPC_APIC_USABLE;
 218         mpc->mpc_apicaddr = apicaddr;
 219         smp_add_mpc_entry(mc, sizeof(*mpc));
 220 }
 221
 222 u8 smp_write_ioapic_from_hw(struct mp_config_table *mc, uintptr_t apicaddr)
 223 {
 224         u8 id = get_ioapic_id(apicaddr);
 225         u8 ver = get_ioapic_version(apicaddr);
 226         smp_write_ioapic(mc, id, ver, apicaddr);
 227         return id;
 228 }
 229
 230 /*
 231  * Type 3: I/O Interrupt Table Entries:
 232  * Entry Type, Int Type, Int Polarity, Int Level,
 233  * Source Bus ID, Source Bus IRQ, Dest APIC ID, Dest PIN#
 234  */
 235 void smp_write_intsrc(struct mp_config_table *mc,
 236         u8 irqtype, u16 irqflag,
 237         u8 srcbus, u8 srcbusirq,
 238         u8 dstapic, u8 dstirq)
 239 {
 240         struct mpc_config_intsrc *mpc;
 241         mpc = smp_next_mpc_entry(mc);
 242         memset(mpc, '\0', sizeof(*mpc));
 243         mpc->mpc_type = MP_INTSRC;
 244         mpc->mpc_irqtype = irqtype;
 245         mpc->mpc_irqflag = irqflag;
 246         mpc->mpc_srcbus = srcbus;
 247         mpc->mpc_srcbusirq = srcbusirq;
 248         mpc->mpc_dstapic = dstapic;
 249         mpc->mpc_dstirq = dstirq;
 250         smp_add_mpc_entry(mc, sizeof(*mpc));
 251 }
 252
 253 /*
 254  * Type 3: I/O Interrupt Table Entries for PCI Devices:
 255  * This has the same fields as 'Type 3: I/O Interrupt Table Entries'
 256  * but the Source Bus IRQ field has a slightly different
 257  * definition:
 258  * Bits 1-0: PIRQ pin: INT_A# = 0, INT_B# = 1, INT_C# = 2, INT_D# = 3
 259  * Bits 2-6: Originating PCI Device Number (Not its parent bridge device number)
 260  * Bit 7: Reserved
 261  */
 262 void smp_write_pci_intsrc(struct mp_config_table *mc,
 263         u8 irqtype, u8 srcbus, u8 dev, u8 pirq,
 264         u8 dstapic, u8 dstirq)
 265 {
 266         u8 srcbusirq = (dev << 2) | pirq;
 267         printk(BIOS_SPEW,
 268                 "\tPCI srcbusirq = 0x%x from dev = 0x%x and pirq = %x\n",
 269                 srcbusirq, dev, pirq);
 270         smp_write_intsrc(mc, irqtype, MP_IRQ_TRIGGER_LEVEL
 271                 | MP_IRQ_POLARITY_LOW, srcbus, srcbusirq, dstapic, dstirq);
 272 }
 273
 274 void smp_write_intsrc_pci_bridge(struct mp_config_table *mc,
 275         u8 irqtype, u16 irqflag, struct device *dev,
 276         unsigned char dstapic, unsigned char *dstirq)
 277 {
 278         struct device *child;
 279
 280         int i;
 281         int srcbus;
 282         int slot;
 283
 284         unsigned char dstirq_x[4];
 285
 286         if (!dev->downstream)
 287                 return;
 288
 289         child = dev->downstream->children;
 290         srcbus = dev->downstream->secondary;
 291
 292         while (child) {
 293                 if (child->path.type != DEVICE_PATH_PCI)
 294                         goto next;
 295
 296                 slot = (child->path.pci.devfn >> 3);
 297                 /* round pins */
 298                 for (i = 0; i < 4; i++)
 299                         dstirq_x[i] = dstirq[(i + slot) % 4];
 300
 301                 if ((child->class >> 16) != PCI_BASE_CLASS_BRIDGE) {
 302                         /* pci device */
 303                         printk(BIOS_DEBUG, "route irq: %s\n",
 304                                dev_path(child));
 305                         for (i = 0; i < 4; i++)
 306                                 smp_write_intsrc(mc, irqtype, irqflag,
 307                                                  srcbus, (slot<<2)|i, dstapic,
 308                                                  dstirq_x[i]);
 309                         goto next;
 310                 }
 311
 312                 switch (child->class>>8) {
 313                 case PCI_CLASS_BRIDGE_PCI:
 314                 case PCI_CLASS_BRIDGE_PCMCIA:
 315                 case PCI_CLASS_BRIDGE_CARDBUS:
 316                         printk(BIOS_DEBUG, "route irq bridge: %s\n",
 317                                dev_path(child));
 318                         smp_write_intsrc_pci_bridge(mc, irqtype,
 319                                                     irqflag, child, dstapic, dstirq_x);
 320                 }
 321
 322 next:
 323                 child = child->sibling;
 324         }
 325 }
 326
 327 /*
 328  * Type 4: Local Interrupt Assignment Entries:
 329  * Entry Type, Int Type, Int Polarity, Int Level,
 330  * Source Bus ID, Source Bus IRQ, Dest LAPIC ID,
 331  * Dest LAPIC LINTIN#
 332  */
 333 void smp_write_lintsrc(struct mp_config_table *mc,
 334         u8 irqtype, u16 irqflag,
 335         u8 srcbusid, u8 srcbusirq,
 336         u8 destapic, u8 destapiclint)
 337 {
 338         struct mpc_config_lintsrc *mpc;
 339         mpc = smp_next_mpc_entry(mc);
 340         memset(mpc, '\0', sizeof(*mpc));
 341         mpc->mpc_type = MP_LINTSRC;
 342         mpc->mpc_irqtype = irqtype;
 343         mpc->mpc_irqflag = irqflag;
 344         mpc->mpc_srcbusid = srcbusid;
 345         mpc->mpc_srcbusirq = srcbusirq;
 346         mpc->mpc_destapic = destapic;
 347         mpc->mpc_destapiclint = destapiclint;
 348         smp_add_mpc_entry(mc, sizeof(*mpc));
 349 }
 350
 351 /*
 352  * Type 128: System Address Space Mapping Entries
 353  * Entry Type, Entry Length, Bus ID, Address Type,
 354  * Address Base Lo/Hi, Address Length Lo/Hi
 355  */
 356 void smp_write_address_space(struct mp_config_table *mc,
 357         u8 busid, u8 address_type,
 358         u32 address_base_low, u32 address_base_high,
 359         u32 address_length_low, u32 address_length_high)
 360 {
 361         struct mp_exten_system_address_space *mpe;
 362         mpe = smp_next_mpe_entry(mc);
 363         memset(mpe, '\0', sizeof(*mpe));
 364         mpe->mpe_type = MPE_SYSTEM_ADDRESS_SPACE;
 365         mpe->mpe_length = sizeof(*mpe);
 366         mpe->mpe_busid = busid;
 367         mpe->mpe_address_type = address_type;
 368         mpe->mpe_address_base_low  = address_base_low;
 369         mpe->mpe_address_base_high = address_base_high;
 370         mpe->mpe_address_length_low  = address_length_low;
 371         mpe->mpe_address_length_high = address_length_high;
 372         smp_add_mpe_entry(mc, (mpe_t)mpe);
 373 }
 374
 375 /*
 376  * Type 129: Bus Hierarchy Descriptor Entry
 377  * Entry Type, Entry Length, Bus ID, Bus Info,
 378  * Parent Bus ID
 379  */
 380 void smp_write_bus_hierarchy(struct mp_config_table *mc,
 381         u8 busid, u8 bus_info, u8 parent_busid)
 382 {
 383         struct mp_exten_bus_hierarchy *mpe;
 384         mpe = smp_next_mpe_entry(mc);
 385         memset(mpe, '\0', sizeof(*mpe));
 386         mpe->mpe_type = MPE_BUS_HIERARCHY;
 387         mpe->mpe_length = sizeof(*mpe);
 388         mpe->mpe_busid = busid;
 389         mpe->mpe_bus_info = bus_info;
 390         mpe->mpe_parent_busid = parent_busid;
 391         smp_add_mpe_entry(mc, (mpe_t)mpe);
 392 }
 393
 394 /*
 395  * Type 130: Compatibility Bus Address Space Modifier Entry
 396  * Entry Type, Entry Length, Bus ID, Address Modifier
 397  * Predefined Range List
 398  */
 399 void smp_write_compatibility_address_space(struct mp_config_table *mc,
 400         u8 busid, u8 address_modifier,
 401         u32 range_list)
 402 {
 403         struct mp_exten_compatibility_address_space *mpe;
 404         mpe = smp_next_mpe_entry(mc);
 405         memset(mpe, '\0', sizeof(*mpe));
 406         mpe->mpe_type = MPE_COMPATIBILITY_ADDRESS_SPACE;
 407         mpe->mpe_length = sizeof(*mpe);
 408         mpe->mpe_busid = busid;
 409         mpe->mpe_address_modifier = address_modifier;
 410         mpe->mpe_range_list = range_list;
 411         smp_add_mpe_entry(mc, (mpe_t)mpe);
 412 }
 413
 414 void mptable_lintsrc(struct mp_config_table *mc, unsigned long bus_isa)
 415 {
 416         smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE
 417                 | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
 418         smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE
 419                 | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
 420 }
 421
 422 void mptable_add_isa_interrupts(struct mp_config_table *mc,
 423         unsigned long bus_isa, unsigned long apicid, int external_int2)
 424 {
 425 /*I/O Ints:                   Type         Trigger            Polarity
 426  *                                   Bus ID   IRQ  APIC ID   PIN# */
 427         smp_write_intsrc(mc, external_int2?mp_INT:mp_ExtINT,
 428                                      MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 429                                      bus_isa, 0x0, apicid, 0x0);
 430         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 431                                      bus_isa, 0x1, apicid, 0x1);
 432         smp_write_intsrc(mc, external_int2?mp_ExtINT:mp_INT,
 433                                      MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 434                                      bus_isa, 0x0, apicid, 0x2);
 435         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 436                                      bus_isa, 0x3, apicid, 0x3);
 437         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 438                                      bus_isa, 0x4, apicid, 0x4);
 439         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 440                                      bus_isa, 0x6, apicid, 0x6);
 441         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 442                                      bus_isa, 0x7, apicid, 0x7);
 443         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 444                                      bus_isa, 0x8, apicid, 0x8);
 445         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 446                                      bus_isa, 0x9, apicid, 0x9);
 447         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 448                                      bus_isa, 0xa, apicid, 0xa);
 449         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 450                                      bus_isa, 0xb, apicid, 0xb);
 451         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 452                                      bus_isa, 0xc, apicid, 0xc);
 453         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 454                                      bus_isa, 0xd, apicid, 0xd);
 455         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 456                                      bus_isa, 0xe, apicid, 0xe);
 457         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
 458                                      bus_isa, 0xf, apicid, 0xf);
 459 }
 460
 461 void mptable_write_buses(struct mp_config_table *mc, int *max_pci_bus,
 462         int *isa_bus)
 463 {
 464         int dummy, i, highest;
 465         char buses[256];
 466         struct device *dev;
 467
 468         if (!max_pci_bus)
 469                 max_pci_bus = &dummy;
 470         if (!isa_bus)
 471                 isa_bus = &dummy;
 472
 473         *max_pci_bus = 0;
 474         highest = 0;
 475         memset(buses, 0, sizeof(buses));
 476
 477         for (dev = all_devices; dev; dev = dev->next) {
 478                 struct bus *bus = dev->downstream;
 479                 if (!bus)
 480                         continue;
 481                 if (bus->secondary > 255) {
 482                         printk(BIOS_ERR, "A bus claims to have a bus ID > 255?!? Aborting\n");
 483                         return;
 484                 }
 485                 buses[bus->secondary] = 1;
 486                 if (highest < bus->secondary)
 487                         highest = bus->secondary;
 488         }
 489         for (i = 0; i <= highest; i++) {
 490                 if (buses[i]) {
 491                         smp_write_bus(mc, i, "PCI   ");
 492                         *max_pci_bus = i;
 493                 }
 494         }
 495         *isa_bus = *max_pci_bus + 1;
 496         smp_write_bus(mc, *isa_bus, "ISA   ");
 497 }
 498
 499 void *mptable_finalize(struct mp_config_table *mc)
 500 {
 501         mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc),
 502                 mc->mpe_length);
 503         mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 504         printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 505                 mc, smp_next_mpe_entry(mc));
 506         return smp_next_mpe_entry(mc);
 507 }