src/cpu/x86/smm/tseg_region.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <assert.h>
   4 #include <commonlib/helpers.h>
   5 #include <console/console.h>
   6 #include <cpu/x86/smm.h>
   7 #include <stage_cache.h>
   8 #include <types.h>
   9 #include <inttypes.h>
  10
  11 /*
  12  *        Subregions within SMM
  13  *     +-------------------------+
  14  *     |          IED            | IED_REGION_SIZE
  15  *     +-------------------------+
  16  *     |  External Stage Cache   | SMM_RESERVED_SIZE
  17  *     +-------------------------+
  18  *     |      code and data      |
  19  *     |         (TSEG)          |
  20  *     +-------------------------+ TSEG
  21  */
  22 int smm_subregion(int sub, uintptr_t *start, size_t *size)
  23 {
  24         uintptr_t sub_base;
  25         size_t sub_size;
  26         const size_t ied_size = CONFIG_IED_REGION_SIZE;
  27         const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
  28
  29         if (CONFIG(SMM_TSEG))
  30                 smm_region(&sub_base, &sub_size);
  31         else if (CONFIG(SMM_ASEG))
  32                 aseg_region(&sub_base, &sub_size);
  33         else
  34                 return -1;
  35
  36         ASSERT(IS_ALIGNED(sub_base, sub_size));
  37         ASSERT(sub_size > (cache_size + ied_size));
  38
  39         switch (sub) {
  40         case SMM_SUBREGION_HANDLER:
  41                 /* Handler starts at the base of TSEG. */
  42                 sub_size -= ied_size;
  43                 sub_size -= cache_size;
  44                 break;
  45         case SMM_SUBREGION_CACHE:
  46                 /* External cache is in the middle of TSEG. */
  47                 sub_base += sub_size - (ied_size + cache_size);
  48                 sub_size = cache_size;
  49                 break;
  50         case SMM_SUBREGION_CHIPSET:
  51                 /* IED is at the top. */
  52                 sub_base += sub_size - ied_size;
  53                 sub_size = ied_size;
  54                 break;
  55         default:
  56                 return -1;
  57         }
  58
  59         *start = sub_base;
  60         *size = sub_size;
  61         return 0;
  62 }
  63
  64 void stage_cache_external_region(void **base, size_t *size)
  65 {
  66         *base = NULL;
  67         *size = 0;
  68         if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size))
  69                 printk(BIOS_ERR, "No cache SMM subregion.\n");
  70 }
  71
  72 void smm_list_regions(void)
  73 {
  74         uintptr_t base;
  75         size_t size;
  76         int i;
  77
  78         smm_region(&base, &size);
  79         if (!size)
  80                 return;
  81
  82         printk(BIOS_DEBUG, "SMM Memory Map\n");
  83         printk(BIOS_DEBUG, "SMRAM       : 0x%" PRIxPTR " 0x%zx\n", base, size);
  84
  85         for (i = 0; i < SMM_SUBREGION_NUM; i++) {
  86                 if (smm_subregion(i, &base, &size))
  87                         continue;
  88                 printk(BIOS_DEBUG, " Subregion %d: 0x%" PRIxPTR " 0x%zx\n", i, base, size);
  89         }
  90 }