src/soc/cavium/cn81xx/clock.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 #include <soc/clock.h>
   3 #include <device/mmio.h>
   4 #include <soc/addressmap.h>
   5
   6 #define PLL_REF_CLK     50000000        /* 50 MHz */
   7
   8 union cavm_rst_boot {
   9         u64 u;
  10         struct {
  11                 u64 rboot_pin:1;
  12                 u64 rboot:1;
  13                 u64 lboot:10;
  14                 u64 lboot_ext23:6;
  15                 u64 lboot_ext45:6;
  16                 u64 reserved_24_29:6;
  17                 u64 lboot_oci:3;
  18                 u64 pnr_mul:6;
  19                 u64 reserved_39_39:1;
  20                 u64 c_mul:7;
  21                 u64 reserved_47_54:8;
  22                 u64 dis_scan:1;
  23                 u64 dis_huk:1;
  24                 u64 vrm_err:1;
  25                 u64 jt_tstmode:1;
  26                 u64 ckill_ppdis:1;
  27                 u64 trusted_mode:1;
  28                 u64 ejtagdis:1;
  29                 u64 jtcsrdis:1;
  30                 u64 chipkill:1;
  31         } s;
  32 };
  33
  34 /**
  35  * Returns the reference clock speed in Hz
  36  */
  37 u64 thunderx_get_ref_clock(void)
  38 {
  39         return PLL_REF_CLK;
  40 }
  41
  42 /**
  43  * Returns the I/O clock speed in Hz
  44  */
  45 u64 thunderx_get_io_clock(void)
  46 {
  47         union cavm_rst_boot rst_boot;
  48
  49         rst_boot.u = read64p(RST_PF_BAR0);
  50
  51         return ((u64)rst_boot.s.pnr_mul) * PLL_REF_CLK;
  52 }
  53
  54 /**
  55  * Returns the core clock speed in Hz
  56  */
  57 u64 thunderx_get_core_clock(void)
  58 {
  59         union cavm_rst_boot rst_boot;
  60
  61         rst_boot.u = read64p(RST_PF_BAR0);
  62
  63         return ((u64)rst_boot.s.c_mul) * PLL_REF_CLK;
  64 }