src/soc/mediatek/common/ddp.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <edid.h>
   5 #include <soc/addressmap.h>
   6 #include <soc/ddp.h>
   7 #include <types.h>
   8
   9 #define RDMA_FIFO_PSEUDO_SIZE(bytes)            (((bytes) / 16) << 16)
  10 #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
  11
  12 void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color)
  13 {
  14         write32(&disp_ovl[idx]->roi_size, height << 16 | width);
  15         write32(&disp_ovl[idx]->roi_bgclr, color);
  16 }
  17
  18 void rdma_start(void)
  19 {
  20         setbits32(&disp_rdma0->global_con, RDMA_ENGINE_EN);
  21 }
  22
  23 void rdma_config(u32 width, u32 height, u32 pixel_clk, u32 fifo_size)
  24 {
  25         u32 threshold;
  26         u32 reg;
  27
  28         clrsetbits32(&disp_rdma0->size_con_0, 0x1FFF, width);
  29         clrsetbits32(&disp_rdma0->size_con_1, 0xFFFFF, height);
  30
  31         /*
  32          * Enable FIFO underflow since DSI and DPI can't be blocked. Set the
  33          * output threshold to 6 microseconds with 7/6 overhead to account for
  34          * blanking, and with a pixel depth of 4 bytes:
  35          */
  36         threshold = pixel_clk * 4 * 7 / 1000;
  37
  38         if (threshold > fifo_size)
  39                 threshold = fifo_size;
  40
  41         reg = RDMA_FIFO_UNDERFLOW_EN | RDMA_FIFO_PSEUDO_SIZE(fifo_size) |
  42               RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
  43
  44         write32(&disp_rdma0->fifo_con, reg);
  45 }
  46
  47 void color_start(u32 width, u32 height)
  48 {
  49         write32(&disp_color0->width, width);
  50         write32(&disp_color0->height, height);
  51         write32(&disp_color0->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL);
  52         write32(&disp_color0->start, BIT(0));
  53 }
  54
  55 void ovl_layer_config(u32 fmt, u32 bpp, u32 width, u32 height)
  56 {
  57         struct disp_ovl_regs *const ovl0 = disp_ovl[0];
  58         write32(&ovl0->layer[0].con, fmt << 12);
  59         write32(&ovl0->layer[0].src_size, height << 16 | width);
  60         write32(&ovl0->layer[0].pitch, (width * bpp) & 0xFFFF);
  61
  62         /* Enable layer */
  63         write32(&ovl0->rdma[0].ctrl, BIT(0));
  64         write32(&ovl0->rdma[0].mem_gmc_setting, RDMA_MEM_GMC);
  65
  66         setbits32(&ovl0->src_con, BIT(0));
  67 }