1 /* SPDX-License-Identifier: GPL-2.0-only */
6 #include <soc/mmu_operations.h>
8 __weak
void mtk_soc_after_dram(void) { /* do nothing */ }
10 void mtk_mmu_init(void)
12 static bool mmu_inited
;
22 * Set 0x0 to 16GB address as device memory. We want to config IO_PHYS
23 * address to DEV_MEM, and map a proper range of dram for the memory
24 * test during calibration.
26 mmu_config_range((void *)0, (uintptr_t)16U * GiB
, DEV_MEM
);
29 mmu_config_range(_sram
, REGION_SIZE(sram
), SECURE_CACHED_MEM
);
31 /* L2C SRAM is cached */
32 mmu_config_range(_sram_l2c
, REGION_SIZE(sram_l2c
), SECURE_CACHED_MEM
);
34 /* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */
35 mmu_config_range(_dma_coherent
, REGION_SIZE(dma_coherent
),
41 void mtk_mmu_after_dram(void)
43 /* Map DRAM as cached now that it's up and running */
44 mmu_config_range(_dram
, (uintptr_t)sdram_size(), NONSECURE_CACHED_MEM
);
49 void mtk_mmu_disable_l2c_sram(void)
51 /* Unmap L2C SRAM so it can be reclaimed by L2 cache */
52 /* TODO: Implement true unmapping, and also use it for the zero-page! */
53 mmu_config_range(_sram_l2c
, REGION_SIZE(sram_l2c
), DEV_MEM
);
55 /* Careful: changing cache geometry while it's active is a bad idea! */
58 mtk_soc_disable_l2c_sram();
60 /* Re-enable MMU with now enlarged L2 cache. Page tables still valid. */