src/soc/mediatek/mt8188/pmif_clk.c

   1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
   2
   3 #include <commonlib/helpers.h>
   4 #include <delay.h>
   5 #include <device/mmio.h>
   6 #include <soc/infracfg.h>
   7 #include <soc/pll.h>
   8 #include <soc/pll_common.h>
   9 #include <soc/pmif.h>
  10 #include <soc/pmif_clk_common.h>
  11 #include <soc/pmif_sw.h>
  12 #include <soc/pmif_spmi.h>
  13 #include <soc/spm.h>
  14
  15 /* APMIXED, ULPOSC_CTRL_SEL */
  16 DEFINE_BITFIELD(OSC1_SEL, 3, 0)
  17
  18 /* APMIXED, ULPOSC1_CON0 */
  19 DEFINE_BITFIELD(OSC1_CALI, 6, 0)
  20 DEFINE_BITFIELD(OSC1_IBAND, 13, 7)
  21 DEFINE_BITFIELD(OSC1_FBAND, 17, 14)
  22 DEFINE_BITFIELD(OSC1_DIV, 23, 18)
  23 DEFINE_BIT(OSC1_CP_EN, 24)
  24
  25 /* APMIXED, ULPOSC1_CON1 */
  26 DEFINE_BITFIELD(OSC1_32KCALI, 7, 0)
  27 DEFINE_BITFIELD(OSC1_RSV1, 15, 8)
  28 DEFINE_BITFIELD(OSC1_RSV2, 23, 16)
  29 DEFINE_BITFIELD(OSC1_MOD, 25, 24)
  30 DEFINE_BIT(OSC1_DIV2_EN, 26)
  31
  32 /* APMIXED, ULPOSC1_CON2 */
  33 DEFINE_BITFIELD(OSC1_BIAS, 7, 0)
  34
  35 /* SPM, POWERON_CONFIG_EN */
  36 DEFINE_BIT(BCLK_CG_EN, 0)
  37 DEFINE_BITFIELD(PROJECT_CODE, 31, 16)
  38
  39 /* SPM, ULPOSC_CON */
  40 DEFINE_BIT(ULPOSC_EN, 0)
  41 DEFINE_BIT(ULPOSC_CG_EN, 2)
  42
  43 /* INFRA, MODULE_SW_CG */
  44 DEFINE_BIT(PMIC_CG_TMR, 0)
  45 DEFINE_BIT(PMIC_CG_AP, 1)
  46 DEFINE_BIT(PMIC_CG_MD, 2)
  47 DEFINE_BIT(PMIC_CG_CONN, 3)
  48
  49 /* INFRA, INFRA_GLOBALCON_RST2 */
  50 DEFINE_BIT(PMIC_WRAP_SWRST, 0)
  51 DEFINE_BIT(PMICSPMI_SWRST, 14)
  52
  53 /* INFRA, PMICW_CLOCK_CTRL */
  54 DEFINE_BITFIELD(PMIC_SYSCK_26M_SEL, 3, 0)
  55
  56 /* TOPCKGEN, CLK_CFG_9 */
  57 DEFINE_BITFIELD(CLK_PWRAP_ULPOSC_SET, 2, 0)
  58 DEFINE_BIT(PDN_PWRAP_ULPOSC, 0)
  59
  60 /* TOPCKGEN, CLK_CFG_UPDATE1 */
  61 DEFINE_BIT(CLK_CFG_UPDATE1, 4)
  62
  63 /* EFUSE, CLK_MONITOR_CTRL */
  64 DEFINE_BIT(CLK_MONITOR_CTRL, 0)
  65
  66 static void pmif_ulposc_config(void)
  67 {
  68         /* ULPOSC_CTRL_SEL */
  69         SET32_BITFIELDS(&mtk_apmixed->ulposc_ctrl_sel, OSC1_SEL, 0x0F);
  70
  71         /* ULPOSC1_CON0 */
  72         SET32_BITFIELDS(&mtk_apmixed->ulposc1_con0, OSC1_CP_EN, 0, OSC1_DIV, 0x0F,
  73                         OSC1_FBAND, 0x2, OSC1_IBAND, 0x4A, OSC1_CALI, 0x7D);
  74
  75         /* ULPOSC1_CON1 */
  76         SET32_BITFIELDS(&mtk_apmixed->ulposc1_con1, OSC1_DIV2_EN, 0, OSC1_MOD, 0,
  77                         OSC1_RSV2, 0, OSC1_RSV1, 0x29, OSC1_32KCALI, 0);
  78
  79         /* ULPOSC1_CON2 */
  80         SET32_BITFIELDS(&mtk_apmixed->ulposc1_con2, OSC1_BIAS, 0x41);
  81
  82         udelay(15);
  83 }
  84
  85 u32 pmif_get_ulposc_freq_mhz(u32 cali_val)
  86 {
  87         u32 result = 0;
  88
  89         /* set calibration value */
  90         SET32_BITFIELDS(&mtk_apmixed->ulposc1_con0, OSC1_CALI, cali_val);
  91         udelay(50);
  92         result = mt_fmeter_get_freq_khz(FMETER_ABIST, FREQ_METER_ABIST_AD_OSC_CK);
  93
  94         return result / 1000;
  95 }
  96
  97 static void pmif_clockmonitor_config(bool enable)
  98 {
  99         SET32_BITFIELDS(&mtk_clk_monitor->clk_monitor_ctrl,
 100                         CLK_MONITOR_CTRL, !enable);
 101 }
 102
 103 static int pmif_init_ulposc(void)
 104 {
 105         /* calibrate ULPOSC1 */
 106         pmif_ulposc_config();
 107
 108         /* enable APB clock swinf */
 109         if (!READ32_BITFIELD(&mtk_spm->poweron_config_set, BCLK_CG_EN))
 110                 SET32_BITFIELDS(&mtk_spm->poweron_config_set, BCLK_CG_EN, 1,
 111                                 PROJECT_CODE, 0xb16);
 112
 113         /* turn on ulposc */
 114         SET32_BITFIELDS(&mtk_spm->ulposc_con, ULPOSC_EN, 1);
 115         udelay(50);
 116         SET32_BITFIELDS(&mtk_spm->ulposc_con, ULPOSC_CG_EN, 1);
 117         udelay(50);
 118
 119         return pmif_ulposc_cali(FREQ_260MHZ);
 120 }
 121
 122 int pmif_clk_init(void)
 123 {
 124         /* initialize pmif clock */
 125         pmif_clockmonitor_config(false);
 126         if (pmif_init_ulposc())
 127                 return E_NODEV;
 128         pmif_clockmonitor_config(true);
 129
 130         /* turn off pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */
 131         SET32_BITFIELDS(&mt8188_infracfg_ao->module_sw_cg_0_set, PMIC_CG_TMR, 1, PMIC_CG_AP, 1,
 132                         PMIC_CG_MD, 1, PMIC_CG_CONN, 1);
 133
 134         SET32_BITFIELDS(&mtk_topckgen->clk_cfg_9, PDN_PWRAP_ULPOSC, 0,
 135                         CLK_PWRAP_ULPOSC_SET, 0);
 136         SET32_BITFIELDS(&mtk_topckgen->clk_cfg_update1, CLK_CFG_UPDATE1, 1);
 137
 138         /* use ULPOSC1 clock */
 139         SET32_BITFIELDS(&mt8188_infracfg_ao->pmicw_clock_ctrl_clr, PMIC_SYSCK_26M_SEL, 0xf);
 140
 141         /* toggle SPI/SPMI sw reset */
 142         SET32_BITFIELDS(&mt8188_infracfg_ao->infra_globalcon_rst2_set, PMICSPMI_SWRST, 1,
 143                         PMIC_WRAP_SWRST, 1);
 144         SET32_BITFIELDS(&mt8188_infracfg_ao->infra_globalcon_rst2_clr, PMICSPMI_SWRST, 1,
 145                         PMIC_WRAP_SWRST, 1);
 146
 147         /* turn on pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */
 148         SET32_BITFIELDS(&mt8188_infracfg_ao->module_sw_cg_0_clr, PMIC_CG_TMR, 1, PMIC_CG_AP, 1,
 149                         PMIC_CG_MD, 1, PMIC_CG_CONN, 1);
 150
 151         return 0;
 152 }