src/soc/mediatek/mt8188/pmif_spmi.c

   1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
   2
   3 #include <device/mmio.h>
   4 #include <soc/iocfg.h>
   5 #include <soc/pll.h>
   6 #include <soc/pmif_spmi.h>
   7
   8 /* IOCFG_LT, DRV_CFG2 */
   9 DEFINE_BITFIELD(SPMI_SCL, 14, 12)
  10 DEFINE_BITFIELD(SPMI_SDA, 17, 15)
  11 DEFINE_BIT(SPMI_SCL_IN, 27)
  12 DEFINE_BIT(SPMI_SDA_IN, 28)
  13 DEFINE_BIT(SPMI_SCL_PU, 11)
  14 DEFINE_BIT(SPMI_SDA_PD, 12)
  15 DEFINE_BIT(SPMI_SCL_SMT, 28)
  16 DEFINE_BIT(SPMI_SDA_SMT, 28)
  17 DEFINE_BITFIELD(SPMI_TD, 19, 16)
  18 DEFINE_BITFIELD(SPMI_RD, 15, 14)
  19 DEFINE_BITFIELD(SPMI_DRI, 5, 3)
  20
  21 /* TOPRGU, WDT_SWSYSRST2 */
  22 DEFINE_BIT(SPMI_MST_RST, 23)
  23 DEFINE_BITFIELD(UNLOCK_KEY, 31, 24)
  24
  25 /* TOPCKGEN, CLK_CFG_17 */
  26 DEFINE_BITFIELD(CLK_SPMI_MST_SEL, 10, 8)
  27 DEFINE_BIT(CLK_SPMI_MST_INT, 12)
  28 DEFINE_BIT(PDN_SPMI_MST, 15)
  29
  30 /* TOPCKGEN, CLK_CFG_UPDATE2 */
  31 DEFINE_BIT(SPMI_MST_CK_UPDATE, 5)
  32
  33 const struct spmi_device spmi_dev[] = {
  34         {
  35                 .slvid = SPMI_SLAVE_6,
  36                 .type = BUCK_CPU,
  37                 .type_id = BUCK_CPU_ID,
  38         },
  39 };
  40
  41 const size_t spmi_dev_cnt = ARRAY_SIZE(spmi_dev);
  42
  43 int spmi_config_master(void)
  44 {
  45         /* Software reset */
  46         SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 1, UNLOCK_KEY, 0x88);
  47
  48         SET32_BITFIELDS(&mtk_topckgen->clk_cfg_17,
  49                         CLK_SPMI_MST_SEL, 0x3,
  50                         CLK_SPMI_MST_INT, 0,
  51                         PDN_SPMI_MST, 0);
  52         SET32_BITFIELDS(&mtk_topckgen->clk_cfg_update2, SPMI_MST_CK_UPDATE, 1);
  53
  54         /* Software reset */
  55         SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 0, UNLOCK_KEY, 0x88);
  56
  57         /* Enable SPMI */
  58         write32(&mtk_spmi_mst->mst_req_en, 1);
  59         write32(&mtk_spmi_mst->rcs_ctrl, 0x15);
  60
  61         return 0;
  62 }
  63
  64 void pmif_spmi_config(struct pmif *arb, int mstid)
  65 {
  66         u32 cmd_per;
  67
  68         /* Clear all cmd permission for per channel */
  69         write32(&arb->mtk_pmif->inf_cmd_per_0, 0);
  70         write32(&arb->mtk_pmif->inf_cmd_per_1, 0);
  71         write32(&arb->mtk_pmif->inf_cmd_per_2, 0);
  72         write32(&arb->mtk_pmif->inf_cmd_per_3, 0);
  73
  74         cmd_per = PMIF_CMD_PER_3 << 28 | PMIF_CMD_PER_3 << 24 |
  75                   PMIF_CMD_PER_3 << 20 | PMIF_CMD_PER_3 << 16 |
  76                   PMIF_CMD_PER_3 << 8 | PMIF_CMD_PER_3 << 4 |
  77                   PMIF_CMD_PER_1_3 << 0;
  78         write32(&arb->mtk_pmif->inf_cmd_per_0, cmd_per);
  79
  80         cmd_per = PMIF_CMD_PER_3 << 8 | PMIF_CMD_PER_3 << 4;
  81         write32(&arb->mtk_pmif->inf_cmd_per_1, cmd_per);
  82 }
  83
  84 void pmif_spmi_iocfg(void)
  85 {
  86         SET32_BITFIELDS(&mtk_iocfg_lt->eh_cfg_clr, SPMI_SCL, 0x7, SPMI_SDA, 0x7);
  87         SET32_BITFIELDS(&mtk_iocfg_lt->ies_cfg1_clr, SPMI_SCL_IN, 0x1);
  88         SET32_BITFIELDS(&mtk_iocfg_lt->ies_cfg1_set, SPMI_SDA_IN, 0x1);
  89         SET32_BITFIELDS(&mtk_iocfg_lt->pu_cfg1_clr, SPMI_SCL_PU, 0x1,
  90                         SPMI_SDA_PD, 0x1);
  91         SET32_BITFIELDS(&mtk_iocfg_lt->pd_cfg1_clr, SPMI_SCL_PU, 0x1,
  92                         SPMI_SDA_PD, 0x1);
  93         SET32_BITFIELDS(&mtk_iocfg_lt->smt_cfg0_set, SPMI_SCL_SMT, 0x1,
  94                         SPMI_SDA_SMT, 0x1);
  95         SET32_BITFIELDS(&mtk_iocfg_lt->tdsel_cfg3_clr, SPMI_TD, 0xF);
  96         SET32_BITFIELDS(&mtk_iocfg_lt->rdsel_cfg3_clr, SPMI_RD, 0x3);
  97         SET32_BITFIELDS(&mtk_iocfg_lt->drv_cfg3_clr, SPMI_DRI, 0x07);
  98         SET32_BITFIELDS(&mtk_iocfg_lt->drv_cfg3_set, SPMI_DRI, 0x02);
  99 }