src/soc/mediatek/mt8195/pmif_clk.c

   1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
   2
   3 #include <commonlib/helpers.h>
   4 #include <delay.h>
   5 #include <device/mmio.h>
   6 #include <soc/infracfg.h>
   7 #include <soc/pll.h>
   8 #include <soc/pll_common.h>
   9 #include <soc/pmif.h>
  10 #include <soc/pmif_clk_common.h>
  11 #include <soc/pmif_sw.h>
  12 #include <soc/pmif_spmi.h>
  13 #include <soc/spm.h>
  14
  15 /* APMIXED, ULPOSC1_CON0 */
  16 DEFINE_BITFIELD(OSC1_CALI, 6, 0)
  17 DEFINE_BITFIELD(OSC1_IBAND, 13, 7)
  18 DEFINE_BITFIELD(OSC1_FBAND, 17, 14)
  19 DEFINE_BITFIELD(OSC1_DIV, 23, 18)
  20 DEFINE_BIT(OSC1_CP_EN, 24)
  21 DEFINE_BITFIELD(OSC1_MOD, 26, 25)
  22 DEFINE_BIT(OSC1_DIV2_EN, 27)
  23
  24 /* APMIXED, ULPOSC1_CON1 */
  25 DEFINE_BITFIELD(OSC1_RSV1, 7, 0)
  26 DEFINE_BITFIELD(OSC1_RSV2, 15, 8)
  27 DEFINE_BITFIELD(OSC1_32KCALI, 23, 16)
  28 DEFINE_BITFIELD(OSC1_BIAS, 31, 24)
  29
  30 /* SPM, POWERON_CONFIG_EN */
  31 DEFINE_BIT(BCLK_CG_EN, 0)
  32 DEFINE_BITFIELD(PROJECT_CODE, 31, 16)
  33
  34 /* SPM, ULPOSC_CON */
  35 DEFINE_BIT(ULPOSC_EN, 0)
  36 DEFINE_BIT(ULPOSC_CG_EN, 2)
  37
  38 /* SCP, SCP_CLK_ON_CTRL */
  39 DEFINE_BIT(SCP_CLK_ON_CTRL, 1)
  40
  41 /* INFRA, MODULE_SW_CG */
  42 DEFINE_BIT(PMIC_CG_TMR, 0)
  43 DEFINE_BIT(PMIC_CG_AP, 1)
  44 DEFINE_BIT(PMIC_CG_MD, 2)
  45 DEFINE_BIT(PMIC_CG_CONN, 3)
  46
  47 /* INFRA, INFRA_GLOBALCON_RST2 */
  48 DEFINE_BIT(PMIC_WRAP_SWRST, 0)
  49 DEFINE_BIT(PMICSPMI_SWRST, 14)
  50
  51 /* INFRA, PMICW_CLOCK_CTRL */
  52 DEFINE_BITFIELD(PMIC_SYSCK_26M_SEL, 3, 0)
  53
  54 /* TOPCKGEN, CLK_CFG_9 */
  55 DEFINE_BITFIELD(CLK_PWRAP_ULPOSC_SET, 2, 0)
  56 DEFINE_BIT(PDN_PWRAP_ULPOSC, 0)
  57
  58 /* TOPCKGEN, CLK_CFG_UPDATE1 */
  59 DEFINE_BIT(CLK_CFG_UPDATE1, 4)
  60
  61 static void pmif_ulposc_config(void)
  62 {
  63         /* ULPOSC1_CON0 */
  64         SET32_BITFIELDS(&mtk_apmixed->ulposc1_con0, OSC1_DIV2_EN, 0, OSC1_MOD, 0,
  65                         OSC1_CP_EN, 0, OSC1_DIV, 0xe, OSC1_FBAND, 0x2,
  66                         OSC1_IBAND, 0x52, OSC1_CALI, 0x40);
  67
  68         /* ULPOSC1_CON1 */
  69         SET32_BITFIELDS(&mtk_apmixed->ulposc1_con1, OSC1_32KCALI, 0, OSC1_BIAS, 0x40,
  70                         OSC1_RSV2, 0, OSC1_RSV1, 0x29);
  71 }
  72
  73 u32 pmif_get_ulposc_freq_mhz(u32 cali_val)
  74 {
  75         u32 result = 0;
  76
  77         /* set calibration value */
  78         SET32_BITFIELDS(&mtk_apmixed->ulposc1_con0, OSC1_CALI, cali_val);
  79         udelay(50);
  80         result = mt_fmeter_get_freq_khz(FMETER_ABIST, FREQ_METER_ABIST_AD_OSC_CK);
  81
  82         return result / 1000;
  83 }
  84
  85 static int pmif_init_ulposc(void)
  86 {
  87         /* calibrate ULPOSC1 */
  88         pmif_ulposc_config();
  89
  90         /* enable spm swinf */
  91         if (!READ32_BITFIELD(&mtk_spm->poweron_config_set, BCLK_CG_EN))
  92                 SET32_BITFIELDS(&mtk_spm->poweron_config_set, BCLK_CG_EN, 1,
  93                                 PROJECT_CODE, 0xb16);
  94
  95         /* turn on ulposc */
  96         SET32_BITFIELDS(&mtk_spm->ulposc_con, ULPOSC_EN, 1);
  97         udelay(100);
  98         SET32_BITFIELDS(&mtk_scp->scp_clk_on_ctrl, SCP_CLK_ON_CTRL, 1);
  99         SET32_BITFIELDS(&mtk_spm->ulposc_con, ULPOSC_CG_EN, 1);
 100
 101         return pmif_ulposc_cali(FREQ_248MHZ);
 102 }
 103
 104 int pmif_clk_init(void)
 105 {
 106         if (pmif_init_ulposc())
 107                 return E_NODEV;
 108
 109         /* turn off pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */
 110         SET32_BITFIELDS(&mt8195_infracfg_ao->module_sw_cg_0_set, PMIC_CG_TMR, 1, PMIC_CG_AP, 1,
 111                         PMIC_CG_MD, 1, PMIC_CG_CONN, 1);
 112
 113         SET32_BITFIELDS(&mtk_topckgen->clk_cfg_9, PDN_PWRAP_ULPOSC, 0,
 114                         CLK_PWRAP_ULPOSC_SET, 0);
 115         SET32_BITFIELDS(&mtk_topckgen->clk_cfg_update1, CLK_CFG_UPDATE1, 1);
 116
 117         /* use ULPOSC1 clock */
 118         SET32_BITFIELDS(&mt8195_infracfg_ao->pmicw_clock_ctrl_clr, PMIC_SYSCK_26M_SEL, 0xf);
 119
 120         /* toggle SPI/SPMI sw reset */
 121         SET32_BITFIELDS(&mt8195_infracfg_ao->infra_globalcon_rst2_set, PMICSPMI_SWRST, 1,
 122                         PMIC_WRAP_SWRST, 1);
 123         SET32_BITFIELDS(&mt8195_infracfg_ao->infra_globalcon_rst2_clr, PMICSPMI_SWRST, 1,
 124                         PMIC_WRAP_SWRST, 1);
 125
 126         /* turn on pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */
 127         SET32_BITFIELDS(&mt8195_infracfg_ao->module_sw_cg_0_clr, PMIC_CG_TMR, 1, PMIC_CG_AP, 1,
 128                         PMIC_CG_MD, 1, PMIC_CG_CONN, 1);
 129
 130         return 0;
 131 }