src/soc/mediatek/mt8195/spi.c

   1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
   2
   3 #include <assert.h>
   4 #include <device/mmio.h>
   5 #include <gpio.h>
   6 #include <soc/addressmap.h>
   7 #include <soc/flash_controller_common.h>
   8 #include <soc/spi.h>
   9
  10 struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = {
  11         {
  12                 .regs = (void *)SPI0_BASE,
  13                 .cs_gpio = GPIO(SPIM0_CSB),
  14         },
  15         {
  16                 .regs = (void *)SPI1_BASE,
  17                 .cs_gpio = GPIO(SPIM1_CSB),
  18         },
  19         {
  20                 .regs = (void *)SPI2_BASE,
  21                 .cs_gpio = GPIO(SPIM2_CSB),
  22         },
  23         {
  24                 .regs = (void *)SPI3_BASE,
  25                 .cs_gpio = GPIO(PWRAP_SPI_CSN),
  26         },
  27         {
  28                 .regs = (void *)SPI4_BASE,
  29                 .cs_gpio = GPIO(DGI_D2),
  30         },
  31         {
  32                 .regs = (void *)SPI5_BASE,
  33                 .cs_gpio = GPIO(DGI_D6),
  34         },
  35 };
  36
  37 static const struct pad_func pad0_funcs[SPI_BUS_NUMBER][4] = {
  38         {
  39                 PAD_FUNC_DOWN(SPIM0_MI, SPIM0_MI),
  40                 PAD_FUNC_GPIO(SPIM0_CSB),
  41                 PAD_FUNC_DOWN(SPIM0_MO, SPIM0_MO),
  42                 PAD_FUNC_DOWN(SPIM0_CLK, SPIM0_CLK),
  43         },
  44         {
  45                 PAD_FUNC_DOWN(SPIM1_MI, SPIM1_MI),
  46                 PAD_FUNC_GPIO(SPIM1_CSB),
  47                 PAD_FUNC_DOWN(SPIM1_MO, SPIM1_MO),
  48                 PAD_FUNC_DOWN(SPIM1_CLK, SPIM1_CLK),
  49         },
  50         {
  51                 PAD_FUNC_DOWN(SPIM2_MI, SPIM2_MI),
  52                 PAD_FUNC_GPIO(SPIM2_CSB),
  53                 PAD_FUNC_DOWN(SPIM2_MO, SPIM2_MO),
  54                 PAD_FUNC_DOWN(SPIM2_CLK, SPIM2_CLK),
  55         },
  56         {
  57                 PAD_FUNC_DOWN(PWRAP_SPI_MI, SPIM3_MI),
  58                 PAD_FUNC_GPIO(PWRAP_SPI_CSN),
  59                 PAD_FUNC_DOWN(PWRAP_SPI_MO, SPIM3_MO),
  60                 PAD_FUNC_DOWN(PWRAP_SPI_CK, SPIM3_CLK),
  61         },
  62         {
  63                 PAD_FUNC_DOWN(DGI_D3, SPIM4_MI),
  64                 PAD_FUNC_GPIO(DGI_D2),
  65                 PAD_FUNC_DOWN(DGI_D1, SPIM4_MO),
  66                 PAD_FUNC_DOWN(DGI_D0, SPIM4_CLK),
  67         },
  68         {
  69                 PAD_FUNC_DOWN(DGI_D7, SPIM5_MI),
  70                 PAD_FUNC_GPIO(DGI_D6),
  71                 PAD_FUNC_DOWN(DGI_D5, SPIM5_MO),
  72                 PAD_FUNC_DOWN(DGI_D4, SPIM5_CLK),
  73         },
  74 };
  75
  76 void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select)
  77 {
  78         assert(bus < SPI_BUS_NUMBER);
  79         assert(pad_select == SPI_PAD0_MASK);
  80         const struct pad_func *ptr = NULL;
  81
  82         ptr = pad0_funcs[bus];
  83         for (int i = 0; i < 4; i++)
  84                 gpio_set_mode(ptr[i].gpio, ptr[i].func);
  85 }
  86
  87 static const struct spi_ctrlr spi_flash_ctrlr = {
  88         .max_xfer_size = 65535,
  89         .flash_probe = mtk_spi_flash_probe,
  90 };
  91
  92 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
  93         {
  94                 .ctrlr = &spi_ctrlr,
  95                 .bus_start = 0,
  96                 .bus_end = SPI_BUS_NUMBER - 1,
  97         },
  98         {
  99                 .ctrlr = &spi_flash_ctrlr,
 100                 .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
 101                 .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
 102         },
 103 };
 104
 105 const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);