src/soc/mediatek/mt8195/spm.c

   1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
   2
   3 #include <soc/mcu_common.h>
   4 #include <soc/spm.h>
   5
   6 static const struct pwr_ctrl spm_init_ctrl = {
   7         .pcm_flags = SPM_FLAG_DISABLE_VCORE_DVS | SPM_FLAG_DISABLE_VCORE_DFS |
   8                      SPM_FLAG_RUN_COMMON_SCENARIO,
   9
  10         /* SPM_AP_STANDBY_CON */
  11         /* [0] */
  12         .reg_wfi_op = 0,
  13         /* [1] */
  14         .reg_wfi_type = 0,
  15         /* [2] */
  16         .reg_mp0_cputop_idle_mask = 0,
  17         /* [3] */
  18         .reg_mp1_cputop_idle_mask = 0,
  19         /* [4] */
  20         .reg_mcusys_idle_mask = 0,
  21         /* [25] */
  22         .reg_md_apsrc_1_sel = 0,
  23         /* [26] */
  24         .reg_md_apsrc_0_sel = 0,
  25         /* [29] */
  26         .reg_conn_apsrc_sel = 0,
  27
  28         /* SPM_SRC_REQ */
  29         /* [0] */
  30         .reg_spm_apsrc_req = 0,
  31         /* [1] */
  32         .reg_spm_f26m_req = 0,
  33         /* [3] */
  34         .reg_spm_infra_req = 0,
  35         /* [4] */
  36         .reg_spm_vrf18_req = 0,
  37         /* [7] FIXME: default disable HW Auto S1*/
  38         .reg_spm_ddr_en_req = 1,
  39         /* [8] */
  40         .reg_spm_dvfs_req = 0,
  41         /* [9] */
  42         .reg_spm_sw_mailbox_req = 0,
  43         /* [10] */
  44         .reg_spm_sspm_mailbox_req = 0,
  45         /* [11] */
  46         .reg_spm_adsp_mailbox_req = 0,
  47         /* [12] */
  48         .reg_spm_scp_mailbox_req = 0,
  49
  50         /* SPM_SRC_MASK */
  51         /* [0] */
  52         .reg_sspm_srcclkena_0_mask_b = 1,
  53         /* [1] */
  54         .reg_sspm_infra_req_0_mask_b = 1,
  55         /* [2] */
  56         .reg_sspm_apsrc_req_0_mask_b = 1,
  57         /* [3] */
  58         .reg_sspm_vrf18_req_0_mask_b = 1,
  59         /* [4] */
  60         .reg_sspm_ddr_en_0_mask_b = 1,
  61         /* [5] */
  62         .reg_scp_srcclkena_mask_b = 1,
  63         /* [6] */
  64         .reg_scp_infra_req_mask_b = 1,
  65         /* [7] */
  66         .reg_scp_apsrc_req_mask_b = 1,
  67         /* [8] */
  68         .reg_scp_vrf18_req_mask_b = 1,
  69         /* [9] */
  70         .reg_scp_ddr_en_mask_b = 1,
  71         /* [10] */
  72         .reg_audio_dsp_srcclkena_mask_b = 1,
  73         /* [11] */
  74         .reg_audio_dsp_infra_req_mask_b = 1,
  75         /* [12] */
  76         .reg_audio_dsp_apsrc_req_mask_b = 1,
  77         /* [13] */
  78         .reg_audio_dsp_vrf18_req_mask_b = 1,
  79         /* [14] */
  80         .reg_audio_dsp_ddr_en_mask_b = 1,
  81         /* [15] */
  82         .reg_apu_srcclkena_mask_b = 1,
  83         /* [16] */
  84         .reg_apu_infra_req_mask_b = 1,
  85         /* [17] */
  86         .reg_apu_apsrc_req_mask_b = 1,
  87         /* [18] */
  88         .reg_apu_vrf18_req_mask_b = 1,
  89         /* [19] */
  90         .reg_apu_ddr_en_mask_b = 1,
  91         /* [20] */
  92         .reg_cpueb_srcclkena_mask_b = 1,
  93         /* [21] */
  94         .reg_cpueb_infra_req_mask_b = 1,
  95         /* [22] */
  96         .reg_cpueb_apsrc_req_mask_b = 1,
  97         /* [23] */
  98         .reg_cpueb_vrf18_req_mask_b = 1,
  99         /* [24] */
 100         .reg_cpueb_ddr_en_mask_b = 1,
 101         /* [25] */
 102         .reg_bak_psri_srcclkena_mask_b = 0,
 103         /* [26] */
 104         .reg_bak_psri_infra_req_mask_b = 0,
 105         /* [27] */
 106         .reg_bak_psri_apsrc_req_mask_b = 0,
 107         /* [28] */
 108         .reg_bak_psri_vrf18_req_mask_b = 0,
 109         /* [29] */
 110         .reg_bak_psri_ddr_en_mask_b = 0,
 111
 112         /* SPM_SRC2_MASK */
 113         /* [0] */
 114         .reg_msdc0_srcclkena_mask_b = 1,
 115         /* [1] */
 116         .reg_msdc0_infra_req_mask_b = 1,
 117         /* [2] */
 118         .reg_msdc0_apsrc_req_mask_b = 1,
 119         /* [3] */
 120         .reg_msdc0_vrf18_req_mask_b = 1,
 121         /* [4] */
 122         .reg_msdc0_ddr_en_mask_b = 1,
 123         /* [5] */
 124         .reg_msdc1_srcclkena_mask_b = 1,
 125         /* [6] */
 126         .reg_msdc1_infra_req_mask_b = 1,
 127         /* [7] */
 128         .reg_msdc1_apsrc_req_mask_b = 1,
 129         /* [8] */
 130         .reg_msdc1_vrf18_req_mask_b = 1,
 131         /* [9] */
 132         .reg_msdc1_ddr_en_mask_b = 1,
 133         /* [10] */
 134         .reg_msdc2_srcclkena_mask_b = 1,
 135         /* [11] */
 136         .reg_msdc2_infra_req_mask_b = 1,
 137         /* [12] */
 138         .reg_msdc2_apsrc_req_mask_b = 1,
 139         /* [13] */
 140         .reg_msdc2_vrf18_req_mask_b = 1,
 141         /* [14] */
 142         .reg_msdc2_ddr_en_mask_b = 1,
 143         /* [15] */
 144         .reg_ufs_srcclkena_mask_b = 1,
 145         /* [16] */
 146         .reg_ufs_infra_req_mask_b = 1,
 147         /* [17] */
 148         .reg_ufs_apsrc_req_mask_b = 1,
 149         /* [18] */
 150         .reg_ufs_vrf18_req_mask_b = 1,
 151         /* [19] */
 152         .reg_ufs_ddr_en_mask_b = 1,
 153         /* [20] */
 154         .reg_usb_srcclkena_mask_b = 1,
 155         /* [21] */
 156         .reg_usb_infra_req_mask_b = 1,
 157         /* [22] */
 158         .reg_usb_apsrc_req_mask_b = 1,
 159         /* [23] */
 160         .reg_usb_vrf18_req_mask_b = 1,
 161         /* [24] */
 162         .reg_usb_ddr_en_mask_b = 1,
 163         /* [25] */
 164         .reg_pextp_p0_srcclkena_mask_b = 1,
 165         /* [26] */
 166         .reg_pextp_p0_infra_req_mask_b = 1,
 167         /* [27] */
 168         .reg_pextp_p0_apsrc_req_mask_b = 1,
 169         /* [28] */
 170         .reg_pextp_p0_vrf18_req_mask_b = 1,
 171         /* [29] */
 172         .reg_pextp_p0_ddr_en_mask_b = 1,
 173
 174         /* SPM_SRC3_MASK */
 175         /* [0] */
 176         .reg_pextp_p1_srcclkena_mask_b = 1,
 177         /* [1] */
 178         .reg_pextp_p1_infra_req_mask_b = 1,
 179         /* [2] */
 180         .reg_pextp_p1_apsrc_req_mask_b = 1,
 181         /* [3] */
 182         .reg_pextp_p1_vrf18_req_mask_b = 1,
 183         /* [4] */
 184         .reg_pextp_p1_ddr_en_mask_b = 1,
 185         /* [5] */
 186         .reg_gce0_infra_req_mask_b = 1,
 187         /* [6] */
 188         .reg_gce0_apsrc_req_mask_b = 1,
 189         /* [7] */
 190         .reg_gce0_vrf18_req_mask_b = 1,
 191         /* [8] */
 192         .reg_gce0_ddr_en_mask_b = 1,
 193         /* [9] */
 194         .reg_gce1_infra_req_mask_b = 1,
 195         /* [10] */
 196         .reg_gce1_apsrc_req_mask_b = 1,
 197         /* [11] */
 198         .reg_gce1_vrf18_req_mask_b = 1,
 199         /* [12] */
 200         .reg_gce1_ddr_en_mask_b = 1,
 201         /* [13] */
 202         .reg_spm_srcclkena_reserved_mask_b = 1,
 203         /* [14] */
 204         .reg_spm_infra_req_reserved_mask_b = 1,
 205         /* [15] */
 206         .reg_spm_apsrc_req_reserved_mask_b = 1,
 207         /* [16] */
 208         .reg_spm_vrf18_req_reserved_mask_b = 1,
 209         /* [17] */
 210         .reg_spm_ddr_en_reserved_mask_b = 1,
 211         /* [18] */
 212         .reg_disp0_apsrc_req_mask_b = 1,
 213         /* [19] */
 214         .reg_disp0_ddr_en_mask_b = 1,
 215         /* [20] */
 216         .reg_disp1_apsrc_req_mask_b = 1,
 217         /* [21] */
 218         .reg_disp1_ddr_en_mask_b = 1,
 219         /* [22] */
 220         .reg_disp2_apsrc_req_mask_b = 1,
 221         /* [23] */
 222         .reg_disp2_ddr_en_mask_b = 1,
 223         /* [24] */
 224         .reg_disp3_apsrc_req_mask_b = 1,
 225         /* [25] */
 226         .reg_disp3_ddr_en_mask_b = 1,
 227         /* [26] */
 228         .reg_infrasys_apsrc_req_mask_b = 0,
 229         /* [27] */
 230         .reg_infrasys_ddr_en_mask_b = 1,
 231
 232         /* [28] */
 233         .reg_cg_check_srcclkena_mask_b = 1,
 234         /* [29] */
 235         .reg_cg_check_apsrc_req_mask_b = 1,
 236         /* [30] */
 237         .reg_cg_check_vrf18_req_mask_b = 1,
 238         /* [31] */
 239         .reg_cg_check_ddr_en_mask_b = 1,
 240
 241         /* SPM_SRC4_MASK */
 242         /* [8:0] */
 243         .reg_mcusys_merge_apsrc_req_mask_b = 0x17,
 244         /* [17:9] */
 245         .reg_mcusys_merge_ddr_en_mask_b = 0x17,
 246         /* [19:18] */
 247         .reg_dramc_md32_infra_req_mask_b = 0,
 248         /* [21:20] */
 249         .reg_dramc_md32_vrf18_req_mask_b = 0,
 250         /* [23:22] */
 251         .reg_dramc_md32_ddr_en_mask_b = 0,
 252         /* [24] */
 253         .reg_dvfsrc_event_trigger_mask_b = 1,
 254
 255         /* SPM_WAKEUP_EVENT_MASK2 */
 256         /* [3:0] */
 257         .reg_sc_sw2spm_wakeup_mask_b = 0,
 258         /* [4] */
 259         .reg_sc_adsp2spm_wakeup_mask_b = 0,
 260         /* [8:5] */
 261         .reg_sc_sspm2spm_wakeup_mask_b = 0,
 262         /* [9] */
 263         .reg_sc_scp2spm_wakeup_mask_b = 0,
 264         /* [10] */
 265         .reg_csyspwrup_ack_mask = 0,
 266         /* [11] */
 267         .reg_csyspwrup_req_mask = 1,
 268
 269         /* SPM_WAKEUP_EVENT_MASK */
 270         /* [31:0] */
 271         .reg_wakeup_event_mask = 0xC1382213,
 272
 273         /* SPM_WAKEUP_EVENT_EXT_MASK */
 274         /* [31:0] */
 275         .reg_ext_wakeup_event_mask = 0xFFFFFFFF,
 276 };
 277
 278 void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
 279 {
 280         /* Auto-gen Start */
 281
 282         /* SPM_AP_STANDBY_CON */
 283         write32(&mtk_spm->spm_ap_standby_con,
 284                 ((pwrctrl->reg_wfi_op & 0x1) << 0) |
 285                 ((pwrctrl->reg_wfi_type & 0x1) << 1) |
 286                 ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
 287                 ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
 288                 ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
 289                 ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
 290                 ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
 291                 ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
 292
 293         /* SPM_SRC_REQ */
 294         write32(&mtk_spm->spm_src_req,
 295                 ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
 296                 ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
 297                 ((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
 298                 ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
 299                 ((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) |
 300                 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
 301                 ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
 302                 ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
 303                 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
 304                 ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
 305
 306         /* SPM_SRC_MASK */
 307         write32(&mtk_spm->spm_src_mask,
 308                 ((pwrctrl->reg_sspm_srcclkena_0_mask_b & 0x1) << 0) |
 309                 ((pwrctrl->reg_sspm_infra_req_0_mask_b & 0x1) << 1) |
 310                 ((pwrctrl->reg_sspm_apsrc_req_0_mask_b & 0x1) << 2) |
 311                 ((pwrctrl->reg_sspm_vrf18_req_0_mask_b & 0x1) << 3) |
 312                 ((pwrctrl->reg_sspm_ddr_en_0_mask_b & 0x1) << 4) |
 313                 ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 5) |
 314                 ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 6) |
 315                 ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 7) |
 316                 ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 8) |
 317                 ((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 9) |
 318                 ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 10) |
 319                 ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 11) |
 320                 ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 12) |
 321                 ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 13) |
 322                 ((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 14) |
 323                 ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 15) |
 324                 ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 16) |
 325                 ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 17) |
 326                 ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 18) |
 327                 ((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 19) |
 328                 ((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 20) |
 329                 ((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 21) |
 330                 ((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 22) |
 331                 ((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 23) |
 332                 ((pwrctrl->reg_cpueb_ddr_en_mask_b & 0x1) << 24) |
 333                 ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 25) |
 334                 ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 26) |
 335                 ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 27) |
 336                 ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 28) |
 337                 ((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 29));
 338
 339         /* SPM_SRC2_MASK */
 340         write32(&mtk_spm->spm_src2_mask,
 341                 ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 0) |
 342                 ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 1) |
 343                 ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 2) |
 344                 ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 3) |
 345                 ((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 4) |
 346                 ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 5) |
 347                 ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 6) |
 348                 ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 7) |
 349                 ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 8) |
 350                 ((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 9) |
 351                 ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 10) |
 352                 ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 11) |
 353                 ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 12) |
 354                 ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 13) |
 355                 ((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 14) |
 356                 ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 15) |
 357                 ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 16) |
 358                 ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 17) |
 359                 ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 18) |
 360                 ((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 19) |
 361                 ((pwrctrl->reg_usb_srcclkena_mask_b & 0x1) << 20) |
 362                 ((pwrctrl->reg_usb_infra_req_mask_b & 0x1) << 21) |
 363                 ((pwrctrl->reg_usb_apsrc_req_mask_b & 0x1) << 22) |
 364                 ((pwrctrl->reg_usb_vrf18_req_mask_b & 0x1) << 23) |
 365                 ((pwrctrl->reg_usb_ddr_en_mask_b & 0x1) << 24) |
 366                 ((pwrctrl->reg_pextp_p0_srcclkena_mask_b & 0x1) << 25) |
 367                 ((pwrctrl->reg_pextp_p0_infra_req_mask_b & 0x1) << 26) |
 368                 ((pwrctrl->reg_pextp_p0_apsrc_req_mask_b & 0x1) << 27) |
 369                 ((pwrctrl->reg_pextp_p0_vrf18_req_mask_b & 0x1) << 28) |
 370                 ((pwrctrl->reg_pextp_p0_ddr_en_mask_b & 0x1) << 29));
 371
 372         /* SPM_SRC3_MASK */
 373         write32(&mtk_spm->spm_src3_mask,
 374                 ((pwrctrl->reg_pextp_p1_srcclkena_mask_b & 0x1) << 0) |
 375                 ((pwrctrl->reg_pextp_p1_infra_req_mask_b & 0x1) << 1) |
 376                 ((pwrctrl->reg_pextp_p1_apsrc_req_mask_b & 0x1) << 2) |
 377                 ((pwrctrl->reg_pextp_p1_vrf18_req_mask_b & 0x1) << 3) |
 378                 ((pwrctrl->reg_pextp_p1_ddr_en_mask_b & 0x1) << 4) |
 379                 ((pwrctrl->reg_gce0_infra_req_mask_b & 0x1) << 5) |
 380                 ((pwrctrl->reg_gce0_apsrc_req_mask_b & 0x1) << 6) |
 381                 ((pwrctrl->reg_gce0_vrf18_req_mask_b & 0x1) << 7) |
 382                 ((pwrctrl->reg_gce0_ddr_en_mask_b & 0x1) << 8) |
 383                 ((pwrctrl->reg_gce1_infra_req_mask_b & 0x1) << 9) |
 384                 ((pwrctrl->reg_gce1_apsrc_req_mask_b & 0x1) << 10) |
 385                 ((pwrctrl->reg_gce1_vrf18_req_mask_b & 0x1) << 11) |
 386                 ((pwrctrl->reg_gce1_ddr_en_mask_b & 0x1) << 12) |
 387                 ((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 13) |
 388                 ((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 14) |
 389                 ((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 15) |
 390                 ((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 16) |
 391                 ((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 17) |
 392                 ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 18) |
 393                 ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 19) |
 394                 ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 20) |
 395                 ((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 21) |
 396                 ((pwrctrl->reg_disp2_apsrc_req_mask_b & 0x1) << 22) |
 397                 ((pwrctrl->reg_disp2_ddr_en_mask_b & 0x1) << 23) |
 398                 ((pwrctrl->reg_disp3_apsrc_req_mask_b & 0x1) << 24) |
 399                 ((pwrctrl->reg_disp3_ddr_en_mask_b & 0x1) << 25) |
 400                 ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 26) |
 401                 ((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 27));
 402
 403         /* SPM_SRC4_MASK */
 404         write32(&mtk_spm->spm_src4_mask, 0x1fc0000);
 405
 406         /* SPM_WAKEUP_EVENT_MASK */
 407         write32(&mtk_spm->spm_wakeup_event_mask,
 408                 ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
 409
 410         /* SPM_WAKEUP_EVENT_EXT_MASK */
 411         write32(&mtk_spm->spm_wakeup_event_ext_mask,
 412                 ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
 413
 414         /* Auto-gen End */
 415 }
 416
 417 void spm_register_init(void)
 418 {
 419         /* Enable register control */
 420         write32(&mtk_spm->poweron_config_set,
 421                 SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
 422
 423         /* Init power control register */
 424         write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF);
 425         write32(&mtk_spm->pcm_pwr_io_en, 0);
 426
 427         /* Reset PCM */
 428         write32(&mtk_spm->pcm_con0,
 429                 SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB);
 430         write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
 431         write32(&mtk_spm->pcm_con1,
 432                 SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB |
 433                 REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB |
 434                 REG_MD32_APB_INTERNAL_EN_LSB);
 435
 436         /* Initial SPM CLK control register */
 437         SET32_BITFIELDS(&mtk_spm->spm_clk_con,
 438                         REG_SYSCLK1_SRC_MD2_SRCCLKENA, 1);
 439
 440         /* Clean wakeup event raw status */
 441         write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF);
 442
 443         /* Clean ISR status */
 444         write32(&mtk_spm->spm_irq_mask, ISRM_ALL);
 445         write32(&mtk_spm->spm_irq_sta, ISRC_ALL);
 446         write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL);
 447
 448         /* Init r7 with POWER_ON_VAL1 */
 449         write32(&mtk_spm->pcm_reg_data_ini,
 450                 read32(&mtk_spm->spm_power_on_val1));
 451         write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
 452         write32(&mtk_spm->pcm_pwr_io_en, 0);
 453
 454         /* Configure ARMPLL Control Mode for MCDI */
 455         write32(&mtk_spm->armpll_clk_sel, ARMPLL_CLK_SEL_DEF);
 456
 457         /* Init for SPM Resource ACK */
 458         write32(&mtk_spm->spm_resource_ack_con0, SPM_RESOURCE_ACK_CON0_DEF);
 459         write32(&mtk_spm->spm_resource_ack_con1, SPM_RESOURCE_ACK_CON1_DEF);
 460         write32(&mtk_spm->spm_resource_ack_con2, SPM_RESOURCE_ACK_CON2_DEF);
 461         write32(&mtk_spm->spm_resource_ack_con3, SPM_RESOURCE_ACK_CON3_DEF);
 462
 463         /* Init VCORE DVFS Status */
 464         SET32_BITFIELDS(&mtk_spm->spm_dvfs_misc,
 465                         SPM_DVFS_FORCE_ENABLE_LSB, 0,
 466                         SPM_DVFSRC_ENABLE_LSB, 1);
 467         write32(&mtk_spm->spm_dvfs_level, SPM_DVFS_LEVEL_DEF);
 468         write32(&mtk_spm->spm_dvs_dfs_level, SPM_DVS_DFS_LEVEL_DEF);
 469 }
 470
 471 void spm_reset_and_init_pcm(void)
 472 {
 473         bool first_load_fw = true;
 474
 475         /* Check the SPM FW is run or not */
 476         if (read32(&mtk_spm->md32pcm_cfgreg_sw_rstn) &
 477             MD32PCM_CFGREG_SW_RSTN_RUN)
 478                 first_load_fw = false;
 479
 480         if (!first_load_fw) {
 481                 spm_code_swapping();
 482                 /* Backup PCM r0 -> SPM_POWER_ON_VAL0 before reset PCM */
 483                 write32(&mtk_spm->spm_power_on_val0,
 484                         read32(&mtk_spm->pcm_reg0_data));
 485         }
 486
 487         /* Disable r0 and r7 to control power */
 488         write32(&mtk_spm->pcm_pwr_io_en, 0);
 489
 490         /* Disable pcm timer after leaving FW */
 491         clrsetbits32(&mtk_spm->pcm_con1,
 492                      RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
 493
 494         /* Reset PCM */
 495         write32(&mtk_spm->pcm_con0,
 496                 SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB);
 497         write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
 498
 499         /* Init PCM_CON1 (disable PCM timer but keep PCM WDT setting) */
 500         clrsetbits32(&mtk_spm->pcm_con1, ~RG_PCM_WDT_WAKE_LSB,
 501                      SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB |
 502                      REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB |
 503                      REG_MD32_APB_INTERNAL_EN_LSB);
 504 }
 505
 506 void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
 507 {
 508         u32 val, mask;
 509
 510         /* Toggle event counter clear */
 511         setbits32(&mtk_spm->pcm_con1,
 512                   SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
 513
 514         /* Toggle for reset SYS TIMER start point */
 515         SET32_BITFIELDS(&mtk_spm->sys_timer_con,
 516                         SYS_TIMER_START_EN_LSB, 1);
 517
 518         if (pwrctrl->timer_val_cust == 0)
 519                 val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX;
 520         else
 521                 val = pwrctrl->timer_val_cust;
 522
 523         write32(&mtk_spm->pcm_timer_val, val);
 524
 525         /* Disable pcm timer */
 526         clrsetbits32(&mtk_spm->pcm_con1,
 527                      RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
 528
 529         /* Unmask AP wakeup source */
 530         if (pwrctrl->wake_src_cust == 0)
 531                 mask = pwrctrl->wake_src;
 532         else
 533                 mask = pwrctrl->wake_src_cust;
 534
 535         write32(&mtk_spm->spm_wakeup_event_mask, ~mask);
 536
 537         /* Unmask SPM ISR */
 538         SET32_BITFIELDS(&mtk_spm->spm_irq_mask,
 539                         ISRM_TWAM_BF, 1,
 540                         ISRM_RET_IRQ_AUX_BF, 0x3ff);
 541
 542         /* Toggle event counter clear */
 543         clrsetbits32(&mtk_spm->pcm_con1,
 544                      SPM_EVENT_COUNTER_CLR_LSB, SPM_REGWR_CFG_KEY);
 545
 546         /* Toggle for reset SYS TIMER start point */
 547         SET32_BITFIELDS(&mtk_spm->sys_timer_con,
 548                         SYS_TIMER_START_EN_LSB, 0);
 549 }
 550
 551 const struct pwr_ctrl *get_pwr_ctrl(void)
 552 {
 553         return &spm_init_ctrl;
 554 }