src/soc/mediatek/mt8196/l2c_ops.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * This file is created based on MT8196 Functional Specification
   5  * Chapter number: 9
   6  */
   7
   8 #include <device/mmio.h>
   9 #include <soc/mmu_operations.h>
  10
  11 DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_FULLNHALF, 0)
  12 DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 1)
  13 DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 2)
  14
  15 #define MP0_CLUSTER_CFG0        0x0C000060
  16 #define CLUST_DIS_VAL           0x3
  17 #define CLUST_DIS_SHIFT         0x4
  18
  19 void mtk_soc_disable_l2c_sram(void)
  20 {
  21         unsigned long v;
  22
  23         uint32_t *mp0_cluster_cfg0 = (void *)(MP0_CLUSTER_CFG0);
  24
  25         SET32_BITFIELDS(mp0_cluster_cfg0,
  26                         MP0_CLUSTER_CFG0_L3_SHARE_EN, 0);
  27         dsb();
  28
  29         __asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v));
  30         v |= (CLUST_DIS_VAL << CLUST_DIS_SHIFT);
  31         __asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v));
  32         dsb();
  33
  34         do {
  35                 __asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v));
  36         } while (((v >> CLUST_DIS_SHIFT) & CLUST_DIS_VAL) != CLUST_DIS_VAL);
  37
  38         SET32_BITFIELDS(mp0_cluster_cfg0,
  39                         MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0);
  40
  41         SET32_BITFIELDS(mp0_cluster_cfg0,
  42                         MP0_CLUSTER_CFG0_L3_SHARE_FULLNHALF, 0);
  43
  44         dsb();
  45 }