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drivers/wifi: Remove unnecessary data structure copy
[coreboot2.git] / src / soc / mediatek / mt8196 / pll.c
blob59a9b0943f9b1245a5d471f61dfe1dc8cf8e11d7
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 /*
4 * This file is created based on MT8196 Functional Specification
5 * Chapter number: 14.1
6 */
7
8 #include <console/console.h>
9 #include <delay.h>
10 #include <device/mmio.h>
11 #include <soc/addressmap.h>
12 #include <soc/pll.h>
13 #include <timer.h>
14
15 #define VLP_FM_WAIT_TIME_MS 40
16
17 #define FMIN (1700UL * MHz)
18 #define FMAX (3800UL * MHz)
19 #define FIN_RATE (26 * MHz)
20 #define CON1_PCW_CHG BIT(31)
21 #define POSTDIV_VAL_MAX 5
22 #define POSTDIV_MASK 0x7
23 #define POSTDIV_SHIFT 24
24 #define PCW_FBITS 14
25
26 #define FM_PLL_CK 0
27 #define FM_PLL_CKDIV_CK 1
28
29 enum mux_id {
30 CLK_CK_AXI_SEL,
31 CLK_CK_MEM_SUB_SEL,
32 CLK_CK_IO_NOC_SEL,
33 CLK_CK_P_AXI_SEL,
34 CLK_CK_PEXTP0_AXI_SEL,
35 CLK_CK_PEXTP1_USB_AXI_SEL,
36 CLK_CK_P_FMEM_SUB_SEL,
37 CLK_CK_PEXPT0_MEM_SUB_SEL,
38 CLK_CK_PEXTP1_USB_MEM_SUB_SEL,
39 CLK_CK_P_NOC_SEL,
40 CLK_CK_EMI_N_SEL,
41 CLK_CK_EMI_S_SEL,
42 CLK_CK_EMI_SLICE_N_SEL,
43 CLK_CK_EMI_SLICE_S_SEL,
44 CLK_CK_AP2CONN_HOST_SEL,
45 CLK_CK_ATB_SEL,
46 CLK_CK_CIRQ_SEL,
47 CLK_CK_PBUS_156M_SEL,
48 CLK_CK_NOC_LOW_SEL,
49 CLK_CK_NOC_MID_SEL,
50 CLK_CK_EFUSE_SEL,
51 CLK_CK_MCL3GIC_SEL,
52 CLK_CK_MCINFRA_SEL,
53 CLK_CK_DSP_SEL,
54 CLK_CK_MFG_REF_SEL,
55 CLK_CK_MFGSC_REF_SEL,
56 CLK_CK_MFG_EB_SEL,
57 CLK_CK_UART_SEL,
58 CLK_CK_SPI0_BCLK_SEL,
59 CLK_CK_SPI1_BCLK_SEL,
60 CLK_CK_SPI2_BCLK_SEL,
61 CLK_CK_SPI3_BCLK_SEL,
62 CLK_CK_SPI4_BCLK_SEL,
63 CLK_CK_SPI5_BCLK_SEL,
64 CLK_CK_SPI6_BCLK_SEL,
65 CLK_CK_SPI7_BCLK_SEL,
66 CLK_CK_MSDC_MACRO_1P_SEL,
67 CLK_CK_MSDC_MACRO_2P_SEL,
68 CLK_CK_MSDC30_1_SEL,
69 CLK_CK_MSDC30_2_SEL,
70 CLK_CK_DISP_PWM_SEL,
71 CLK_CK_USB_TOP_1P_SEL,
72 CLK_CK_USB_XHCI_1P_SEL,
73 CLK_CK_USB_FMCNT_P1_SEL,
74 CLK_CK_I2C_P_SEL,
75 CLK_CK_I2C_EAST_SEL,
76 CLK_CK_I2C_WEST_SEL,
77 CLK_CK_I2C_NORTH_SEL,
78 CLK_CK_AES_UFSFDE_SEL,
79 CLK_CK_SEL,
80 CLK_CK_MBIST_SEL,
81 CLK_CK_PEXTP_MBIST_SEL,
82 CLK_CK_AUD_1_SEL,
83 CLK_CK_AUD_2_SEL,
84 CLK_CK_ADSP_SEL,
85 CLK_CK_ADSP_UARTHUB_BCLK_SEL,
86 CLK_CK_DPMAIF_MAIN_SEL,
87 CLK_CK_PWM_SEL,
88 CLK_CK_MCUPM_SEL,
89 CLK_CK_SFLASH_SEL,
90 CLK_CK_IPSEAST_SEL,
91 CLK_CK_IPSWEST_SEL,
92 CLK_CK_TL_SEL,
93 CLK_CK_TL_P1_SEL,
94 CLK_CK_TL_P2_SEL,
95 CLK_CK_EMI_INTERFACE_546_SEL,
96 CLK_CK_SDF_SEL,
97 CLK_CK_UARTHUB_BCLK_SEL,
98 CLK_CK_DPSW_CMP_26M_SEL,
99 CLK_CK_SMAPCK_SEL,
100 CLK_CK_SSR_PKA_SEL,
101 CLK_CK_SSR_DMA_SEL,
102 CLK_CK_SSR_KDF_SEL,
103 CLK_CK_SSR_RNG_SEL,
104 CLK_CK_SPU0_SEL,
105 CLK_CK_SPU1_SEL,
106 CLK_CK_DXCC_SEL,
107 CLK_CK_SPU0_BOOT_SEL,
108 CLK_CK_SPU1_BOOT_SEL,
109 CLK_CK_SGMII0_REF_325M_SEL,
110 CLK_CK_SGMII0_REG_SEL,
111 CLK_CK_SGMII1_REF_325M_SEL,
112 CLK_CK_SGMII1_REG_SEL,
113 CLK_CK_GMAC_312P5M_SEL,
114 CLK_CK_GMAC_125M_SEL,
115 CLK_CK_GMAC_RMII_SEL,
116 CLK_CK_GMAC_62P4M_PTP_SEL,
117 CLK_CK_DUMMY1_SEL,
118 CLK_CK_DUMMY2_SEL,
119 };
120
121 enum cksys2_mux_id {
122 CLK_CK2_SENINF0_SEL,
123 CLK_CK2_SENINF1_SEL,
124 CLK_CK2_SENINF2_SEL,
125 CLK_CK2_SENINF3_SEL,
126 CLK_CK2_SENINF4_SEL,
127 CLK_CK2_SENINF5_SEL,
128 CLK_CK2_IMG1_SEL,
129 CLK_CK2_IPE_SEL,
130 CLK_CK2_CAM_SEL,
131 CLK_CK2_CAMTM_SEL,
132 CLK_CK2_DPE_SEL,
133 CLK_CK2_VDEC_SEL,
134 CLK_CK2_CCUSYS_SEL,
135 CLK_CK2_CCUTM_SEL,
136 CLK_CK2_VENC_SEL,
137 CLK_CK2_DVO_SEL,
138 CLK_CK2_DVO_FAVT_SEL,
139 CLK_CK2_DP1_SEL,
140 CLK_CK2_DP0_SEL,
141 CLK_CK2_DISP_SEL,
142 CLK_CK2_MDP_SEL,
143 CLK_CK2_MMINFRA_SEL,
144 CLK_CK2_MMINFRA_SNOC_SEL,
145 CLK_CK2_MMUP_SEL,
146 CLK_CK2_DUMMY1_SEL,
147 CLK_CK2_DUMMY2_SEL,
148 CLK_CK2_MMINFRA_AO_SEL,
149 };
150
151 enum vlp_mux_id {
152 CLK_VLP_CK_SCP_SEL,
153 CLK_VLP_CK_SCP_SPI_SEL,
154 CLK_VLP_CK_SCP_IIC_SEL,
155 CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL,
156 CLK_VLP_CK_PWRAP_ULPOSC_SEL,
157 CLK_VLP_CK_SPMI_M_TIA_32K_SEL,
158 CLK_VLP_CK_APXGPT_26M_BCLK_SEL,
159 CLK_VLP_CK_DPSW_SEL,
160 CLK_VLP_CK_DPSW_CENTRAL_SEL,
161 CLK_VLP_CK_SPMI_M_MST_SEL,
162 CLK_VLP_CK_DVFSRC_SEL,
163 CLK_VLP_CK_PWM_VLP_SEL,
164 CLK_VLP_CK_AXI_VLP_SEL,
165 CLK_VLP_CK_SYSTIMER_26M_SEL,
166 CLK_VLP_CK_SSPM_SEL,
167 CLK_VLP_CK_SRCK_SEL,
168 CLK_VLP_CK_CAMTG0_SEL,
169 CLK_VLP_CK_CAMTG1_SEL,
170 CLK_VLP_CK_CAMTG2_SEL,
171 CLK_VLP_CK_CAMTG3_SEL,
172 CLK_VLP_CK_CAMTG4_SEL,
173 CLK_VLP_CK_CAMTG5_SEL,
174 CLK_VLP_CK_CAMTG6_SEL,
175 CLK_VLP_CK_CAMTG7_SEL,
176 CLK_VLP_CK_IPS_SEL,
177 CLK_VLP_CK_SSPM_26M_SEL,
178 CLK_VLP_CK_ULPOSC_SSPM_SEL,
179 CLK_VLP_CK_VLP_PBUS_26M_SEL,
180 CLK_VLP_CK_DEBUG_ERR_FLAG_SEL,
181 CLK_VLP_CK_DPMSRDMA_SEL,
182 CLK_VLP_CK_VLP_PBUS_156M_SEL,
183 CLK_VLP_CK_SPM_SEL,
184 CLK_VLP_CK_MMINFRA_VLP_SEL,
185 CLK_VLP_CK_USB_TOP_SEL,
186 CLK_VLP_CK_USB_XHCI_SEL,
187 CLK_VLP_CK_NOC_VLP_SEL,
188 CLK_VLP_CK_AUDIO_H_SEL,
189 CLK_VLP_CK_AUD_ENGEN1_SEL,
190 CLK_VLP_CK_AUD_ENGEN2_SEL,
191 CLK_VLP_CK_AUD_INTBUS_SEL,
192 CLK_VLP_CK_SPVLP_26M_SEL,
193 CLK_VLP_CK_SPU0_VLP_SEL,
194 CLK_VLP_CK_SPU1_VLP_SEL,
195 CLK_VLP_CK_VLP_DUMMY1_SEL,
196 CLK_VLP_CK_VLP_DUMMY2_SEL,
197 };
198
199 #define MUX_UPD(_id, _sys, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\
200 [_id] = { \
201 .reg = &_sys->_clk_cfg.cfg, \
202 .set_reg = &_sys->_clk_cfg.set, \
203 .clr_reg = &_sys->_clk_cfg.clr, \
204 .mux_shift = _mux_shift, \
205 .mux_width = _mux_width, \
206 .upd_reg = &_sys->_upd_reg, \
207 .upd_shift = _upd_shift, \
208 }
209
210 #define CKSYS_MUX_UPD(_id, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\
211 MUX_UPD(_id, mtk_topckgen, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift)
212
213 #define CKSYS2_MUX_UPD(_id, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\
214 MUX_UPD(_id, mtk_topckgen2, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift)
215
216 #define VLP_MUX_UPD(_id, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\
217 MUX_UPD(_id, mtk_vlpsys, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift)
218
219 struct mux_sel {
220 u8 id;
221 u8 sel;
222 };
223
224 static const struct mux muxes[] = {
225 CKSYS_MUX_UPD(CLK_CK_AXI_SEL, clk_cfg[0], 0, 3, clk_cfg_update[0], 0),
226 CKSYS_MUX_UPD(CLK_CK_MEM_SUB_SEL, clk_cfg[0], 8, 4, clk_cfg_update[0], 1),
227 CKSYS_MUX_UPD(CLK_CK_IO_NOC_SEL, clk_cfg[0], 16, 3, clk_cfg_update[0], 2),
228 CKSYS_MUX_UPD(CLK_CK_P_AXI_SEL, clk_cfg[0], 24, 3, clk_cfg_update[0], 3),
229 CKSYS_MUX_UPD(CLK_CK_PEXTP0_AXI_SEL, clk_cfg[1], 0, 3, clk_cfg_update[0], 4),
230 CKSYS_MUX_UPD(CLK_CK_PEXTP1_USB_AXI_SEL, clk_cfg[1], 8, 3, clk_cfg_update[0], 5),
231 CKSYS_MUX_UPD(CLK_CK_P_FMEM_SUB_SEL, clk_cfg[1], 16, 4, clk_cfg_update[0], 6),
232 CKSYS_MUX_UPD(CLK_CK_PEXPT0_MEM_SUB_SEL, clk_cfg[1], 24, 4, clk_cfg_update[0], 7),
233 CKSYS_MUX_UPD(CLK_CK_PEXTP1_USB_MEM_SUB_SEL, clk_cfg[2], 0, 4, clk_cfg_update[0], 8),
234 CKSYS_MUX_UPD(CLK_CK_P_NOC_SEL, clk_cfg[2], 8, 4, clk_cfg_update[0], 9),
235 CKSYS_MUX_UPD(CLK_CK_EMI_N_SEL, clk_cfg[2], 16, 3, clk_cfg_update[0], 10),
236 CKSYS_MUX_UPD(CLK_CK_EMI_S_SEL, clk_cfg[2], 24, 3, clk_cfg_update[0], 11),
237 CKSYS_MUX_UPD(CLK_CK_EMI_SLICE_N_SEL, clk_cfg[3], 0, 2, clk_cfg_update[0], 12),
238 CKSYS_MUX_UPD(CLK_CK_EMI_SLICE_S_SEL, clk_cfg[3], 8, 2, clk_cfg_update[0], 13),
239 CKSYS_MUX_UPD(CLK_CK_AP2CONN_HOST_SEL, clk_cfg[3], 16, 1, clk_cfg_update[0], 14),
240 CKSYS_MUX_UPD(CLK_CK_ATB_SEL, clk_cfg[3], 24, 2, clk_cfg_update[0], 15),
241 CKSYS_MUX_UPD(CLK_CK_CIRQ_SEL, clk_cfg[4], 0, 2, clk_cfg_update[0], 16),
242 CKSYS_MUX_UPD(CLK_CK_PBUS_156M_SEL, clk_cfg[4], 8, 2, clk_cfg_update[0], 17),
243 CKSYS_MUX_UPD(CLK_CK_NOC_LOW_SEL, clk_cfg[4], 16, 3, clk_cfg_update[0], 18),
244 CKSYS_MUX_UPD(CLK_CK_NOC_MID_SEL, clk_cfg[4], 24, 4, clk_cfg_update[0], 19),
245 CKSYS_MUX_UPD(CLK_CK_EFUSE_SEL, clk_cfg[5], 0, 1, clk_cfg_update[0], 20),
246 CKSYS_MUX_UPD(CLK_CK_MCL3GIC_SEL, clk_cfg[5], 8, 2, clk_cfg_update[0], 21),
247 CKSYS_MUX_UPD(CLK_CK_MCINFRA_SEL, clk_cfg[5], 16, 3, clk_cfg_update[0], 22),
248 CKSYS_MUX_UPD(CLK_CK_DSP_SEL, clk_cfg[5], 24, 3, clk_cfg_update[0], 23),
249 CKSYS_MUX_UPD(CLK_CK_MFG_REF_SEL, clk_cfg[6], 0, 1, clk_cfg_update[0], 24),
250 CKSYS_MUX_UPD(CLK_CK_MFGSC_REF_SEL, clk_cfg[6], 8, 1, clk_cfg_update[0], 25),
251 CKSYS_MUX_UPD(CLK_CK_MFG_EB_SEL, clk_cfg[6], 16, 2, clk_cfg_update[0], 26),
252 CKSYS_MUX_UPD(CLK_CK_UART_SEL, clk_cfg[6], 24, 2, clk_cfg_update[0], 27),
253 CKSYS_MUX_UPD(CLK_CK_SPI0_BCLK_SEL, clk_cfg[7], 0, 3, clk_cfg_update[0], 28),
254 CKSYS_MUX_UPD(CLK_CK_SPI1_BCLK_SEL, clk_cfg[7], 8, 3, clk_cfg_update[0], 29),
255 CKSYS_MUX_UPD(CLK_CK_SPI2_BCLK_SEL, clk_cfg[7], 16, 3, clk_cfg_update[0], 30),
256 CKSYS_MUX_UPD(CLK_CK_SPI3_BCLK_SEL, clk_cfg[7], 24, 3, clk_cfg_update[1], 0),
257 CKSYS_MUX_UPD(CLK_CK_SPI4_BCLK_SEL, clk_cfg[8], 0, 3, clk_cfg_update[1], 1),
258 CKSYS_MUX_UPD(CLK_CK_SPI5_BCLK_SEL, clk_cfg[8], 8, 3, clk_cfg_update[1], 2),
259 CKSYS_MUX_UPD(CLK_CK_SPI6_BCLK_SEL, clk_cfg[8], 16, 3, clk_cfg_update[1], 3),
260 CKSYS_MUX_UPD(CLK_CK_SPI7_BCLK_SEL, clk_cfg[8], 24, 3, clk_cfg_update[1], 4),
261 CKSYS_MUX_UPD(CLK_CK_MSDC_MACRO_1P_SEL, clk_cfg[9], 0, 3, clk_cfg_update[1], 5),
262 CKSYS_MUX_UPD(CLK_CK_MSDC_MACRO_2P_SEL, clk_cfg[9], 8, 3, clk_cfg_update[1], 6),
263 CKSYS_MUX_UPD(CLK_CK_MSDC30_1_SEL, clk_cfg[9], 16, 3, clk_cfg_update[1], 7),
264 CKSYS_MUX_UPD(CLK_CK_MSDC30_2_SEL, clk_cfg[9], 24, 3, clk_cfg_update[1], 8),
265 CKSYS_MUX_UPD(CLK_CK_DISP_PWM_SEL, clk_cfg[10], 0, 3, clk_cfg_update[1], 9),
266 CKSYS_MUX_UPD(CLK_CK_USB_TOP_1P_SEL, clk_cfg[10], 8, 1, clk_cfg_update[1], 10),
267 CKSYS_MUX_UPD(CLK_CK_USB_XHCI_1P_SEL, clk_cfg[10], 16, 1, clk_cfg_update[1], 11),
268 CKSYS_MUX_UPD(CLK_CK_USB_FMCNT_P1_SEL, clk_cfg[10], 24, 1, clk_cfg_update[1], 12),
269 CKSYS_MUX_UPD(CLK_CK_I2C_P_SEL, clk_cfg[11], 0, 3, clk_cfg_update[1], 13),
270 CKSYS_MUX_UPD(CLK_CK_I2C_EAST_SEL, clk_cfg[11], 8, 3, clk_cfg_update[1], 14),
271 CKSYS_MUX_UPD(CLK_CK_I2C_WEST_SEL, clk_cfg[11], 16, 3, clk_cfg_update[1], 15),
272 CKSYS_MUX_UPD(CLK_CK_I2C_NORTH_SEL, clk_cfg[11], 24, 3, clk_cfg_update[1], 16),
273 CKSYS_MUX_UPD(CLK_CK_AES_UFSFDE_SEL, clk_cfg[12], 0, 3, clk_cfg_update[1], 17),
274 CKSYS_MUX_UPD(CLK_CK_SEL, clk_cfg[12], 8, 3, clk_cfg_update[1], 18),
275 CKSYS_MUX_UPD(CLK_CK_MBIST_SEL, clk_cfg[12], 16, 2, clk_cfg_update[1], 19),
276 CKSYS_MUX_UPD(CLK_CK_PEXTP_MBIST_SEL, clk_cfg[12], 24, 1, clk_cfg_update[1], 20),
277 CKSYS_MUX_UPD(CLK_CK_AUD_1_SEL, clk_cfg[13], 0, 1, clk_cfg_update[1], 21),
278 CKSYS_MUX_UPD(CLK_CK_AUD_2_SEL, clk_cfg[13], 8, 1, clk_cfg_update[1], 22),
279 CKSYS_MUX_UPD(CLK_CK_ADSP_SEL, clk_cfg[13], 16, 1, clk_cfg_update[1], 23),
280 CKSYS_MUX_UPD(CLK_CK_ADSP_UARTHUB_BCLK_SEL, clk_cfg[13], 24, 2, clk_cfg_update[1], 24),
281 CKSYS_MUX_UPD(CLK_CK_DPMAIF_MAIN_SEL, clk_cfg[14], 0, 4, clk_cfg_update[1], 25),
282 CKSYS_MUX_UPD(CLK_CK_PWM_SEL, clk_cfg[14], 8, 2, clk_cfg_update[1], 26),
283 CKSYS_MUX_UPD(CLK_CK_MCUPM_SEL, clk_cfg[14], 16, 3, clk_cfg_update[1], 27),
284 CKSYS_MUX_UPD(CLK_CK_SFLASH_SEL, clk_cfg[14], 24, 2, clk_cfg_update[1], 28),
285 CKSYS_MUX_UPD(CLK_CK_IPSEAST_SEL, clk_cfg[15], 0, 3, clk_cfg_update[1], 29),
286 CKSYS_MUX_UPD(CLK_CK_IPSWEST_SEL, clk_cfg[15], 8, 3, clk_cfg_update[1], 30),
287 CKSYS_MUX_UPD(CLK_CK_TL_SEL, clk_cfg[15], 16, 2, clk_cfg_update[2], 0),
288 CKSYS_MUX_UPD(CLK_CK_TL_P1_SEL, clk_cfg[15], 24, 2, clk_cfg_update[2], 1),
289 CKSYS_MUX_UPD(CLK_CK_TL_P2_SEL, clk_cfg[16], 0, 2, clk_cfg_update[2], 2),
290 CKSYS_MUX_UPD(CLK_CK_EMI_INTERFACE_546_SEL, clk_cfg[16], 8, 1, clk_cfg_update[2], 3),
291 CKSYS_MUX_UPD(CLK_CK_SDF_SEL, clk_cfg[16], 16, 3, clk_cfg_update[2], 4),
292 CKSYS_MUX_UPD(CLK_CK_UARTHUB_BCLK_SEL, clk_cfg[16], 24, 2, clk_cfg_update[2], 5),
293 CKSYS_MUX_UPD(CLK_CK_DPSW_CMP_26M_SEL, clk_cfg[17], 0, 1, clk_cfg_update[2], 6),
294 CKSYS_MUX_UPD(CLK_CK_SMAPCK_SEL, clk_cfg[17], 8, 1, clk_cfg_update[2], 7),
295 CKSYS_MUX_UPD(CLK_CK_SSR_PKA_SEL, clk_cfg[17], 16, 3, clk_cfg_update[2], 8),
296 CKSYS_MUX_UPD(CLK_CK_SSR_DMA_SEL, clk_cfg[17], 24, 3, clk_cfg_update[2], 9),
297 CKSYS_MUX_UPD(CLK_CK_SSR_KDF_SEL, clk_cfg[18], 0, 2, clk_cfg_update[2], 10),
298 CKSYS_MUX_UPD(CLK_CK_SSR_RNG_SEL, clk_cfg[18], 8, 2, clk_cfg_update[2], 11),
299 CKSYS_MUX_UPD(CLK_CK_SPU0_SEL, clk_cfg[18], 16, 3, clk_cfg_update[2], 12),
300 CKSYS_MUX_UPD(CLK_CK_SPU1_SEL, clk_cfg[18], 24, 3, clk_cfg_update[2], 13),
301 CKSYS_MUX_UPD(CLK_CK_DXCC_SEL, clk_cfg[19], 0, 2, clk_cfg_update[2], 14),
302 CKSYS_MUX_UPD(CLK_CK_SPU0_BOOT_SEL, clk_cfg[19], 8, 1, clk_cfg_update[2], 15),
303 CKSYS_MUX_UPD(CLK_CK_SPU1_BOOT_SEL, clk_cfg[19], 16, 1, clk_cfg_update[2], 16),
304 CKSYS_MUX_UPD(CLK_CK_SGMII0_REF_325M_SEL, clk_cfg[19], 24, 1, clk_cfg_update[2], 17),
305 CKSYS_MUX_UPD(CLK_CK_SGMII0_REG_SEL, clk_cfg[20], 0, 1, clk_cfg_update[2], 18),
306 CKSYS_MUX_UPD(CLK_CK_SGMII1_REF_325M_SEL, clk_cfg[20], 8, 1, clk_cfg_update[2], 19),
307 CKSYS_MUX_UPD(CLK_CK_SGMII1_REG_SEL, clk_cfg[20], 16, 1, clk_cfg_update[2], 20),
308 CKSYS_MUX_UPD(CLK_CK_GMAC_312P5M_SEL, clk_cfg[20], 24, 1, clk_cfg_update[2], 21),
309 CKSYS_MUX_UPD(CLK_CK_GMAC_125M_SEL, clk_cfg[21], 0, 1, clk_cfg_update[2], 22),
310 CKSYS_MUX_UPD(CLK_CK_GMAC_RMII_SEL, clk_cfg[21], 8, 1, clk_cfg_update[2], 23),
311 CKSYS_MUX_UPD(CLK_CK_GMAC_62P4M_PTP_SEL, clk_cfg[21], 16, 2, clk_cfg_update[2], 24),
312 CKSYS_MUX_UPD(CLK_CK_DUMMY1_SEL, clk_cfg[21], 24, 2, clk_cfg_update[2], 25),
313 CKSYS_MUX_UPD(CLK_CK_DUMMY2_SEL, clk_cfg[22], 0, 2, clk_cfg_update[2], 26),
314 };
315
316 static const struct mux_sel mux_sels[] = {
317 { .id = CLK_CK_AXI_SEL, .sel = 5 },
318 { .id = CLK_CK_MEM_SUB_SEL, .sel = 10 },
319 { .id = CLK_CK_IO_NOC_SEL, .sel = 5 },
320 { .id = CLK_CK_P_AXI_SEL, .sel = 7 },
321 { .id = CLK_CK_PEXTP0_AXI_SEL, .sel = 7 },
322 { .id = CLK_CK_PEXTP1_USB_AXI_SEL, .sel = 7 },
323 { .id = CLK_CK_P_FMEM_SUB_SEL, .sel = 10 },
324 { .id = CLK_CK_PEXPT0_MEM_SUB_SEL, .sel = 10 },
325 { .id = CLK_CK_PEXTP1_USB_MEM_SUB_SEL, .sel = 10 },
326 { .id = CLK_CK_P_NOC_SEL, .sel = 11 },
327 { .id = CLK_CK_EMI_N_SEL, .sel = 5 },
328 { .id = CLK_CK_EMI_S_SEL, .sel = 5 },
329 { .id = CLK_CK_EMI_SLICE_N_SEL, .sel = 2 },
330 { .id = CLK_CK_EMI_SLICE_S_SEL, .sel = 2 },
331 { .id = CLK_CK_AP2CONN_HOST_SEL, .sel = 1 },
332 { .id = CLK_CK_ATB_SEL, .sel = 3 },
333 { .id = CLK_CK_CIRQ_SEL, .sel = 2 },
334 { .id = CLK_CK_PBUS_156M_SEL, .sel = 3 },
335 { .id = CLK_CK_NOC_LOW_SEL, .sel = 5 },
336 { .id = CLK_CK_NOC_MID_SEL, .sel = 7 },
337 { .id = CLK_CK_EFUSE_SEL, .sel = 0 },
338 { .id = CLK_CK_MCL3GIC_SEL, .sel = 3 },
339 { .id = CLK_CK_MCINFRA_SEL, .sel = 5 },
340 { .id = CLK_CK_DSP_SEL, .sel = 5 },
341 { .id = CLK_CK_MFG_REF_SEL, .sel = 0 },
342 { .id = CLK_CK_MFGSC_REF_SEL, .sel = 0 },
343 { .id = CLK_CK_MFG_EB_SEL, .sel = 3 },
344 { .id = CLK_CK_UART_SEL, .sel = 0 },
345 { .id = CLK_CK_SPI0_BCLK_SEL, .sel = 7 },
346 { .id = CLK_CK_SPI1_BCLK_SEL, .sel = 7 },
347 { .id = CLK_CK_SPI2_BCLK_SEL, .sel = 7 },
348 { .id = CLK_CK_SPI3_BCLK_SEL, .sel = 7 },
349 { .id = CLK_CK_SPI4_BCLK_SEL, .sel = 7 },
350 { .id = CLK_CK_SPI5_BCLK_SEL, .sel = 7 },
351 { .id = CLK_CK_SPI6_BCLK_SEL, .sel = 7 },
352 { .id = CLK_CK_SPI7_BCLK_SEL, .sel = 7 },
353 { .id = CLK_CK_MSDC_MACRO_1P_SEL, .sel = 4 },
354 { .id = CLK_CK_MSDC_MACRO_2P_SEL, .sel = 4 },
355 { .id = CLK_CK_MSDC30_1_SEL, .sel = 4 },
356 { .id = CLK_CK_MSDC30_2_SEL, .sel = 4 },
357 { .id = CLK_CK_DISP_PWM_SEL, .sel = 5 },
358 { .id = CLK_CK_USB_TOP_1P_SEL, .sel = 1 },
359 { .id = CLK_CK_USB_XHCI_1P_SEL, .sel = 1 },
360 { .id = CLK_CK_USB_FMCNT_P1_SEL, .sel = 1 },
361 { .id = CLK_CK_I2C_P_SEL, .sel = 2 },
362 { .id = CLK_CK_I2C_EAST_SEL, .sel = 2 },
363 { .id = CLK_CK_I2C_WEST_SEL, .sel = 2 },
364 { .id = CLK_CK_I2C_NORTH_SEL, .sel = 2 },
365 { .id = CLK_CK_AES_UFSFDE_SEL, .sel = 5 },
366 { .id = CLK_CK_SEL, .sel = 6 },
367 { .id = CLK_CK_MBIST_SEL, .sel = 3 },
368 { .id = CLK_CK_PEXTP_MBIST_SEL, .sel = 1 },
369 { .id = CLK_CK_AUD_1_SEL, .sel = 1 },
370 { .id = CLK_CK_AUD_2_SEL, .sel = 1 },
371 { .id = CLK_CK_ADSP_SEL, .sel = 1 },
372 { .id = CLK_CK_ADSP_UARTHUB_BCLK_SEL, .sel = 0 },
373 { .id = CLK_CK_DPMAIF_MAIN_SEL, .sel = 3 },
374 { .id = CLK_CK_PWM_SEL, .sel = 0 },
375 { .id = CLK_CK_MCUPM_SEL, .sel = 4 },
376 { .id = CLK_CK_SFLASH_SEL, .sel = 2 },
377 { .id = CLK_CK_IPSEAST_SEL, .sel = 1 },
378 { .id = CLK_CK_IPSWEST_SEL, .sel = 1 },
379 { .id = CLK_CK_TL_SEL, .sel = 2 },
380 { .id = CLK_CK_TL_P1_SEL, .sel = 3 },
381 { .id = CLK_CK_TL_P2_SEL, .sel = 2 },
382 { .id = CLK_CK_EMI_INTERFACE_546_SEL, .sel = 1 },
383 { .id = CLK_CK_SDF_SEL, .sel = 5 },
384 { .id = CLK_CK_UARTHUB_BCLK_SEL, .sel = 0 },
385 { .id = CLK_CK_DPSW_CMP_26M_SEL, .sel = 1 },
386 { .id = CLK_CK_SMAPCK_SEL, .sel = 1 },
387 { .id = CLK_CK_SSR_PKA_SEL, .sel = 5 },
388 { .id = CLK_CK_SSR_DMA_SEL, .sel = 5 },
389 { .id = CLK_CK_SSR_KDF_SEL, .sel = 3 },
390 { .id = CLK_CK_SSR_RNG_SEL, .sel = 3 },
391 { .id = CLK_CK_SPU0_SEL, .sel = 1 },
392 { .id = CLK_CK_SPU1_SEL, .sel = 1 },
393 { .id = CLK_CK_DXCC_SEL, .sel = 0 },
394 { .id = CLK_CK_SPU0_BOOT_SEL, .sel = 1 },
395 { .id = CLK_CK_SPU1_BOOT_SEL, .sel = 1 },
396 { .id = CLK_CK_SGMII0_REF_325M_SEL, .sel = 1 },
397 { .id = CLK_CK_SGMII0_REG_SEL, .sel = 1 },
398 { .id = CLK_CK_SGMII1_REF_325M_SEL, .sel = 1 },
399 { .id = CLK_CK_SGMII1_REG_SEL, .sel = 1 },
400 { .id = CLK_CK_GMAC_312P5M_SEL, .sel = 1 },
401 { .id = CLK_CK_GMAC_125M_SEL, .sel = 1 },
402 { .id = CLK_CK_GMAC_RMII_SEL, .sel = 1 },
403 { .id = CLK_CK_GMAC_62P4M_PTP_SEL, .sel = 2 },
404 { .id = CLK_CK_DUMMY1_SEL, .sel = 3 },
405 { .id = CLK_CK_DUMMY2_SEL, .sel = 3 },
406 };
407
408 static const struct mux cksys2_muxes[] = {
409 CKSYS2_MUX_UPD(CLK_CK2_SENINF0_SEL, cksys2_clk_cfg[0], 0, 4,
410 cksys2_clk_cfg_update, 0),
411 CKSYS2_MUX_UPD(CLK_CK2_SENINF1_SEL, cksys2_clk_cfg[0], 8, 4,
412 cksys2_clk_cfg_update, 1),
413 CKSYS2_MUX_UPD(CLK_CK2_SENINF2_SEL, cksys2_clk_cfg[0], 16, 4,
414 cksys2_clk_cfg_update, 2),
415 CKSYS2_MUX_UPD(CLK_CK2_SENINF3_SEL, cksys2_clk_cfg[0], 24, 4,
416 cksys2_clk_cfg_update, 3),
417 CKSYS2_MUX_UPD(CLK_CK2_SENINF4_SEL, cksys2_clk_cfg[1], 0, 4,
418 cksys2_clk_cfg_update, 4),
419 CKSYS2_MUX_UPD(CLK_CK2_SENINF5_SEL, cksys2_clk_cfg[1], 8, 4,
420 cksys2_clk_cfg_update, 5),
421 CKSYS2_MUX_UPD(CLK_CK2_IMG1_SEL, cksys2_clk_cfg[1], 16, 4,
422 cksys2_clk_cfg_update, 6),
423 CKSYS2_MUX_UPD(CLK_CK2_IPE_SEL, cksys2_clk_cfg[1], 24, 4,
424 cksys2_clk_cfg_update, 7),
425 CKSYS2_MUX_UPD(CLK_CK2_CAM_SEL, cksys2_clk_cfg[2], 0, 4,
426 cksys2_clk_cfg_update, 8),
427 CKSYS2_MUX_UPD(CLK_CK2_CAMTM_SEL, cksys2_clk_cfg[2], 8, 3,
428 cksys2_clk_cfg_update, 9),
429 CKSYS2_MUX_UPD(CLK_CK2_DPE_SEL, cksys2_clk_cfg[2], 16, 4,
430 cksys2_clk_cfg_update, 10),
431 CKSYS2_MUX_UPD(CLK_CK2_VDEC_SEL, cksys2_clk_cfg[2], 24, 4,
432 cksys2_clk_cfg_update, 11),
433 CKSYS2_MUX_UPD(CLK_CK2_CCUSYS_SEL, cksys2_clk_cfg[3], 0, 4,
434 cksys2_clk_cfg_update, 12),
435 CKSYS2_MUX_UPD(CLK_CK2_CCUTM_SEL, cksys2_clk_cfg[3], 8, 3,
436 cksys2_clk_cfg_update, 13),
437 CKSYS2_MUX_UPD(CLK_CK2_VENC_SEL, cksys2_clk_cfg[3], 16, 4,
438 cksys2_clk_cfg_update, 14),
439 CKSYS2_MUX_UPD(CLK_CK2_DVO_SEL, cksys2_clk_cfg[3], 24, 3,
440 cksys2_clk_cfg_update, 15),
441 CKSYS2_MUX_UPD(CLK_CK2_DVO_FAVT_SEL, cksys2_clk_cfg[4], 0, 3,
442 cksys2_clk_cfg_update, 16),
443 CKSYS2_MUX_UPD(CLK_CK2_DP1_SEL, cksys2_clk_cfg[4], 8, 3,
444 cksys2_clk_cfg_update, 17),
445 CKSYS2_MUX_UPD(CLK_CK2_DP0_SEL, cksys2_clk_cfg[4], 16, 3,
446 cksys2_clk_cfg_update, 18),
447 CKSYS2_MUX_UPD(CLK_CK2_DISP_SEL, cksys2_clk_cfg[4], 24, 4,
448 cksys2_clk_cfg_update, 19),
449 CKSYS2_MUX_UPD(CLK_CK2_MDP_SEL, cksys2_clk_cfg[5], 0, 4,
450 cksys2_clk_cfg_update, 20),
451 CKSYS2_MUX_UPD(CLK_CK2_MMINFRA_SEL, cksys2_clk_cfg[5], 8, 4,
452 cksys2_clk_cfg_update, 21),
453 CKSYS2_MUX_UPD(CLK_CK2_MMINFRA_SNOC_SEL, cksys2_clk_cfg[5], 16, 4,
454 cksys2_clk_cfg_update, 22),
455 CKSYS2_MUX_UPD(CLK_CK2_MMUP_SEL, cksys2_clk_cfg[5], 24, 3,
456 cksys2_clk_cfg_update, 23),
457 CKSYS2_MUX_UPD(CLK_CK2_DUMMY1_SEL, cksys2_clk_cfg[6], 0, 2,
458 cksys2_clk_cfg_update, 24),
459 CKSYS2_MUX_UPD(CLK_CK2_DUMMY2_SEL, cksys2_clk_cfg[6], 8, 2,
460 cksys2_clk_cfg_update, 25),
461 CKSYS2_MUX_UPD(CLK_CK2_MMINFRA_AO_SEL, cksys2_clk_cfg[6], 16, 2,
462 cksys2_clk_cfg_update, 26),
463 };
464
465 static const struct mux_sel cksys2_mux_sels[] = {
466 { .id = CLK_CK2_SENINF0_SEL, .sel = 9 },
467 { .id = CLK_CK2_SENINF1_SEL, .sel = 9 },
468 { .id = CLK_CK2_SENINF2_SEL, .sel = 9 },
469 { .id = CLK_CK2_SENINF3_SEL, .sel = 9 },
470 { .id = CLK_CK2_SENINF4_SEL, .sel = 9 },
471 { .id = CLK_CK2_SENINF5_SEL, .sel = 9 },
472 { .id = CLK_CK2_IMG1_SEL, .sel = 7 },
473 { .id = CLK_CK2_IPE_SEL, .sel = 10 },
474 { .id = CLK_CK2_CAM_SEL, .sel = 14 },
475 { .id = CLK_CK2_CAMTM_SEL, .sel = 4 },
476 { .id = CLK_CK2_DPE_SEL, .sel = 8 },
477 { .id = CLK_CK2_VDEC_SEL, .sel = 12 },
478 { .id = CLK_CK2_CCUSYS_SEL, .sel = 12 },
479 { .id = CLK_CK2_CCUTM_SEL, .sel = 4 },
480 { .id = CLK_CK2_VENC_SEL, .sel = 13 },
481 { .id = CLK_CK2_DVO_SEL, .sel = 4 },
482 { .id = CLK_CK2_DVO_FAVT_SEL, .sel = 6 },
483 { .id = CLK_CK2_DP1_SEL, .sel = 4 },
484 { .id = CLK_CK2_DP0_SEL, .sel = 4 },
485 { .id = CLK_CK2_DISP_SEL, .sel = 8 },
486 { .id = CLK_CK2_MDP_SEL, .sel = 12 },
487 { .id = CLK_CK2_MMINFRA_SEL, .sel = 13 },
488 { .id = CLK_CK2_MMINFRA_SNOC_SEL, .sel = 11 },
489 { .id = CLK_CK2_MMUP_SEL, .sel = 7 },
490 { .id = CLK_CK2_DUMMY1_SEL, .sel = 3 },
491 { .id = CLK_CK2_DUMMY2_SEL, .sel = 3 },
492 { .id = CLK_CK2_MMINFRA_AO_SEL, .sel = 2 },
493 };
494
495 static const struct mux vlp_muxes[] = {
496 VLP_MUX_UPD(CLK_VLP_CK_SCP_SEL, vlp_clk_cfg[0], 0, 3,
497 vlp_clk_cfg_update[0], 0),
498 VLP_MUX_UPD(CLK_VLP_CK_SCP_SPI_SEL, vlp_clk_cfg[0], 8, 2,
499 vlp_clk_cfg_update[0], 1),
500 VLP_MUX_UPD(CLK_VLP_CK_SCP_IIC_SEL, vlp_clk_cfg[0], 16, 2,
501 vlp_clk_cfg_update[0], 2),
502 VLP_MUX_UPD(CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL, vlp_clk_cfg[0], 24, 3,
503 vlp_clk_cfg_update[0], 3),
504 VLP_MUX_UPD(CLK_VLP_CK_PWRAP_ULPOSC_SEL, vlp_clk_cfg[1], 0, 2,
505 vlp_clk_cfg_update[0], 4),
506 VLP_MUX_UPD(CLK_VLP_CK_SPMI_M_TIA_32K_SEL, vlp_clk_cfg[1], 8, 3,
507 vlp_clk_cfg_update[0], 5),
508 VLP_MUX_UPD(CLK_VLP_CK_APXGPT_26M_BCLK_SEL, vlp_clk_cfg[1], 16, 1,
509 vlp_clk_cfg_update[0], 6),
510 VLP_MUX_UPD(CLK_VLP_CK_DPSW_SEL, vlp_clk_cfg[1], 24, 2,
511 vlp_clk_cfg_update[0], 7),
512 VLP_MUX_UPD(CLK_VLP_CK_DPSW_CENTRAL_SEL, vlp_clk_cfg[2], 0, 2,
513 vlp_clk_cfg_update[0], 8),
514 VLP_MUX_UPD(CLK_VLP_CK_SPMI_M_MST_SEL, vlp_clk_cfg[2], 8, 2,
515 vlp_clk_cfg_update[0], 9),
516 VLP_MUX_UPD(CLK_VLP_CK_DVFSRC_SEL, vlp_clk_cfg[2], 16, 1,
517 vlp_clk_cfg_update[0], 10),
518 VLP_MUX_UPD(CLK_VLP_CK_PWM_VLP_SEL, vlp_clk_cfg[2], 24, 3,
519 vlp_clk_cfg_update[0], 11),
520 VLP_MUX_UPD(CLK_VLP_CK_AXI_VLP_SEL, vlp_clk_cfg[3], 0, 3,
521 vlp_clk_cfg_update[0], 12),
522 VLP_MUX_UPD(CLK_VLP_CK_SYSTIMER_26M_SEL, vlp_clk_cfg[3], 8, 1,
523 vlp_clk_cfg_update[0], 13),
524 VLP_MUX_UPD(CLK_VLP_CK_SSPM_SEL, vlp_clk_cfg[3], 16, 3,
525 vlp_clk_cfg_update[0], 14),
526 VLP_MUX_UPD(CLK_VLP_CK_SRCK_SEL, vlp_clk_cfg[3], 24, 1,
527 vlp_clk_cfg_update[0], 15),
528 VLP_MUX_UPD(CLK_VLP_CK_CAMTG0_SEL, vlp_clk_cfg[4], 0, 4,
529 vlp_clk_cfg_update[0], 16),
530 VLP_MUX_UPD(CLK_VLP_CK_CAMTG1_SEL, vlp_clk_cfg[4], 8, 4,
531 vlp_clk_cfg_update[0], 17),
532 VLP_MUX_UPD(CLK_VLP_CK_CAMTG2_SEL, vlp_clk_cfg[4], 16, 4,
533 vlp_clk_cfg_update[0], 18),
534 VLP_MUX_UPD(CLK_VLP_CK_CAMTG3_SEL, vlp_clk_cfg[4], 24, 4,
535 vlp_clk_cfg_update[0], 19),
536 VLP_MUX_UPD(CLK_VLP_CK_CAMTG4_SEL, vlp_clk_cfg[5], 0, 4,
537 vlp_clk_cfg_update[0], 20),
538 VLP_MUX_UPD(CLK_VLP_CK_CAMTG5_SEL, vlp_clk_cfg[5], 8, 4,
539 vlp_clk_cfg_update[0], 21),
540 VLP_MUX_UPD(CLK_VLP_CK_CAMTG6_SEL, vlp_clk_cfg[5], 16, 4,
541 vlp_clk_cfg_update[0], 22),
542 VLP_MUX_UPD(CLK_VLP_CK_CAMTG7_SEL, vlp_clk_cfg[5], 24, 4,
543 vlp_clk_cfg_update[0], 23),
544 VLP_MUX_UPD(CLK_VLP_CK_IPS_SEL, vlp_clk_cfg[6], 0, 2,
545 vlp_clk_cfg_update[0], 24),
546 VLP_MUX_UPD(CLK_VLP_CK_SSPM_26M_SEL, vlp_clk_cfg[6], 8, 1,
547 vlp_clk_cfg_update[0], 25),
548 VLP_MUX_UPD(CLK_VLP_CK_ULPOSC_SSPM_SEL, vlp_clk_cfg[6], 16, 2,
549 vlp_clk_cfg_update[0], 26),
550 VLP_MUX_UPD(CLK_VLP_CK_VLP_PBUS_26M_SEL, vlp_clk_cfg[6], 24, 1,
551 vlp_clk_cfg_update[0], 27),
552 VLP_MUX_UPD(CLK_VLP_CK_DEBUG_ERR_FLAG_SEL, vlp_clk_cfg[7], 0, 1,
553 vlp_clk_cfg_update[0], 28),
554 VLP_MUX_UPD(CLK_VLP_CK_DPMSRDMA_SEL, vlp_clk_cfg[7], 8, 1,
555 vlp_clk_cfg_update[0], 29),
556 VLP_MUX_UPD(CLK_VLP_CK_VLP_PBUS_156M_SEL, vlp_clk_cfg[7], 16, 2,
557 vlp_clk_cfg_update[0], 30),
558 VLP_MUX_UPD(CLK_VLP_CK_SPM_SEL, vlp_clk_cfg[7], 24, 1,
559 vlp_clk_cfg_update[1], 0),
560 VLP_MUX_UPD(CLK_VLP_CK_MMINFRA_VLP_SEL, vlp_clk_cfg[8], 0, 2,
561 vlp_clk_cfg_update[1], 1),
562 VLP_MUX_UPD(CLK_VLP_CK_USB_TOP_SEL, vlp_clk_cfg[8], 8, 1,
563 vlp_clk_cfg_update[1], 2),
564 VLP_MUX_UPD(CLK_VLP_CK_USB_XHCI_SEL, vlp_clk_cfg[8], 16, 1,
565 vlp_clk_cfg_update[1], 3),
566 VLP_MUX_UPD(CLK_VLP_CK_NOC_VLP_SEL, vlp_clk_cfg[8], 24, 2,
567 vlp_clk_cfg_update[1], 4),
568 VLP_MUX_UPD(CLK_VLP_CK_AUDIO_H_SEL, vlp_clk_cfg[9], 0, 2,
569 vlp_clk_cfg_update[1], 5),
570 VLP_MUX_UPD(CLK_VLP_CK_AUD_ENGEN1_SEL, vlp_clk_cfg[9], 8, 2,
571 vlp_clk_cfg_update[1], 6),
572 VLP_MUX_UPD(CLK_VLP_CK_AUD_ENGEN2_SEL, vlp_clk_cfg[9], 16, 2,
573 vlp_clk_cfg_update[1], 7),
574 VLP_MUX_UPD(CLK_VLP_CK_AUD_INTBUS_SEL, vlp_clk_cfg[9], 24, 2,
575 vlp_clk_cfg_update[1], 8),
576 VLP_MUX_UPD(CLK_VLP_CK_SPVLP_26M_SEL, vlp_clk_cfg[10], 0, 1,
577 vlp_clk_cfg_update[1], 9),
578 VLP_MUX_UPD(CLK_VLP_CK_SPU0_VLP_SEL, vlp_clk_cfg[10], 8, 3,
579 vlp_clk_cfg_update[1], 10),
580 VLP_MUX_UPD(CLK_VLP_CK_SPU1_VLP_SEL, vlp_clk_cfg[10], 16, 3,
581 vlp_clk_cfg_update[1], 11),
582 VLP_MUX_UPD(CLK_VLP_CK_VLP_DUMMY1_SEL, vlp_clk_cfg[10], 24, 3,
583 vlp_clk_cfg_update[1], 12),
584 VLP_MUX_UPD(CLK_VLP_CK_VLP_DUMMY2_SEL, vlp_clk_cfg[11], 0, 3,
585 vlp_clk_cfg_update[1], 13),
586 };
587
588 static const struct mux_sel vlp_mux_sels[] = {
589 { .id = CLK_VLP_CK_SCP_SEL, .sel = 0 },
590 { .id = CLK_VLP_CK_SCP_SPI_SEL, .sel = 0 },
591 { .id = CLK_VLP_CK_SCP_IIC_SEL, .sel = 0 },
592 { .id = CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL, .sel = 0 },
593 { .id = CLK_VLP_CK_PWRAP_ULPOSC_SEL, .sel = 1 },
594 { .id = CLK_VLP_CK_SPMI_M_TIA_32K_SEL, .sel = 2 },
595 { .id = CLK_VLP_CK_APXGPT_26M_BCLK_SEL, .sel = 0 },
596 { .id = CLK_VLP_CK_DPSW_SEL, .sel = 2 },
597 { .id = CLK_VLP_CK_DPSW_CENTRAL_SEL, .sel = 2 },
598 { .id = CLK_VLP_CK_SPMI_M_MST_SEL, .sel = 1 },
599 { .id = CLK_VLP_CK_DVFSRC_SEL, .sel = 0 },
600 { .id = CLK_VLP_CK_PWM_VLP_SEL, .sel = 0 },
601 { .id = CLK_VLP_CK_AXI_VLP_SEL, .sel = 4 },
602 { .id = CLK_VLP_CK_SYSTIMER_26M_SEL, .sel = 0 },
603 { .id = CLK_VLP_CK_SSPM_SEL, .sel = 4 },
604 { .id = CLK_VLP_CK_SRCK_SEL, .sel = 1 },
605 { .id = CLK_VLP_CK_CAMTG0_SEL, .sel = 7 },
606 { .id = CLK_VLP_CK_CAMTG1_SEL, .sel = 7 },
607 { .id = CLK_VLP_CK_CAMTG2_SEL, .sel = 7 },
608 { .id = CLK_VLP_CK_CAMTG3_SEL, .sel = 7 },
609 { .id = CLK_VLP_CK_CAMTG4_SEL, .sel = 7 },
610 { .id = CLK_VLP_CK_CAMTG5_SEL, .sel = 7 },
611 { .id = CLK_VLP_CK_CAMTG6_SEL, .sel = 7 },
612 { .id = CLK_VLP_CK_CAMTG7_SEL, .sel = 7 },
613 { .id = CLK_VLP_CK_IPS_SEL, .sel = 2 },
614 { .id = CLK_VLP_CK_SSPM_26M_SEL, .sel = 0 },
615 { .id = CLK_VLP_CK_ULPOSC_SSPM_SEL, .sel = 1 },
616 { .id = CLK_VLP_CK_VLP_PBUS_26M_SEL, .sel = 1 },
617 { .id = CLK_VLP_CK_DEBUG_ERR_FLAG_SEL, .sel = 0 },
618 { .id = CLK_VLP_CK_DPMSRDMA_SEL, .sel = 1 },
619 { .id = CLK_VLP_CK_VLP_PBUS_156M_SEL, .sel = 3 },
620 { .id = CLK_VLP_CK_SPM_SEL, .sel = 1 },
621 { .id = CLK_VLP_CK_MMINFRA_VLP_SEL, .sel = 2 },
622 { .id = CLK_VLP_CK_USB_TOP_SEL, .sel = 1 },
623 { .id = CLK_VLP_CK_USB_XHCI_SEL, .sel = 1 },
624 { .id = CLK_VLP_CK_NOC_VLP_SEL, .sel = 2 },
625 { .id = CLK_VLP_CK_AUDIO_H_SEL, .sel = 3 },
626 { .id = CLK_VLP_CK_AUD_ENGEN1_SEL, .sel = 3 },
627 { .id = CLK_VLP_CK_AUD_ENGEN2_SEL, .sel = 3 },
628 { .id = CLK_VLP_CK_AUD_INTBUS_SEL, .sel = 3 },
629 { .id = CLK_VLP_CK_SPVLP_26M_SEL, .sel = 0 },
630 { .id = CLK_VLP_CK_SPU0_VLP_SEL, .sel = 6 },
631 { .id = CLK_VLP_CK_SPU1_VLP_SEL, .sel = 6 },
632 { .id = CLK_VLP_CK_VLP_DUMMY1_SEL, .sel = 4 },
633 { .id = CLK_VLP_CK_VLP_DUMMY2_SEL, .sel = 4 },
634 };
635
636 enum pll_id {
637 CLK_APMIXED_MAINPLL,
638 CLK_APMIXED_UNIVPLL,
639 CLK_APMIXED_MSDCPLL,
640 CLK_APMIXED_ADSPPLL,
641 CLK_APMIXED2_MAINPLL2,
642 CLK_APMIXED2_UNIVPLL2,
643 CLK_APMIXED2_MMPLL2,
644 CLK_APMIXED2_IMGPLL,
645 CLK_APMIXED2_TVDPLL1,
646 CLK_APMIXED2_TVDPLL2,
647 CLK_APMIXED2_TVDPLL3,
648 CLK_VLP_APLL1,
649 CLK_VLP_APLL2,
650 };
651
652 enum mcusys_pll_id {
653 CLK_CPLL_ARMPLL_LL,
654 CLK_CPBL_ARMPLL_BL,
655 CLK_CPB_ARMPLL_B,
656 CLK_CCIPLL,
657 CLK_PTPPLL,
658 };
659
660 enum mfg_pll_id {
661 CLK_MFG_AO_MFGPLL,
662 CLK_MFGSC0_AO_MFGPLL_SC0,
663 CLK_MFGSC1_AO_MFGPLL_SC1,
664 };
665
666 struct rate {
667 u8 id;
668 u32 rate;
669 };
670
671 static const struct rate pll_rates[] = {
672 { .id = CLK_APMIXED_MAINPLL, .rate = MAINPLL_HZ },
673 { .id = CLK_APMIXED_UNIVPLL, .rate = UNIVPLL_HZ },
674 { .id = CLK_APMIXED_MSDCPLL, .rate = MSDCPLL_HZ },
675 { .id = CLK_APMIXED_ADSPPLL, .rate = ADSPPLL_HZ },
676 { .id = CLK_APMIXED2_MAINPLL2, .rate = MAINPLL2_HZ },
677 { .id = CLK_APMIXED2_UNIVPLL2, .rate = UNIVPLL2_HZ },
678 { .id = CLK_APMIXED2_MMPLL2, .rate = MMPLL2_HZ },
679 { .id = CLK_APMIXED2_IMGPLL, .rate = IMGPLL_HZ },
680 { .id = CLK_APMIXED2_TVDPLL1, .rate = TVDPLL1_HZ },
681 { .id = CLK_APMIXED2_TVDPLL2, .rate = TVDPLL2_HZ },
682 { .id = CLK_APMIXED2_TVDPLL3, .rate = TVDPLL3_HZ },
683 { .id = CLK_VLP_APLL1, .rate = VLP_APLL1_HZ },
684 { .id = CLK_VLP_APLL2, .rate = VLP_APLL2_HZ },
685 };
686
687 static const struct rate mcusys_pll_rates[] = {
688 { .id = CLK_CPLL_ARMPLL_LL, .rate = ARMPLL_LL_HZ },
689 { .id = CLK_CPBL_ARMPLL_BL, .rate = ARMPLL_BL_HZ },
690 { .id = CLK_CPB_ARMPLL_B, .rate = ARMPLL_B_HZ },
691 { .id = CLK_CCIPLL, .rate = CCIPLL_HZ },
692 { .id = CLK_PTPPLL, .rate = PTPPLL_HZ },
693 };
694
695 static const struct rate mfg_pll_rates[] = {
696 { .id = CLK_MFG_AO_MFGPLL, .rate = MFGPLL_HZ },
697 { .id = CLK_MFGSC0_AO_MFGPLL_SC0, .rate = MFGPLL_SC0_HZ },
698 { .id = CLK_MFGSC1_AO_MFGPLL_SC1, .rate = MFGPLL_SC1_HZ },
699 };
700
701 static const u32 pll_div_rate[] = {
702 3800UL * MHz,
703 1900 * MHz,
704 950 * MHz,
705 475 * MHz,
706 237500 * KHz,
707 0,
708 };
709
710 #define PLL_SYS(_id, _sys, _reg, _rstb, _pcwbits, _div_reg, _div_shift, \
711 _pcw_reg, _pcw_shift, _div_rate) \
712 [_id] = { \
713 .reg = &_sys->_reg, \
714 .rstb_shift = _rstb, \
715 .pcwbits = _pcwbits, \
716 .div_reg = &_sys->_div_reg, \
717 .div_shift = _div_shift, \
718 .pcw_reg = &_sys->_pcw_reg, \
719 .pcw_shift = _pcw_shift, \
720 .div_rate = _div_rate, \
721 }
722
723 static const struct pll plls[] = {
724 PLL_SYS(CLK_APMIXED_MAINPLL, mtk_apmixed, mainpll_con[0], 23, 22,
725 mainpll_con[1], 24, mainpll_con[1], 0, pll_div_rate),
726 PLL_SYS(CLK_APMIXED_UNIVPLL, mtk_apmixed, univpll_con[0], 23, 22,
727 univpll_con[1], 24, univpll_con[1], 0, pll_div_rate),
728 PLL_SYS(CLK_APMIXED_MSDCPLL, mtk_apmixed, msdcpll_con[0], NO_RSTB_SHIFT, 22,
729 msdcpll_con[1], 24, msdcpll_con[1], 0, pll_div_rate),
730 PLL_SYS(CLK_APMIXED_ADSPPLL, mtk_apmixed, adsppll_con[0], NO_RSTB_SHIFT, 22,
731 adsppll_con[1], 24, adsppll_con[1], 0, pll_div_rate),
732 PLL_SYS(CLK_APMIXED2_MAINPLL2, mtk_apmixed2, mainpll2_con[0], 23, 22,
733 mainpll2_con[1], 24, mainpll2_con[1], 0, pll_div_rate),
734 PLL_SYS(CLK_APMIXED2_UNIVPLL2, mtk_apmixed2, univpll2_con[0], 23, 22,
735 univpll2_con[1], 24, univpll2_con[1], 0, pll_div_rate),
736 PLL_SYS(CLK_APMIXED2_MMPLL2, mtk_apmixed2, mmpll2_con[0], 23, 22,
737 mmpll2_con[1], 24, mmpll2_con[1], 0, pll_div_rate),
738 PLL_SYS(CLK_APMIXED2_IMGPLL, mtk_apmixed2, imgpll_con[0], 23, 22,
739 imgpll_con[1], 24, imgpll_con[1], 0, pll_div_rate),
740 PLL_SYS(CLK_APMIXED2_TVDPLL1, mtk_apmixed2, tvdpll1_con[0], NO_RSTB_SHIFT, 22,
741 tvdpll1_con[1], 24, tvdpll1_con[1], 0, pll_div_rate),
742 PLL_SYS(CLK_APMIXED2_TVDPLL2, mtk_apmixed2, tvdpll2_con[0], NO_RSTB_SHIFT, 22,
743 tvdpll2_con[1], 24, tvdpll2_con[1], 0, pll_div_rate),
744 PLL_SYS(CLK_APMIXED2_TVDPLL3, mtk_apmixed2, tvdpll3_con[0], NO_RSTB_SHIFT, 22,
745 tvdpll3_con[1], 24, tvdpll3_con[1], 0, pll_div_rate),
746 PLL_SYS(CLK_VLP_APLL1, mtk_vlpsys, vlp_apll1_con[0], NO_RSTB_SHIFT, 32,
747 vlp_apll1_con[1], 24, vlp_apll1_con[2], 0, pll_div_rate),
748 PLL_SYS(CLK_VLP_APLL2, mtk_vlpsys, vlp_apll2_con[0], NO_RSTB_SHIFT, 32,
749 vlp_apll2_con[1], 24, vlp_apll2_con[2], 0, pll_div_rate),
750 };
751
752 static const struct pll mcusys_plls[] = {
753 PLL_SYS(CLK_CPLL_ARMPLL_LL, mtk_armpll_ll, pll_con[0], NO_RSTB_SHIFT, 22,
754 pll_con[1], 24, pll_con[1], 0, pll_div_rate),
755 PLL_SYS(CLK_CPBL_ARMPLL_BL, mtk_armpll_bl, pll_con[0], NO_RSTB_SHIFT, 22,
756 pll_con[1], 24, pll_con[1], 0, pll_div_rate),
757 PLL_SYS(CLK_CPB_ARMPLL_B, mtk_armpll_b, pll_con[0], NO_RSTB_SHIFT, 22,
758 pll_con[1], 24, pll_con[1], 0, pll_div_rate),
759 PLL_SYS(CLK_CCIPLL, mtk_ccipll, pll_con[0], NO_RSTB_SHIFT, 22,
760 pll_con[1], 24, pll_con[1], 0, pll_div_rate),
761 PLL_SYS(CLK_PTPPLL, mtk_ptppll, pll_con[0], NO_RSTB_SHIFT, 22,
762 pll_con[1], 24, pll_con[1], 0, pll_div_rate),
763 };
764
765 static const struct pll mfg_plls[] = {
766 PLL_SYS(CLK_MFG_AO_MFGPLL, mtk_mfgpll, pll_con[3],
767 NO_RSTB_SHIFT, 22, pll_con[1], 24, pll_con[1], 0, pll_div_rate),
768 PLL_SYS(CLK_MFGSC0_AO_MFGPLL_SC0, mtk_mfgpll_sc0, pll_con[3],
769 NO_RSTB_SHIFT, 22, pll_con[1], 24, pll_con[1], 0, pll_div_rate),
770 PLL_SYS(CLK_MFGSC1_AO_MFGPLL_SC1, mtk_mfgpll_sc1, pll_con[3],
771 NO_RSTB_SHIFT, 22, pll_con[1], 24, pll_con[1], 0, pll_div_rate),
772 };
773
774 enum fmeter_id {
775 VLP_CKSYS_CTRL,
776 MFGPLL_CTRL,
777 MFGPLL_SC0_CTRL,
778 MFGPLL_SC1_CTRL,
779 CCIPLL_CTRL,
780 ARMPLL_LL_CTRL,
781 ARMPLL_BL_CTRL,
782 ARMPLL_B_CTRL,
783 PTPPLL_CTRL,
784 };
785
786 struct fmeter_data {
787 u8 id;
788 void *pll_con0;
789 void *pll_con1;
790 void *pll_con5;
791 void *con0;
792 void *con1;
793 };
794
795 static const struct fmeter_data fmd[] = {
796 [VLP_CKSYS_CTRL] = {
797 VLP_CKSYS_CTRL, NULL, NULL, NULL,
798 &mtk_vlpsys->vlp_fqmtr_con[0], &mtk_vlpsys->vlp_fqmtr_con[1] },
799 [MFGPLL_CTRL] = {
800 MFGPLL_CTRL,
801 &mtk_mfgpll->pll_con[0], &mtk_mfgpll->pll_con[1],
802 &mtk_mfgpll->pll_con[5], &mtk_mfgpll->fqmtr_con[0],
803 &mtk_mfgpll->fqmtr_con[1] },
804 [MFGPLL_SC0_CTRL] = {
805 MFGPLL_SC0_CTRL,
806 &mtk_mfgpll_sc0->pll_con[0], &mtk_mfgpll_sc0->pll_con[1],
807 &mtk_mfgpll_sc0->pll_con[5], &mtk_mfgpll_sc0->fqmtr_con[0],
808 &mtk_mfgpll_sc0->fqmtr_con[1] },
809 [MFGPLL_SC1_CTRL] = {
810 MFGPLL_SC1_CTRL,
811 &mtk_mfgpll_sc1->pll_con[0], &mtk_mfgpll_sc1->pll_con[1],
812 &mtk_mfgpll_sc1->pll_con[5], &mtk_mfgpll_sc1->fqmtr_con[0],
813 &mtk_mfgpll_sc1->fqmtr_con[1] },
814 [CCIPLL_CTRL] = {
815 CCIPLL_CTRL,
816 &mtk_ccipll->pll_con[0], &mtk_ccipll->pll_con[1], 0,
817 &mtk_ccipll->fqmtr_con[0], &mtk_ccipll->fqmtr_con[1] },
818 [ARMPLL_LL_CTRL] = {
819 ARMPLL_LL_CTRL,
820 &mtk_armpll_ll->pll_con[0], &mtk_armpll_ll->pll_con[1], 0,
821 &mtk_armpll_ll->fqmtr_con[0], &mtk_armpll_ll->fqmtr_con[1] },
822 [ARMPLL_BL_CTRL] = {
823 ARMPLL_BL_CTRL,
824 &mtk_armpll_bl->pll_con[0], &mtk_armpll_bl->pll_con[1], 0,
825 &mtk_armpll_bl->fqmtr_con[0], &mtk_armpll_bl->fqmtr_con[1] },
826 [ARMPLL_B_CTRL] = {
827 ARMPLL_B_CTRL,
828 &mtk_armpll_b->pll_con[0], &mtk_armpll_b->pll_con[1], 0,
829 &mtk_armpll_b->fqmtr_con[0], &mtk_armpll_b->fqmtr_con[1] },
830 [PTPPLL_CTRL] = {
831 PTPPLL_CTRL,
832 &mtk_ptppll->pll_con[0], &mtk_ptppll->pll_con[1], 0,
833 &mtk_ptppll->fqmtr_con[0], &mtk_ptppll->fqmtr_con[1] },
834 };
835
836 #define PM_DUMMY 63
837
838 #define VOTE_OFS(ofs) ((void *)(uintptr_t)(VOTE_BASE + ofs))
839
840 #define VOTE_CTRL VOTE_OFS(0x150C)
841 #define VOTE_DCM VOTE_OFS(0x1510)
842 #define VOTE_REG_EN0 VOTE_OFS(0x1514)
843 #define VOTE_REG_EN1 VOTE_OFS(0x1518)
844 #define VOTE_REG_EN6 VOTE_OFS(0x152C)
845 #define VOTE_APB_M_REG0 VOTE_OFS(0x1530)
846 #define VOTE_APB_M_REG5 VOTE_OFS(0x1544)
847 #define VOTE_TIMEOUT0 VOTE_OFS(0x154C)
848 #define VOTE_TIMEOUT1 VOTE_OFS(0x1550)
849 #define VOTE_REG_KEY VOTE_OFS(0x1560)
850 #define VOTE_MTCMOS_MODE_SEL_0 VOTE_OFS(0x1570)
851 #define VOTE_MTCMOS_MODE_SEL_1 VOTE_OFS(0x1574)
852 #define VOTE_MUX_MAPPING_LINK_EN_0 VOTE_OFS(0x1578)
853 #define VOTE_MUX_MAPPING_LINK_EN_1 VOTE_OFS(0x157C)
854 #define VOTE_MUX_MODE_SEL_0 VOTE_OFS(0x1580)
855 #define VOTE_MUX_MODE_SEL_1 VOTE_OFS(0x1584)
856 #define VOTE_MUX_MAPPING_LINK_EN_2 VOTE_OFS(0x1588)
857 #define VOTE_MUX_MODE_SEL_2 VOTE_OFS(0x158C)
858 #define VOTE_MTCMOS_DIS_MUX_0 VOTE_OFS(0x1590)
859 #define VOTE_MTCMOS_DIS_MUX_1 VOTE_OFS(0x1594)
860
861 #define VOTE_LOCK_REG_CFG 0x80000000
862
863 #define VOTE_CG_MAP_MTCMOS(x) VOTE_OFS(0x15A0 + (x) * 0x4)
864 #define VOTE_CG_SET_ADDR(x) VOTE_OFS(0x1600 + (x) * 0x8)
865 #define VOTE_CG_CLR_ADDR(x) VOTE_OFS(0x1604 + (x) * 0x8)
866
867 #define VOTE_CG_MTCMOS_DUMMY_RANGE_START1 0
868 #define VOTE_CG_MTCMOS_DUMMY_RANGE_END1 14
869 #define VOTE_CG_MTCMOS_DUMMY_RANGE_START2 30
870 #define VOTE_CG_MTCMOS_DUMMY_RANGE_END2 49
871
872 #define VOTE_MAP(_id, _base, _set_val, _clr_val)\
873 [_id] = { \
874 .map_base = _base, \
875 .set_addr = _set_val, \
876 .clr_addr = _clr_val, \
877 }
878
879 struct range {
880 u32 start;
881 u32 end;
882 };
883
884 struct vote_map {
885 u32 map_base;
886 u16 set_addr;
887 u16 clr_addr;
888 };
889
890 struct cg_mtcmos_map {
891 u8 cg_idx;
892 u8 mtcmos_idx;
893 };
894
895 static const struct vote_map vote_maps[] = {
896 VOTE_MAP(0, IMP_IIC_WRAP_N_BASE, 0xE04, 0xE08),
897 VOTE_MAP(1, PERICFG_AO_BASE, 0x30, 0x2C),
898 VOTE_MAP(2, SSR_TOP_BASE, 0x0, 0x0),
899 VOTE_MAP(3, CKSYS_BASE, 0x0078, 0x0074),
900 VOTE_MAP(4, CKSYS_BASE, 0x0088, 0x0084),
901 VOTE_MAP(5, CKSYS_BASE, 0x0098, 0x0094),
902 VOTE_MAP(6, CKSYS_BASE, 0x00C8, 0x00C4),
903 VOTE_MAP(7, CKSYS_BASE, 0x0118, 0x0114),
904 VOTE_MAP(8, CKSYS_BASE, 0x0128, 0x0124),
905 VOTE_MAP(9, VLP_CKSYS_BASE, 0x0058, 0x0054),
906 VOTE_MAP(10, VLP_CKSYS_BASE, 0x0068, 0x0064),
907 };
908
909 static const struct range vote_cg_mtcmos_dummy_range[] = {
910 { VOTE_CG_MTCMOS_DUMMY_RANGE_START1, VOTE_CG_MTCMOS_DUMMY_RANGE_END1 },
911 { VOTE_CG_MTCMOS_DUMMY_RANGE_START2, VOTE_CG_MTCMOS_DUMMY_RANGE_END2 },
912 };
913
914 enum {
915 PM_ISP_TRAW,
916 PM_ISP_DIP,
917 PM_ISP_MAIN,
918 PM_ISP_VCORE,
919 PM_ISP_WPE_EIS,
920 PM_ISP_WPE_TNR,
921 PM_ISP_WPE_LITE,
922 PM_VDE0,
923 PM_VDE1,
924 PM_VDE_VCORE0,
925 PM_VEN0,
926 PM_VEN1,
927 PM_VEN2,
928 PM_CAM_MRAW,
929 PM_CAM_RAWA,
930 PM_CAM_RAWB,
931 PM_CAM_RAWC,
932 PM_CAM_RMSA,
933 PM_CAM_RMSB,
934 PM_CAM_RMSC,
935 PM_CAM_MAIN,
936 PM_CAM_VCORE,
937 PM_CAM_CCU,
938 PM_CAM_CCU_AO,
939 PM_DISP_VCORE,
940 PM_DIS0,
941 PM_DIS1,
942 PM_OVL0,
943 PM_OVL1,
944 PM_DISP_EDPTX,
945 PM_DISP_DPTX,
946 PM_MML0,
947 PM_MML1,
948 PM_MMINFRA0,
949 PM_MMINFRA1,
950 PM_MMINFRA_AO,
951 PM_DP_TX,
952 PM_CSI_BS_RX,
953 PM_CSI_LS_RX,
954 PM_DSI_PHY0,
955 PM_DSI_PHY1,
956 PM_DSI_PHY2,
957 PM_DUMMY1 = 63,
958 PM_DUMMY2,
959 };
960
961 enum {
962 CLK_SENINF0_SEL,
963 CLK_SENINF1_SEL,
964 CLK_SENINF2_SEL,
965 CLK_SENINF3_SEL,
966 CLK_SENINF4_SEL,
967 CLK_SENINF5_SEL,
968 CLK_IMG1_SEL,
969 CLK_IPE_SEL,
970 CLK_CAM_SEL,
971 CLK_CAMTM_SEL,
972 CLK_DPE_SEL,
973 CLK_VDEC_SEL,
974 CLK_CCUSYS_SEL,
975 CLK_CCUTM_SEL,
976 CLK_VENC_SEL,
977 CLK_DVO_SEL,
978 CLK_DVO_FAVT_SEL,
979 CLK_DP1_SEL,
980 CLK_DP0_SEL,
981 CLK_DISP_SEL,
982 CLK_MDP_SEL,
983 CLK_MMINFRA_SEL,
984 CLK_MMINFRA_SNOC_SEL,
985 CLK_MMUP_SEL,
986 CLK_MMINFRA_AO_SEL,
987 };
988
989 #define MMVOTE_OFS(ofs) ((void *)(uintptr_t)(MMVOTE_BASE + ofs))
990
991 #define MMVOTE_MTCMOS_MODE_SEL_0 MMVOTE_OFS(0x1570)
992 #define MMVOTE_MTCMOS_DIS_MUX_0 MMVOTE_OFS(0x1590)
993 #define MMVOTE_MTCMOS_DIS_MUX_1 MMVOTE_OFS(0x1594)
994
995 #define MMVOTE_PRE_CLK_MUX(x) MMVOTE_OFS(0x4180 + (x) * 0x4)
996 #define MMVOTE_MTCMOS_MAP_MTCMOS(x) MMVOTE_OFS(0x5484 + (x) * 0x4)
997 #define MMVOTE_MTCMOS_MAP_MUX(t, x) MMVOTE_OFS(0x5108 + (t) * 0xc + (x) * 0x4)
998
999 #define MMVOTE_CTRL MMVOTE_OFS(0x150C)
1000 #define MMVOTE_REG_EN0 MMVOTE_OFS(0x1514)
1001 #define MMVOTE_REG_EN1 MMVOTE_OFS(0x1518)
1002 #define MMVOTE_REG_EN6 MMVOTE_OFS(0x152C)
1003 #define MMVOTE_APB_M_REG0 MMVOTE_OFS(0x1530)
1004 #define MMVOTE_APB_M_REG5 MMVOTE_OFS(0x1544)
1005 #define MMVOTE_TIMEOUT0 MMVOTE_OFS(0x154C)
1006 #define MMVOTE_TIMEOUT1 MMVOTE_OFS(0x1550)
1007 #define MMVOTE_REG_KEY MMVOTE_OFS(0x1560)
1008
1009 #define MMVOTE_UNLOCK_REG_CFG 0x10907
1010
1011 #define MMVOTE_CG_MAP_MTCMOS(x) MMVOTE_OFS(0x15A0 + (x) * 0x4)
1012 #define MMVOTE_CG_SET_ADDR(x) MMVOTE_OFS(0x1600 + (x) * 0x8)
1013 #define MMVOTE_CG_CLR_ADDR(x) MMVOTE_OFS(0x1604 + (x) * 0x8)
1014
1015 #define MMVOTE_CG_MTCMOS_MAP_COUNT 50
1016
1017 #define MMVOTE_CG_MTCMOS_DUMMY_RANGE_START1 0
1018 #define MMVOTE_CG_MTCMOS_DUMMY_RANGE_END1 28
1019 #define MMVOTE_CG_MTCMOS_DUMMY_RANGE_START2 30
1020 #define MMVOTE_CG_MTCMOS_DUMMY_RANGE_END2 49
1021
1022 static const struct vote_map mmvote_maps[] = {
1023 VOTE_MAP(0, MMVOTE_CAM_MAIN_R1A_BASE, 0x8, 0x4),
1024 VOTE_MAP(1, MMVOTE_CAM_MAIN_R1A_BASE, 0xC0, 0xC0),
1025 VOTE_MAP(2, MMVOTE_MMSYS1_CONFIG_BASE, 0x108, 0x104),
1026 VOTE_MAP(3, MMVOTE_MMSYS1_CONFIG_BASE, 0x118, 0x114),
1027 VOTE_MAP(4, MMVOTE_MMSYS_CONFIG_BASE, 0x108, 0x104),
1028 VOTE_MAP(5, MMVOTE_MMSYS_CONFIG_BASE, 0x118, 0x114),
1029 VOTE_MAP(6, MMVOTE_DISP_VDISP_AO_CONFIG_BASE, 0x108, 0x104),
1030 VOTE_MAP(7, MMVOTE_IMGSYS_MAIN_BASE, 0x58, 0x54),
1031 VOTE_MAP(8, MMVOTE_IMGSYS_MAIN_BASE, 0x8, 0x4),
1032 VOTE_MAP(9, MMVOTE_IMG_VCORE_D1A_BASE, 0x8, 0x4),
1033 VOTE_MAP(10, MMVOTE_OVLSYS1_CONFIG_BASE, 0x108, 0x104),
1034 VOTE_MAP(11, MMVOTE_OVLSYS1_CONFIG_BASE, 0x118, 0x114),
1035 VOTE_MAP(12, MMVOTE_OVLSYS_CONFIG_BASE, 0x108, 0x104),
1036 VOTE_MAP(13, MMVOTE_OVLSYS_CONFIG_BASE, 0x118, 0x114),
1037 VOTE_MAP(14, MMVOTE_CCU_MAIN_BASE, 0x8, 0x4),
1038 VOTE_MAP(15, MMVOTE_VDEC_GCON_BASE, 0x8, 0xC),
1039 VOTE_MAP(16, MMVOTE_VDEC_GCON_BASE, 0x200, 0x204),
1040 VOTE_MAP(17, MMVOTE_VDEC_GCON_BASE, 0x0, 0x4),
1041 VOTE_MAP(18, MMVOTE_VDEC_SOC_GCON_BASE, 0x8, 0xC),
1042 VOTE_MAP(19, MMVOTE_VDEC_SOC_GCON_BASE, 0x200, 0x204),
1043 VOTE_MAP(20, MMVOTE_VDEC_SOC_GCON_BASE, 0x0, 0x4),
1044 VOTE_MAP(21, MMVOTE_VDEC_SOC_GCON_BASE, 0x1EC, 0x1EC),
1045 VOTE_MAP(22, MMVOTE_VDEC_SOC_GCON_BASE, 0x1E0, 0x1E0),
1046 VOTE_MAP(23, MMVOTE_VENC_GCON_BASE, 0x4, 0x8),
1047 VOTE_MAP(24, MMVOTE_VENC_GCON_BASE, 0x14, 0x10),
1048 VOTE_MAP(25, MMVOTE_VENC_GCON_CORE1_BASE, 0x4, 0x8),
1049 VOTE_MAP(26, MMVOTE_VENC_GCON_CORE1_BASE, 0x14, 0x10),
1050 VOTE_MAP(27, MMVOTE_VENC_GCON_CORE2_BASE, 0x4, 0x8),
1051 VOTE_MAP(28, MMVOTE_VENC_GCON_CORE2_BASE, 0x14, 0x10),
1052 VOTE_MAP(30, CKSYS_GP2_BASE, 0x0028, 0x0024),
1053 VOTE_MAP(31, CKSYS_GP2_BASE, 0x0038, 0x0034),
1054 VOTE_MAP(32, CKSYS_GP2_BASE, 0x0048, 0x0044),
1055 VOTE_MAP(33, CKSYS_GP2_BASE, 0x0058, 0x0054),
1056 VOTE_MAP(34, CKSYS_GP2_BASE, 0x0068, 0x0064),
1057 VOTE_MAP(35, CKSYS_GP2_BASE, 0x0078, 0x0074),
1058 };
1059
1060 static const struct range mmvote_cg_mtcmos_dummy_range[] = {
1061 { MMVOTE_CG_MTCMOS_DUMMY_RANGE_START1, MMVOTE_CG_MTCMOS_DUMMY_RANGE_END1 },
1062 { MMVOTE_CG_MTCMOS_DUMMY_RANGE_START2, MMVOTE_CG_MTCMOS_DUMMY_RANGE_END2 },
1063 };
1064
1065 static const struct range mmvote_mtcmos_mtcmos_dummy_range[] = {
1066 { PM_ISP_TRAW, PM_DSI_PHY2 },
1067 { PM_DUMMY1, PM_DUMMY2 },
1068 };
1069
1070 #define CG_VDEC_SOC_GCON_1 19
1071
1072 static const struct cg_mtcmos_map mmvote_cg_mtcmos_table[] = {
1073 { CG_VDEC_SOC_GCON_1, PM_VDE_VCORE0 },
1074 { CG_VDEC_SOC_GCON_1, PM_VDE0 },
1075 };
1076
1077 struct mtcmos_mux_map {
1078 u8 mtcmos_idx;
1079 u8 mux_idx;
1080 };
1081
1082 static const struct mtcmos_mux_map mmvote_mtcmos_mux_table[] = {
1083 { PM_ISP_TRAW, CLK_IMG1_SEL },
1084 { PM_ISP_DIP, CLK_IMG1_SEL },
1085 { PM_ISP_MAIN, CLK_IMG1_SEL },
1086 { PM_ISP_MAIN, CLK_IPE_SEL },
1087 { PM_ISP_VCORE, CLK_IMG1_SEL },
1088 { PM_ISP_VCORE, CLK_IPE_SEL },
1089 { PM_ISP_WPE_EIS, CLK_IMG1_SEL },
1090 { PM_ISP_WPE_TNR, CLK_IMG1_SEL },
1091 { PM_ISP_WPE_LITE, CLK_IMG1_SEL },
1092 { PM_VDE0, CLK_VDEC_SEL },
1093 { PM_VDE1, CLK_VDEC_SEL },
1094 { PM_VDE_VCORE0, CLK_VDEC_SEL },
1095 { PM_VEN0, CLK_VENC_SEL },
1096 { PM_VEN1, CLK_VENC_SEL },
1097 { PM_VEN2, CLK_VENC_SEL },
1098 { PM_CAM_MRAW, CLK_DPE_SEL },
1099 { PM_CAM_RAWA, CLK_CAM_SEL },
1100 { PM_CAM_RAWB, CLK_CAM_SEL },
1101 { PM_CAM_RAWC, CLK_CAM_SEL },
1102 { PM_CAM_RMSA, CLK_CAM_SEL },
1103 { PM_CAM_RMSB, CLK_CAM_SEL },
1104 { PM_CAM_RMSC, CLK_CAM_SEL },
1105 { PM_CAM_MAIN, CLK_CAM_SEL },
1106 { PM_CAM_VCORE, CLK_CAM_SEL },
1107 { PM_CAM_VCORE, CLK_CAMTM_SEL },
1108 { PM_CAM_VCORE, CLK_CCUSYS_SEL },
1109 { PM_CAM_CCU, CLK_CCUSYS_SEL },
1110 { PM_CAM_CCU, CLK_CCUTM_SEL },
1111 { PM_CAM_CCU_AO, CLK_CCUSYS_SEL },
1112 { PM_DISP_VCORE, CLK_DISP_SEL },
1113 { PM_DIS0, CLK_DISP_SEL },
1114 { PM_DIS1, CLK_DISP_SEL },
1115 { PM_OVL0, CLK_DISP_SEL },
1116 { PM_OVL1, CLK_DISP_SEL },
1117 { PM_DISP_EDPTX, CLK_DISP_SEL },
1118 { PM_DISP_DPTX, CLK_DISP_SEL },
1119 { PM_MML0, CLK_MDP_SEL },
1120 { PM_MML1, CLK_MDP_SEL },
1121 { PM_MMINFRA0, CLK_MMINFRA_SEL },
1122 { PM_MMINFRA0, CLK_MMINFRA_SNOC_SEL },
1123 { PM_MMINFRA1, CLK_MMINFRA_SEL },
1124 { PM_MMINFRA1, CLK_MMINFRA_SNOC_SEL },
1125 { PM_MMINFRA_AO, CLK_MMINFRA_AO_SEL },
1126 { PM_CSI_BS_RX, CLK_SENINF2_SEL },
1127 { PM_CSI_BS_RX, CLK_SENINF3_SEL },
1128 { PM_CSI_BS_RX, CLK_SENINF4_SEL },
1129 { PM_CSI_BS_RX, CLK_SENINF5_SEL },
1130 { PM_CSI_LS_RX, CLK_SENINF0_SEL },
1131 { PM_CSI_LS_RX, CLK_SENINF1_SEL },
1132 };
1133
1134 #define CG_MTCMOS_FILED_WIDTH 7
1135 #define CG_MTCMOS_FIELD_COUNT 4
1136 #define CG_MTCMOS_FIELD_MASK GENMASK(6, 0)
1137
1138 #define MTCMOS_MTCMOS_FILED_WIDTH 8
1139 #define MTCMOS_MTCMOS_FIELD_COUNT 4
1140 #define MTCMOS_MTCMOS_FIELD_MASK GENMASK(7, 0)
1141 #define MTCMOS_LEVEL_SHIFT 6
1142
1143 static void vote_init(void)
1144 {
1145 u32 group;
1146 u32 offset;
1147 void *addr;
1148 u32 start, end;
1149
1150 /* Vote map */
1151 for (int i = 0; i < ARRAY_SIZE(vote_maps); i++) {
1152 if (!vote_maps[i].map_base)
1153 continue;
1154
1155 write32(VOTE_CG_SET_ADDR(i), vote_maps[i].map_base + vote_maps[i].set_addr);
1156 write32(VOTE_CG_CLR_ADDR(i), vote_maps[i].map_base + vote_maps[i].clr_addr);
1157 }
1158
1159 /* VOTE_REG_EN0 0x1514 = 0x89FF8001 */
1160 write32(VOTE_REG_EN0, 0x89FF8001);
1161
1162 /* VOTE_REG_EN1 0x1518 = 0x1FF */
1163 write32(VOTE_REG_EN1, 0x1FF);
1164
1165 /* VOTE_REG_EN6 0x152C = 0x1400 */
1166 write32(VOTE_REG_EN6, BIT(12) | BIT(10));
1167
1168 /* VOTE_DCM 0x1510 = 0x1E7 */
1169 write32(VOTE_DCM, 0x1E7);
1170
1171 /* VOTE_APB_M_REG0 0x1530 = 0x6 */
1172 write32(VOTE_APB_M_REG0, 0x6);
1173
1174 /* VOTE_CTRL 0x150C = 0x80000001 */
1175 write32(VOTE_CTRL, BIT(31) | BIT(0));
1176
1177 /* Disable Timeout:0x0 */
1178 write32(VOTE_TIMEOUT0, 0);
1179 write32(VOTE_TIMEOUT1, 0);
1180
1181 /* VOTE_APB_M_REG0 0x1530[25:24] = 0x3 */
1182 setbits32(VOTE_APB_M_REG0, BIT(25) | BIT(24));
1183
1184 /* CG map MTCMOS */
1185 for (int i = 0; i < ARRAY_SIZE(mmvote_cg_mtcmos_dummy_range); i++) {
1186 start = vote_cg_mtcmos_dummy_range[i].start;
1187 end = vote_cg_mtcmos_dummy_range[i].end;
1188
1189 for (int cg_idx = start; cg_idx <= end; cg_idx++) {
1190 group = cg_idx / CG_MTCMOS_FIELD_COUNT;
1191 offset = cg_idx % CG_MTCMOS_FIELD_COUNT;
1192 offset *= CG_MTCMOS_FILED_WIDTH;
1193 addr = VOTE_CG_MAP_MTCMOS(group);
1194
1195 clrsetbits32(addr, CG_MTCMOS_FIELD_MASK << offset, PM_DUMMY << offset);
1196 }
1197 }
1198
1199 /* Link setup */
1200 write32(VOTE_MTCMOS_MODE_SEL_0, 0);
1201 write32(VOTE_MTCMOS_MODE_SEL_1, 0);
1202 write32(VOTE_MUX_MAPPING_LINK_EN_0, 0);
1203 write32(VOTE_MUX_MAPPING_LINK_EN_1, 0);
1204 write32(VOTE_MUX_MODE_SEL_0, 0);
1205 write32(VOTE_MUX_MODE_SEL_1, 0);
1206 write32(VOTE_MUX_MAPPING_LINK_EN_2, 0);
1207 write32(VOTE_MUX_MODE_SEL_2, 0);
1208 write32(VOTE_MTCMOS_DIS_MUX_0, 0xFFFFFFFF);
1209 write32(VOTE_MTCMOS_DIS_MUX_1, 0xFFFFFFFF);
1210
1211 /* Lock donmain */
1212 write32(VOTE_REG_KEY, VOTE_LOCK_REG_CFG);
1213
1214 /* Vote enable */
1215 write32(VOTE_APB_M_REG5, BIT(0));
1216 }
1217
1218 static void mmvote_init(void)
1219 {
1220 u32 group;
1221 u32 offset;
1222 u32 level_offset;
1223 void *addr;
1224 u32 start, end;
1225
1226 /* Vote setup */
1227 for (int i = 0; i < ARRAY_SIZE(mmvote_maps); i++) {
1228 if (!mmvote_maps[i].map_base)
1229 continue;
1230
1231 write32(MMVOTE_CG_SET_ADDR(i),
1232 mmvote_maps[i].map_base + mmvote_maps[i].set_addr);
1233 write32(MMVOTE_CG_CLR_ADDR(i),
1234 mmvote_maps[i].map_base + mmvote_maps[i].clr_addr);
1235
1236 }
1237
1238 /* MMVOTE_REG_EN0 0x1514 = 0xBDFF8001 */
1239 write32(MMVOTE_REG_EN0, 0xBDFF8001);
1240
1241 /* MMVOTE_REG_EN1 0x1518 = 0x1CB */
1242 write32(MMVOTE_REG_EN1, 0x1CB);
1243
1244 /* MMVOTE_REG_EN6 0x152C = 0x1400 */
1245 write32(MMVOTE_REG_EN6, BIT(12) | BIT(10));
1246
1247 /* MMVOTE_APB_M_REG0 0x1530 = 0x7 */
1248 write32(MMVOTE_APB_M_REG0, BIT(2) | BIT(1) | BIT(0));
1249
1250 /* MMVOTE_CTRL 0x150C = 0x80000001 */
1251 write32(MMVOTE_CTRL, BIT(31) | BIT(0));
1252
1253 /* Disable Timeout: 0x0 */
1254 write32(MMVOTE_TIMEOUT0, 0);
1255 write32(MMVOTE_TIMEOUT1, 0);
1256
1257 /* MMVOTE_APB_M_REG0 0x1530[25:24] = 0x3 */
1258 setbits32(MMVOTE_APB_M_REG0, BIT(25) | BIT(24));
1259
1260 /* CG map MTCMOS */
1261 for (int i = 0; i < ARRAY_SIZE(mmvote_cg_mtcmos_dummy_range); i++) {
1262 start = mmvote_cg_mtcmos_dummy_range[i].start;
1263 end = mmvote_cg_mtcmos_dummy_range[i].end;
1264
1265 for (int cg_idx = start; cg_idx <= end; cg_idx++) {
1266 group = cg_idx / CG_MTCMOS_FIELD_COUNT;
1267 offset = cg_idx % CG_MTCMOS_FIELD_COUNT;
1268 offset *= CG_MTCMOS_FILED_WIDTH;
1269 addr = MMVOTE_CG_MAP_MTCMOS(group);
1270
1271 clrsetbits32(addr, CG_MTCMOS_FIELD_MASK << offset, PM_DUMMY1 << offset);
1272 }
1273 }
1274
1275 for (int i = 0; i < ARRAY_SIZE(mmvote_cg_mtcmos_table); i++) {
1276 group = mmvote_cg_mtcmos_table[i].cg_idx / CG_MTCMOS_FIELD_COUNT;
1277 offset = mmvote_cg_mtcmos_table[i].cg_idx % CG_MTCMOS_FIELD_COUNT;
1278 offset *= CG_MTCMOS_FILED_WIDTH;
1279 addr = MMVOTE_CG_MAP_MTCMOS(group);
1280
1281 clrsetbits32(addr,
1282 CG_MTCMOS_FIELD_MASK << offset,
1283 mmvote_cg_mtcmos_table[i].mtcmos_idx << offset);
1284 }
1285
1286 /* MTCMOS map MTCMOS */
1287 for (int i = 0; i < ARRAY_SIZE(mmvote_mtcmos_mtcmos_dummy_range); i++) {
1288 start = mmvote_mtcmos_mtcmos_dummy_range[i].start;
1289 end = mmvote_mtcmos_mtcmos_dummy_range[i].end;
1290
1291 for (int mtcmos_idx = start; mtcmos_idx <= end; mtcmos_idx++) {
1292 group = mtcmos_idx / MTCMOS_MTCMOS_FIELD_COUNT;
1293 offset = mtcmos_idx % MTCMOS_MTCMOS_FIELD_COUNT;
1294 offset *= MTCMOS_MTCMOS_FILED_WIDTH;
1295 level_offset = offset + MTCMOS_LEVEL_SHIFT;
1296 addr = MMVOTE_MTCMOS_MAP_MTCMOS(group);
1297
1298 clrsetbits32(addr, MTCMOS_MTCMOS_FIELD_MASK << offset,
1299 mtcmos_idx << offset | 3 << level_offset);
1300 }
1301 }
1302
1303 /* MTCMOS map MUX */
1304 for (int i = 0; i < ARRAY_SIZE(mmvote_mtcmos_mux_table); i++) {
1305 group = mmvote_mtcmos_mux_table[i].mux_idx / 32;
1306 addr = MMVOTE_MTCMOS_MAP_MUX(mmvote_mtcmos_mux_table[i].mtcmos_idx, group);
1307
1308 setbits32(addr, BIT(mmvote_mtcmos_mux_table[i].mux_idx % 32));
1309 }
1310 write32(MMVOTE_PRE_CLK_MUX(0), 0x1785FC0);
1311 write32(MMVOTE_PRE_CLK_MUX(1), 0);
1312
1313 /* Link Setup */
1314 write32(MMVOTE_MTCMOS_DIS_MUX_0, 0x0);
1315 write32(MMVOTE_MTCMOS_DIS_MUX_1, 0x3E0);
1316 write32(MMVOTE_MTCMOS_MODE_SEL_0, 0xFFBFFFFF);
1317
1318 /* Lock domain */
1319 write32(MMVOTE_REG_KEY, MMVOTE_UNLOCK_REG_CFG);
1320
1321 /* mmvote enable */
1322 write32(MMVOTE_APB_M_REG5, BIT(0));
1323 }
1324
1325 static u32 mt_get_subsys_freq(const struct fmeter_data *fm_data, u32 id)
1326 {
1327 u32 freq, output;
1328 u32 clk_div = 1, post_div = 1;
1329 bool ckdiv_en = false;
1330
1331 if (fm_data->pll_con0 != NULL) {
1332 ckdiv_en = !!(read32(fm_data->pll_con0) & BIT(16));
1333 setbits32(fm_data->pll_con0, BIT(16) | BIT(12));
1334 }
1335
1336 if (fm_data->id == MFGPLL_CTRL || fm_data->id == MFGPLL_SC0_CTRL ||
1337 fm_data->id == MFGPLL_SC1_CTRL)
1338 setbits32(fm_data->pll_con5, BIT(4));
1339
1340 write32(fm_data->con0, 0);
1341 setbits32(fm_data->con0, BIT(15));
1342
1343 if (fm_data->id == VLP_CKSYS_CTRL)
1344 clrsetbits32(fm_data->con0, GENMASK(20, 16), id << 16);
1345 else
1346 clrsetbits32(fm_data->con0, GENMASK(2, 0), id);
1347
1348 clrsetbits32(fm_data->con1, GENMASK(31, 16), 0x1FF << 16);
1349
1350 clrbits32(fm_data->con0, GENMASK(31, 24));
1351
1352 setbits32(fm_data->con0, BIT(12));
1353 setbits32(fm_data->con0, BIT(4));
1354 clrbits32(fm_data->con0, BIT(1) | BIT(0));
1355
1356 /* wait frequency meter finish */
1357 if (fm_data->id == VLP_CKSYS_CTRL) {
1358 udelay(VLP_FM_WAIT_TIME_MS);
1359 } else if (!wait_us(1000, !(read32(fm_data->con0) & BIT(4)))) {
1360 printk(BIOS_ERR, "mtcmos_vote disable timeout\n");
1361 return 0;
1362 }
1363
1364 output = read32(fm_data->con1) & 0xFFFF;
1365 freq = output * 26000 / 512;
1366
1367 if (fm_data->pll_con0 != NULL && fm_data->id != VLP_CKSYS_CTRL && id == FM_PLL_CKDIV_CK)
1368 clk_div = (read32(fm_data->pll_con0) & GENMASK(10, 7)) >> 7;
1369
1370 if (clk_div == 0)
1371 clk_div = 1;
1372
1373 if (fm_data->pll_con1 != NULL && fm_data->id != VLP_CKSYS_CTRL && id == FM_PLL_CKDIV_CK)
1374 post_div = BIT((read32(fm_data->pll_con1) & GENMASK(26, 24)) >> 24);
1375
1376 freq = freq * clk_div / post_div;
1377
1378 if (fm_data->pll_con0 != NULL) {
1379 if (ckdiv_en)
1380 clrbits32(fm_data->pll_con0, BIT(12));
1381 else
1382 clrbits32(fm_data->pll_con0, BIT(16) | BIT(12));
1383 }
1384
1385 if (fm_data->id == MFGPLL_CTRL || fm_data->id == MFGPLL_SC0_CTRL ||
1386 fm_data->id == MFGPLL_SC1_CTRL)
1387 clrbits32(fm_data->pll_con5, BIT(4));
1388
1389 write32(fm_data->con0, 0x8000);
1390
1391 printk(BIOS_INFO, "meter[%d:%d] = %d Khz(output: %d, clk_div: %d, post_div: %d)\n",
1392 fm_data->id, id, freq, output, clk_div, post_div);
1393
1394 return freq;
1395 }
1396
1397 u32 mt_get_vlpck_freq(u32 id)
1398 {
1399 return mt_get_subsys_freq(&fmd[VLP_CKSYS_CTRL], id);
1400 }
1401
1402 static inline u32 mt_get_cpu_freq(u32 id)
1403 {
1404 return mt_get_subsys_freq(&fmd[id], FM_PLL_CKDIV_CK);
1405 }
1406
1407 static inline u32 mt_get_gpu_freq(u32 id)
1408 {
1409 return mt_get_subsys_freq(&fmd[id], FM_PLL_CK);
1410 }
1411
1412 static void mt_dump_cpu_freq(void)
1413 {
1414 mt_get_cpu_freq(ARMPLL_B_CTRL);
1415 mt_get_cpu_freq(ARMPLL_BL_CTRL);
1416 mt_get_cpu_freq(ARMPLL_LL_CTRL);
1417 mt_get_cpu_freq(CCIPLL_CTRL);
1418 mt_get_cpu_freq(PTPPLL_CTRL);
1419 }
1420
1421 static void mt_dump_gpu_freq(void)
1422 {
1423 mt_get_gpu_freq(MFGPLL_CTRL);
1424 mt_get_gpu_freq(MFGPLL_SC0_CTRL);
1425 mt_get_gpu_freq(MFGPLL_SC1_CTRL);
1426 }
1427
1428 void pll_set_pcw_change(const struct pll *pll)
1429 {
1430 setbits32(pll->div_reg, PLL_PCW_CHG);
1431 }
1432
1433 void mt_pll_init(void)
1434 {
1435 int i;
1436
1437 write32(&mtk_apmixed->ref_clk_req_protected_con, 0);
1438 write32(&mtk_apmixed2->gp2_ref_clk_req_protected_con, 0);
1439 write32(&mtk_vlpsys->vlp_ref_clk_req_protected_con, 0);
1440
1441 /* Set xPLL frequency */
1442 for (i = 0; i < ARRAY_SIZE(pll_rates); i++)
1443 pll_set_rate(&plls[pll_rates[i].id], pll_rates[i].rate);
1444
1445 setbits32(&mtk_apmixed->univpll_con[0], BIT(17));
1446 setbits32(&mtk_apmixed2->univpll2_con[0], BIT(17));
1447
1448 setbits32(&mtk_vlpsys->vlp_ap_pll_con3, BIT(5) | BIT(0));
1449
1450 clrbits32(&mtk_mcusys->cpu_src_clk_config, BIT(0));
1451 clrbits32(&mtk_mcusys->dsu_pcsm_clk_src_config, BIT(0));
1452 clrbits32(&mtk_mcusys->infra_clk_src_config, BIT(0));
1453
1454 /* [1]: clk_en = 0 */
1455 clrbits32(&mtk_mcusys->cpu_src_clk_config, BIT(1));
1456 clrbits32(&mtk_mcusys->dsu_pcsm_clk_src_config, BIT(1));
1457 clrbits32(&mtk_mcusys->infra_clk_src_config, BIT(1));
1458 clrbits32(&mtk_mcusys->ses_clk_free_ck_en, BIT(1));
1459
1460 /* MCUSYS PLL set frequency */
1461 for (i = 0; i < ARRAY_SIZE(mcusys_pll_rates); i++)
1462 pll_set_rate(&mcusys_plls[mcusys_pll_rates[i].id], mcusys_pll_rates[i].rate);
1463
1464 /* PLL all enable */
1465 write32(&mtk_apmixed->pllen_all_set, 0xF);
1466 write32(&mtk_apmixed2->gp2_pllen_all_set, 0x7F);
1467 write32(&mtk_vlpsys->vlp_pllen_apll_set, 0x3);
1468
1469 setbits32(&mtk_ccipll->pll_con[0], BIT(0));
1470 setbits32(&mtk_armpll_ll->pll_con[0], BIT(0));
1471 setbits32(&mtk_armpll_bl->pll_con[0], BIT(0));
1472 setbits32(&mtk_armpll_b->pll_con[0], BIT(0));
1473 setbits32(&mtk_ptppll->pll_con[0], BIT(0));
1474
1475 setbits32(&mtk_spm_mtcmos->spm2gpupm_con, BIT(4));
1476
1477 /* Set MFGPLLs Frequency */
1478 for (i = 0; i < ARRAY_SIZE(mfg_pll_rates); i++)
1479 pll_set_rate(&mfg_plls[mfg_pll_rates[i].id], mfg_pll_rates[i].rate);
1480
1481 setbits32(&mtk_mfgpll->pll_con[0], BIT(0));
1482 setbits32(&mtk_mfgpll_sc0->pll_con[0], BIT(0));
1483 setbits32(&mtk_mfgpll_sc1->pll_con[0], BIT(0));
1484
1485 /* Wait PLL stable (20us) */
1486 udelay(PLL_EN_DELAY);
1487
1488 setbits32(&mtk_mcusys->ses_clk_free_ck_en, BIT(1));
1489 setbits32(&mtk_mcusys->cpu_src_clk_config, BIT(2) | BIT(1) | BIT(0));
1490 setbits32(&mtk_mcusys->dsu_pcsm_clk_src_config, BIT(2) | BIT(1) | BIT(0));
1491 setbits32(&mtk_mcusys->infra_clk_src_config, BIT(2) | BIT(1) | BIT(0));
1492
1493 /* pll all rstb */
1494 write32(&mtk_apmixed->pll_div_rstb_all_set, 0x3);
1495 write32(&mtk_apmixed2->gp2_pll_div_rstb_all_set, 0xF);
1496
1497 setbits32(&mtk_apmixed->mainpll_con[0], 0xFF000000);
1498 setbits32(&mtk_apmixed->univpll_con[0], 0xFF000000);
1499
1500 clrsetbits32(&mtk_mcusys->cpu_plldiv0_cfg, GENMASK(10, 8), 0x100);
1501 clrsetbits32(&mtk_mcusys->cpu_plldiv1_cfg, GENMASK(10, 8), 0x100);
1502 clrsetbits32(&mtk_mcusys->cpu_plldiv2_cfg, GENMASK(10, 8), 0x100);
1503 clrsetbits32(&mtk_mcusys->bus_plldiv_cfg, GENMASK(10, 8), 0x100);
1504
1505 /* [10]: toggle mux update */
1506 setbits32(&mtk_mcusys->cpu_plldiv0_cfg, BIT(10));
1507 setbits32(&mtk_mcusys->cpu_plldiv1_cfg, BIT(10));
1508 setbits32(&mtk_mcusys->cpu_plldiv2_cfg, BIT(10));
1509 setbits32(&mtk_mcusys->bus_plldiv_cfg, BIT(10));
1510
1511 clrbits32(&mtk_apinfra_io_ctrl->clk_io_intx_bus_ctrl, BIT(4) | BIT(2));
1512
1513 clrbits32(&mtk_apinfra_io_noc->clk_io_noc_ctrl, BIT(4) | BIT(2));
1514
1515 /* free run */
1516 clrbits32(&mtk_apinfra_mem_ctrl->vdnr_dcm_mem_intx_bus_ctrl, GENMASK(4, 2));
1517 clrbits32(&mtk_apinfra_mem_ctrl->clk_mem_intx_bus_ctrl[0], BIT(7) | BIT(4));
1518 clrbits32(&mtk_apinfra_mem_ctrl->clk_mem_intx_bus_ctrl[1], BIT(21));
1519 clrbits32(&mtk_apinfra_mem_ctrl->clk_mem_intx_bus_ctrl[2], BIT(22));
1520 clrbits32(&mtk_apinfra_mem_ctrl->clk_mem_intx_bus_ctrl[3], BIT(20));
1521 clrbits32(&mtk_apinfra_mem_ctrl->clk_mem_intx_bus_ctrl[4], BIT(24));
1522 clrbits32(&mtk_apinfra_mem_ctrl->clk_mem_intx_bus_ctrl[5], BIT(23));
1523 clrbits32(&mtk_apinfra_mem_noc->vdnr_mem_intf_par_bus_ctrl, BIT(4) | BIT(2));
1524
1525 /* BUS idle to cksys protect release */
1526 write32(&mtk_topckgen->clk_prot_idle_reg, 0xFFFFFFFF);
1527 write32(&mtk_topckgen2->cksys2_clk_prot_idle_reg, 0xFFFFFFFF);
1528 write32(&mtk_vlpsys->vlp_clk_prot_idle_reg, 0xFFFFFFFF);
1529
1530 setbits32(&mtk_peri->vdnr_dcm_top_peri_par_bus_u_peri_par_bus_ctrl,
1531 BIT(14) | BIT(11) | BIT(8) | BIT(5));
1532
1533 setbits32(&mtk_usb->vdnr_dcm_top_usb_bus_u_usb_bus_ctrl, BIT(10) | BIT(7) | BIT(4));
1534
1535 write32(&mtk_topckgen->clk_cfg[0].clr, 0x7);
1536 write32(&mtk_topckgen->clk_cfg[0].set, 0x5);
1537 write32(&mtk_topckgen->clk_cfg_update[0], 0x1);
1538
1539 for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
1540 pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
1541
1542 write32(&mtk_topckgen->clk_cfg_update[0], 0x7FFFFFFF);
1543 write32(&mtk_topckgen->clk_cfg_update[1], 0x7FFFFFFF);
1544 write32(&mtk_topckgen->clk_cfg_update[2], 0x7FFF);
1545
1546 for (i = 0; i < ARRAY_SIZE(cksys2_mux_sels); i++)
1547 pll_mux_set_sel(&cksys2_muxes[cksys2_mux_sels[i].id], cksys2_mux_sels[i].sel);
1548
1549 write32(&mtk_topckgen2->cksys2_clk_cfg_update, 0x7FFFFFF);
1550
1551 for (i = 0; i < ARRAY_SIZE(vlp_mux_sels); i++)
1552 pll_mux_set_sel(&vlp_muxes[vlp_mux_sels[i].id], vlp_mux_sels[i].sel);
1553
1554 write32(&mtk_vlpsys->vlp_clk_cfg_update[0], 0x7FFFFFFF);
1555 write32(&mtk_vlpsys->vlp_clk_cfg_update[1], 0x3FFF);
1556
1557 mt_dump_cpu_freq();
1558 mt_dump_gpu_freq();
1559
1560 write32(&mtk_apifrbus->apifrbus_ao_mem_reg_module_cg.clr, 0x10);
1561
1562 write32(&mtk_pericfg->pericfg_ao_peri_cg_0_set, 0x40000);
1563 write32(&mtk_pericfg->pericfg_ao_peri_cg_1_clr, 0x01FFFA44);
1564 write32(&mtk_pericfg->pericfg_ao_peri_cg_1_set, 0x00000002);
1565 write32(&mtk_pericfg->pericfg_ao_peri_cg_2_clr, 0x1C0000);
1566
1567 setbits32(&mtk_ssr->ssr_top_ssr_top_clk_cfg[0], BIT(24) | BIT(16) | BIT(8) | BIT(0));
1568 setbits32(&mtk_ssr->ssr_top_ssr_top_clk_cfg[1], BIT(24));
1569 }
1570
1571 void mt_pll_set_tvd_pll1_freq(u32 freq)
1572 {
1573 const struct pll *pll = &plls[CLK_APMIXED2_TVDPLL3];
1574
1575 clrbits32(pll->reg, MT8196_PLL_EN);
1576 pll_set_rate(pll, freq);
1577 setbits32(pll->reg, MT8196_PLL_EN);
1578
1579 udelay(PLL_EN_DELAY);
1580 }
1581
1582 void mt_pll_edp_mux_set_sel(u32 sel)
1583 {
1584 pll_mux_set_sel(&cksys2_muxes[CLK_CK2_DVO_SEL], sel);
1585 }
1586
1587 void mt_pll_post_init(void)
1588 {
1589 /* fenc setup */
1590 write32(&mtk_topckgen->clk_prot_idle_all_reg[0], 0);
1591 write32(&mtk_topckgen->clk_prot_idle_all_reg[1], 0);
1592 write32(&mtk_topckgen->clk_prot_idle_all_reg[2], 0);
1593 write32(&mtk_topckgen->clk_prot_idle_all_inv_reg[0], 0);
1594 write32(&mtk_topckgen->clk_prot_idle_all_inv_reg[1], 0);
1595 write32(&mtk_topckgen->clk_prot_idle_all_inv_reg[2], 0);
1596 write32(&mtk_topckgen->clk_prot_vote_ck_en_reg[0], 0xFFFFFFFF);
1597 write32(&mtk_topckgen->clk_prot_vote_ck_en_reg[1], 0xFFFFFFFF);
1598 write32(&mtk_topckgen->clk_prot_vote_ck_en_reg[2], 0xFFFFFFFF);
1599 write32(&mtk_topckgen->clk_prot_spm_ck_en_reg, 0xFFFFFFFF);
1600 write32(&mtk_topckgen2->cksys2_clk_prot_idle_all_reg, 0);
1601 write32(&mtk_topckgen2->cksys2_clk_prot_idle_all_inv_reg, 0);
1602 write32(&mtk_topckgen2->cksys2_clk_prot_vote_ck_en_reg, 0xFFFFFFFF);
1603 write32(&mtk_topckgen2->cksys2_clk_prot_spm_ck_en_reg, 0xFFFFFFFF);
1604 write32(&mtk_vlpsys->vlp_clk_prot_idle_all_reg[0], 0);
1605 write32(&mtk_vlpsys->vlp_clk_prot_idle_all_reg[1], 0);
1606 write32(&mtk_vlpsys->vlp_clk_prot_idle_all_inv_reg[0], 0);
1607 write32(&mtk_vlpsys->vlp_clk_prot_idle_all_inv_reg[1], 0);
1608 write32(&mtk_apmixed->fenc_protected_con, 0xFFFFFFFF);
1609 write32(&mtk_apmixed2->gp2_fenc_protected_con, 0xFFF7FFFF);
1610 write32(&mtk_vlpsys->vlp_fenc_protected_con, 0xFFFFFFFF);
1611 write32(&mtk_apmixed->child_enable_mask_con, 0xFFFFFFFF);
1612 write32(&mtk_apmixed2->gp2_child_enable_mask_con, 0xFFFFFFFF);
1613 write32(&mtk_vlpsys->vlp_child_enable_mask_con, 0xFFFFFFFF);
1614 write32(&mtk_topckgen->clk_fenc_bypass_reg[0], 0);
1615 write32(&mtk_topckgen->clk_fenc_bypass_reg[1], 0);
1616 write32(&mtk_topckgen->clk_fenc_bypass_reg[2], 0);
1617 write32(&mtk_topckgen2->cksys2_clk_fenc_bypass_reg, 0);
1618 write32(&mtk_vlpsys->vlp_clk_fenc_bypass_reg[0], 0);
1619 write32(&mtk_vlpsys->vlp_clk_fenc_bypass_reg[1], 0);
1620 write32(&mtk_apmixed->fenc_bypass_con, 0);
1621 write32(&mtk_apmixed2->gp2_fenc_bypass_con, 0);
1622 write32(&mtk_vlpsys->vlp_fenc_bypass_con, 0);
1623 write32(&mtk_apmixed->pllen_all_clr, 0xFFFFFFFF);
1624 write32(&mtk_apmixed2->gp2_pllen_all_clr, 0xFFFFFFFF);
1625 write32(&mtk_vlpsys->vlp_pllen_apll_clr, 0x3);
1626
1627 /* power down unused mux */
1628 write32(&mtk_topckgen->clk_cfg[3].set, 0x8080);
1629 write32(&mtk_topckgen->clk_cfg[4].set, 0x80800000);
1630 write32(&mtk_topckgen->clk_cfg[6].set, 0x8000);
1631 write32(&mtk_topckgen->clk_cfg[9].set, 0x8080);
1632 write32(&mtk_topckgen->clk_cfg[12].set, 0x80800000);
1633 write32(&mtk_topckgen->clk_cfg[15].set, 0x8000);
1634 write32(&mtk_topckgen->clk_cfg[16].set, 0x800000);
1635 write32(&mtk_topckgen->clk_cfg[18].set, 0x80000000);
1636 write32(&mtk_topckgen->clk_cfg[19].set, 0x80808000);
1637 write32(&mtk_topckgen->clk_cfg[20].set, 0x80808080);
1638 write32(&mtk_topckgen->clk_cfg[21].set, 0x80808080);
1639 write32(&mtk_topckgen->clk_cfg[22].set, 0x80);
1640
1641 write32(&mtk_vlpsys->vlp_clk_cfg[6].set, 0x80);
1642 write32(&mtk_vlpsys->vlp_clk_cfg[10].set, 0x80800000);
1643 write32(&mtk_vlpsys->vlp_clk_cfg[11].set, 0x80);
1644
1645 write32(&mtk_topckgen2->cksys2_clk_cfg[0].set, 0x80808080);
1646 write32(&mtk_topckgen2->cksys2_clk_cfg[1].set, 0x80808080);
1647 write32(&mtk_topckgen2->cksys2_clk_cfg[2].set, 0x80808080);
1648 write32(&mtk_topckgen2->cksys2_clk_cfg[3].set, 0x80808080);
1649 write32(&mtk_topckgen2->cksys2_clk_cfg[4].set, 0x80808080);
1650 write32(&mtk_topckgen2->cksys2_clk_cfg[5].set, 0x808080);
1651 write32(&mtk_topckgen2->cksys2_clk_cfg[6].set, 0x80808080);
1652
1653 vote_init();
1654 mmvote_init();
1655 }
1656
1657 void mt_pll_raise_little_cpu_freq(u32 freq)
1658 {
1659 const struct pll *pll = &mcusys_plls[CLK_CPLL_ARMPLL_LL];
1660
1661 clrbits32(&mtk_mcusys->cpu_plldiv0_cfg, GENMASK(10, 8));
1662 setbits32(&mtk_mcusys->cpu_plldiv0_cfg, BIT(10));
1663
1664 clrbits32(pll->reg, MT8196_PLL_EN);
1665 pll_set_rate(pll, freq);
1666 setbits32(pll->reg, MT8196_PLL_EN);
1667
1668 clrsetbits32(&mtk_mcusys->cpu_plldiv0_cfg, GENMASK(10, 8), BIT(8));
1669 setbits32(&mtk_mcusys->cpu_plldiv0_cfg, BIT(10));
1670 }
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