src/soc/rockchip/common/vop.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <soc/addressmap.h>
   5 #include <soc/clock.h>
   6 #include <soc/edp.h>
   7 #include <soc/vop.h>
   8
   9 static struct rockchip_vop_regs * const vop_regs[] = {
  10         (struct rockchip_vop_regs *)VOP_BIG_BASE,
  11         (struct rockchip_vop_regs *)VOP_LIT_BASE
  12 };
  13
  14 void rkvop_enable(u32 vop_id, u32 fbbase)
  15 {
  16         struct rockchip_vop_regs *preg = vop_regs[vop_id];
  17
  18         write32(&preg->win0_yrgb_mst, fbbase);
  19
  20         /* On RK3288, the reg_cfg_done[1:31] is reserved and read-only,
  21          * but it's fine to write to it
  22          */
  23         write32(&preg->reg_cfg_done, 0xffff); /* enable reg config */
  24 }
  25
  26 void rkvop_prepare(u32 vop_id, const struct edid *edid)
  27 {
  28         u32 lb_mode;
  29         u32 rgb_mode;
  30         u32 hactive = edid->mode.ha;
  31         u32 vactive = edid->mode.va;
  32         u32 hsync_len = edid->mode.hspw;
  33         u32 hback_porch = edid->mode.hbl - edid->mode.hso - edid->mode.hspw;
  34         u32 vsync_len = edid->mode.vspw;
  35         u32 vback_porch = edid->mode.vbl - edid->mode.vso - edid->mode.vspw;
  36         u32 xpos = 0, ypos = 0;
  37         struct rockchip_vop_regs *preg = vop_regs[vop_id];
  38
  39         write32(&preg->win0_act_info,
  40                 V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1));
  41
  42         write32(&preg->win0_dsp_st, V_DSP_XST(xpos + hsync_len + hback_porch) |
  43                                     V_DSP_YST(ypos + vsync_len + vback_porch));
  44
  45         write32(&preg->win0_dsp_info, V_DSP_WIDTH(hactive - 1) |
  46                                       V_DSP_HEIGHT(vactive - 1));
  47
  48         clrsetbits32(&preg->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
  49                                                 V_WIN0_KEY_EN(0) |
  50                                                 V_WIN0_KEY_COLOR(0));
  51
  52         switch (edid->framebuffer_bits_per_pixel) {
  53         case 16:
  54                 rgb_mode = RGB565;
  55                 write32(&preg->win0_vir, V_RGB565_VIRWIDTH(hactive));
  56                 break;
  57         case 24:
  58                 rgb_mode = RGB888;
  59                 write32(&preg->win0_vir, V_RGB888_VIRWIDTH(hactive));
  60                 break;
  61         case 32:
  62         default:
  63                 rgb_mode = ARGB8888;
  64                 write32(&preg->win0_vir, V_ARGB888_VIRWIDTH(hactive));
  65                 break;
  66         }
  67
  68         if (hactive > 2560)
  69                 lb_mode = LB_RGB_3840X2;
  70         else if (hactive > 1920)
  71                 lb_mode = LB_RGB_2560X4;
  72         else if (hactive > 1280)
  73                 lb_mode = LB_RGB_1920X5;
  74         else
  75                 lb_mode = LB_RGB_1280X8;
  76
  77         clrsetbits32(&preg->win0_ctrl0,
  78                      M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
  79                      V_WIN0_LB_MODE(lb_mode) |
  80                      V_WIN0_DATA_FMT(rgb_mode) | V_WIN0_EN(1));
  81 }
  82
  83 void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode)
  84 {
  85         u32 hactive = edid->mode.ha;
  86         u32 vactive = edid->mode.va;
  87         u32 hfront_porch = edid->mode.hso;
  88         u32 hsync_len = edid->mode.hspw;
  89         u32 hback_porch = edid->mode.hbl - edid->mode.hso - edid->mode.hspw;
  90         u32 vfront_porch = edid->mode.vso;
  91         u32 vsync_len = edid->mode.vspw;
  92         u32 vback_porch = edid->mode.vbl - edid->mode.vso - edid->mode.vspw;
  93         u32 dsp_out_mode;
  94         struct rockchip_vop_regs *preg = vop_regs[vop_id];
  95
  96         switch (mode) {
  97         case VOP_MODE_HDMI:
  98                 clrsetbits32(&preg->sys_ctrl,
  99                              M_ALL_OUT_EN, V_HDMI_OUT_EN(1));
 100                 dsp_out_mode = 15;
 101                 break;
 102         case VOP_MODE_MIPI:
 103                 clrsetbits32(&preg->sys_ctrl, M_ALL_OUT_EN,
 104                              V_MIPI_OUT_EN(1));
 105                 dsp_out_mode = 0;
 106                 break;
 107         case VOP_MODE_DUAL_MIPI:
 108                 clrsetbits32(&preg->sys_ctrl, M_ALL_OUT_EN,
 109                              V_MIPI_OUT_EN(1) | V_DUAL_MIPI_EN(1));
 110                 dsp_out_mode = 0;
 111                 break;
 112         case VOP_MODE_EDP:
 113         default:
 114                 clrsetbits32(&preg->sys_ctrl,
 115                              M_ALL_OUT_EN, V_EDP_OUT_EN(1));
 116                 dsp_out_mode = 15;
 117                 break;
 118         }
 119
 120         clrsetbits32(&preg->dsp_ctrl0,
 121                      M_DSP_OUT_MODE | M_DSP_VSYNC_POL |
 122                      M_DSP_HSYNC_POL,
 123                      V_DSP_OUT_MODE(dsp_out_mode) |
 124                      V_DSP_HSYNC_POL(edid->mode.phsync == '+') |
 125                      V_DSP_VSYNC_POL(edid->mode.pvsync == '+'));
 126
 127         write32(&preg->dsp_htotal_hs_end, V_HSYNC(hsync_len) |
 128                 V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch));
 129
 130         write32(&preg->dsp_hact_st_end,
 131                 V_HEAP(hsync_len + hback_porch + hactive) |
 132                 V_HASP(hsync_len + hback_porch));
 133
 134         write32(&preg->dsp_vtotal_vs_end, V_VSYNC(vsync_len) |
 135                 V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch));
 136
 137         write32(&preg->dsp_vact_st_end,
 138                 V_VAEP(vsync_len + vback_porch + vactive) |
 139                 V_VASP(vsync_len + vback_porch));
 140
 141         write32(&preg->post_dsp_hact_info,
 142                 V_HEAP(hsync_len + hback_porch + hactive) |
 143                 V_HASP(hsync_len + hback_porch));
 144
 145         write32(&preg->post_dsp_vact_info,
 146                 V_VAEP(vsync_len + vback_porch + vactive) |
 147                 V_VASP(vsync_len + vback_porch));
 148
 149         /* On RK3288, the reg_cfg_done[1:31] is reserved and read-only,
 150          * but it's fine to write to it
 151          */
 152         write32(&preg->reg_cfg_done, 0xffff); /* enable reg config */
 153 }