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drivers/wifi: Remove unnecessary data structure copy
[coreboot2.git] / src / soc / rockchip / rk3288 / sdram.c
blob0237ca26f2bc997a4ca11a5617102e43c24bfa9d
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 #include <device/mmio.h>
3 #include <console/console.h>
4 #include <delay.h>
5 #include <soc/addressmap.h>
6 #include <soc/clock.h>
7 #include <soc/sdram.h>
8 #include <soc/grf.h>
9 #include <soc/soc.h>
10 #include <soc/pmu.h>
11 #include <types.h>
12
13 struct rk3288_ddr_pctl_regs {
14 u32 scfg;
15 u32 sctl;
16 u32 stat;
17 u32 intrstat;
18 u32 reserved0[12];
19 u32 mcmd;
20 u32 powctl;
21 u32 powstat;
22 u32 cmdtstat;
23 u32 tstaten;
24 u32 reserved1[3];
25 u32 mrrcfg0;
26 u32 mrrstat0;
27 u32 mrrstat1;
28 u32 reserved2[4];
29 u32 mcfg1;
30 u32 mcfg;
31 u32 ppcfg;
32 u32 mstat;
33 u32 lpddr2zqcfg;
34 u32 reserved3;
35 u32 dtupdes;
36 u32 dtuna;
37 u32 dtune;
38 u32 dtuprd0;
39 u32 dtuprd1;
40 u32 dtuprd2;
41 u32 dtuprd3;
42 u32 dtuawdt;
43 u32 reserved4[3];
44 u32 togcnt1u;
45 u32 tinit;
46 u32 trsth;
47 u32 togcnt100n;
48 u32 trefi;
49 u32 tmrd;
50 u32 trfc;
51 u32 trp;
52 u32 trtw;
53 u32 tal;
54 u32 tcl;
55 u32 tcwl;
56 u32 tras;
57 u32 trc;
58 u32 trcd;
59 u32 trrd;
60 u32 trtp;
61 u32 twr;
62 u32 twtr;
63 u32 texsr;
64 u32 txp;
65 u32 txpdll;
66 u32 tzqcs;
67 u32 tzqcsi;
68 u32 tdqs;
69 u32 tcksre;
70 u32 tcksrx;
71 u32 tcke;
72 u32 tmod;
73 u32 trstl;
74 u32 tzqcl;
75 u32 tmrr;
76 u32 tckesr;
77 u32 tdpd;
78 u32 reserved5[14];
79 u32 ecccfg;
80 u32 ecctst;
81 u32 eccclr;
82 u32 ecclog;
83 u32 reserved6[28];
84 u32 dtuwactl;
85 u32 dturactl;
86 u32 dtucfg;
87 u32 dtuectl;
88 u32 dtuwd0;
89 u32 dtuwd1;
90 u32 dtuwd2;
91 u32 dtuwd3;
92 u32 dtuwdm;
93 u32 dturd0;
94 u32 dturd1;
95 u32 dturd2;
96 u32 dturd3;
97 u32 dtulfsrwd;
98 u32 dtulfsrrd;
99 u32 dtueaf;
100 u32 dfitctrldelay;
101 u32 dfiodtcfg;
102 u32 dfiodtcfg1;
103 u32 dfiodtrankmap;
104 u32 dfitphywrdata;
105 u32 dfitphywrlat;
106 u32 reserved7[2];
107 u32 dfitrddataen;
108 u32 dfitphyrdlat;
109 u32 reserved8[2];
110 u32 dfitphyupdtype0;
111 u32 dfitphyupdtype1;
112 u32 dfitphyupdtype2;
113 u32 dfitphyupdtype3;
114 u32 dfitctrlupdmin;
115 u32 dfitctrlupdmax;
116 u32 dfitctrlupddly;
117 u32 reserved9;
118 u32 dfiupdcfg;
119 u32 dfitrefmski;
120 u32 dfitctrlupdi;
121 u32 reserved10[4];
122 u32 dfitrcfg0;
123 u32 dfitrstat0;
124 u32 dfitrwrlvlen;
125 u32 dfitrrdlvlen;
126 u32 dfitrrdlvlgateen;
127 u32 dfiststat0;
128 u32 dfistcfg0;
129 u32 dfistcfg1;
130 u32 reserved11;
131 u32 dfitdramclken;
132 u32 dfitdramclkdis;
133 u32 dfistcfg2;
134 u32 dfistparclr;
135 u32 dfistparlog;
136 u32 reserved12[3];
137 u32 dfilpcfg0;
138 u32 reserved13[3];
139 u32 dfitrwrlvlresp0;
140 u32 dfitrwrlvlresp1;
141 u32 dfitrwrlvlresp2;
142 u32 dfitrrdlvlresp0;
143 u32 dfitrrdlvlresp1;
144 u32 dfitrrdlvlresp2;
145 u32 dfitrwrlvldelay0;
146 u32 dfitrwrlvldelay1;
147 u32 dfitrwrlvldelay2;
148 u32 dfitrrdlvldelay0;
149 u32 dfitrrdlvldelay1;
150 u32 dfitrrdlvldelay2;
151 u32 dfitrrdlvlgatedelay0;
152 u32 dfitrrdlvlgatedelay1;
153 u32 dfitrrdlvlgatedelay2;
154 u32 dfitrcmd;
155 u32 reserved14[46];
156 u32 ipvr;
157 u32 iptr;
158 };
159 check_member(rk3288_ddr_pctl_regs, iptr, 0x03fc);
160
161 struct rk3288_ddr_publ_datx {
162 u32 dxgcr;
163 u32 dxgsr[2];
164 u32 dxdllcr;
165 u32 dxdqtr;
166 u32 dxdqstr;
167 u32 reserved[10];
168 };
169
170 struct rk3288_ddr_publ_regs {
171 u32 ridr;
172 u32 pir;
173 u32 pgcr;
174 u32 pgsr;
175 u32 dllgcr;
176 u32 acdllcr;
177 u32 ptr[3];
178 u32 aciocr;
179 u32 dxccr;
180 u32 dsgcr;
181 u32 dcr;
182 u32 dtpr[3];
183 u32 mr[4];
184 u32 odtcr;
185 u32 dtar;
186 u32 dtdr[2];
187 u32 reserved1[24];
188 u32 dcuar;
189 u32 dcudr;
190 u32 dcurr;
191 u32 dculr;
192 u32 dcugcr;
193 u32 dcutpr;
194 u32 dcusr[2];
195 u32 reserved2[8];
196 u32 bist[17];
197 u32 reserved3[15];
198 u32 zq0cr[2];
199 u32 zq0sr[2];
200 u32 zq1cr[2];
201 u32 zq1sr[2];
202 u32 zq2cr[2];
203 u32 zq2sr[2];
204 u32 zq3cr[2];
205 u32 zq3sr[2];
206 struct rk3288_ddr_publ_datx datx8[4];
207 };
208 check_member(rk3288_ddr_publ_regs, datx8[3].dxdqstr, 0x0294);
209
210 struct rk3288_msch_regs {
211 u32 coreid;
212 u32 revisionid;
213 u32 ddrconf;
214 u32 ddrtiming;
215 u32 ddrmode;
216 u32 readlatency;
217 u32 reserved1[8];
218 u32 activate;
219 u32 devtodev;
220 };
221 check_member(rk3288_msch_regs, devtodev, 0x003c);
222
223 static struct rk3288_ddr_pctl_regs * const rk3288_ddr_pctl[2] = {
224 (void *)DDR_PCTL0_BASE, (void *)DDR_PCTL1_BASE};
225 static struct rk3288_ddr_publ_regs * const rk3288_ddr_publ[2] = {
226 (void *)DDR_PUBL0_BASE, (void *)DDR_PUBL1_BASE};
227 static struct rk3288_msch_regs * const rk3288_msch[2] = {
228 (void *)SERVICE_BUS_BASE, (void *)SERVICE_BUS_BASE + 0x80};
229
230 /* PCT_DFISTCFG0 */
231 #define DFI_INIT_START (1 << 0)
232
233 /* PCT_DFISTCFG1 */
234 #define DFI_DRAM_CLK_SR_EN (1 << 0)
235 #define DFI_DRAM_CLK_DPD_EN (1 << 1)
236
237 /* PCT_DFISTCFG2 */
238 #define DFI_PARITY_INTR_EN (1 << 0)
239 #define DFI_PARITY_EN (1 << 1)
240
241 /* PCT_DFILPCFG0 */
242 #define TLP_RESP_TIME(n) (n << 16)
243 #define LP_SR_EN (1 << 8)
244 #define LP_PD_EN (1 << 0)
245
246 /* PCT_DFITCTRLDELAY */
247 #define TCTRL_DELAY_TIME(n) (n << 0)
248
249 /* PCT_DFITPHYWRDATA */
250 #define TPHY_WRDATA_TIME(n) (n << 0)
251
252 /* PCT_DFITPHYRDLAT */
253 #define TPHY_RDLAT_TIME(n) (n << 0)
254
255 /* PCT_DFITDRAMCLKDIS */
256 #define TDRAM_CLK_DIS_TIME(n) (n << 0)
257
258 /* PCT_DFITDRAMCLKEN */
259 #define TDRAM_CLK_EN_TIME(n) (n << 0)
260
261 /* PCTL_DFIODTCFG */
262 #define RANK0_ODT_WRITE_SEL (1 << 3)
263 #define RANK1_ODT_WRITE_SEL (1 << 11)
264
265 /* PCTL_DFIODTCFG1 */
266 #define ODT_LEN_BL8_W(n) (n<<16)
267
268 /* PUBL_ACDLLCR */
269 #define ACDLLCR_DLLDIS (1 << 31)
270 #define ACDLLCR_DLLSRST (1 << 30)
271
272 /* PUBL_DXDLLCR */
273 #define DXDLLCR_DLLDIS (1 << 31)
274 #define DXDLLCR_DLLSRST (1 << 30)
275
276 /* PUBL_DLLGCR */
277 #define DLLGCR_SBIAS (1 << 30)
278
279 /* PUBL_DXGCR */
280 #define DQSRTT (1 << 9)
281 #define DQRTT (1 << 10)
282
283 /* PIR */
284 #define PIR_INIT (1 << 0)
285 #define PIR_DLLSRST (1 << 1)
286 #define PIR_DLLLOCK (1 << 2)
287 #define PIR_ZCAL (1 << 3)
288 #define PIR_ITMSRST (1 << 4)
289 #define PIR_DRAMRST (1 << 5)
290 #define PIR_DRAMINIT (1 << 6)
291 #define PIR_QSTRN (1 << 7)
292 #define PIR_RVTRN (1 << 8)
293 #define PIR_ICPC (1 << 16)
294 #define PIR_DLLBYP (1 << 17)
295 #define PIR_CTLDINIT (1 << 18)
296 #define PIR_CLRSR (1 << 28)
297 #define PIR_LOCKBYP (1 << 29)
298 #define PIR_ZCALBYP (1 << 30)
299 #define PIR_INITBYP (1u << 31)
300
301 /* PGCR */
302 #define PGCR_DFTLMT(n) ((n) << 3)
303 #define PGCR_DFTCMP(n) ((n) << 2)
304 #define PGCR_DQSCFG(n) ((n) << 1)
305 #define PGCR_ITMDMD(n) ((n) << 0)
306
307 /* PGSR */
308 #define PGSR_IDONE (1 << 0)
309 #define PGSR_DLDONE (1 << 1)
310 #define PGSR_ZCDONE (1 << 2)
311 #define PGSR_DIDONE (1 << 3)
312 #define PGSR_DTDONE (1 << 4)
313 #define PGSR_DTERR (1 << 5)
314 #define PGSR_DTIERR (1 << 6)
315 #define PGSR_DFTERR (1 << 7)
316 #define PGSR_RVERR (1 << 8)
317 #define PGSR_RVEIRR (1 << 9)
318
319 /* PTR0 */
320 #define PRT_ITMSRST(n) ((n) << 18)
321 #define PRT_DLLLOCK(n) ((n) << 6)
322 #define PRT_DLLSRST(n) ((n) << 0)
323
324 /* PTR1 */
325 #define PRT_DINIT0(n) ((n) << 0)
326 #define PRT_DINIT1(n) ((n) << 19)
327
328 /* PTR2 */
329 #define PRT_DINIT2(n) ((n) << 0)
330 #define PRT_DINIT3(n) ((n) << 17)
331
332 /* DCR */
333 #define DDRMD_LPDDR 0
334 #define DDRMD_DDR 1
335 #define DDRMD_DDR2 2
336 #define DDRMD_DDR3 3
337 #define DDRMD_LPDDR2_LPDDR3 4
338 #define DDRMD_MSK (7 << 0)
339 #define DDRMD_CFG(n) ((n) << 0)
340 #define PDQ_MSK (7 << 4)
341 #define PDQ_CFG(n) ((n) << 4)
342
343 /* DXCCR */
344 #define DQSNRES_MSK (0x0f << 8)
345 #define DQSNRES_CFG(n) ((n) << 8)
346 #define DQSRES_MSK (0x0f << 4)
347 #define DQSRES_CFG(n) ((n) << 4)
348
349 /* DTPR */
350 #define TDQSCKMAX_VAL(n) (((n) >> 27) & 7)
351 #define TDQSCK_VAL(n) (((n) >> 24) & 7)
352
353 /* DSGCR */
354 #define DQSGX_MSK (0x07 << 5)
355 #define DQSGX_CFG(n) ((n) << 5)
356 #define DQSGE_MSK (0x07 << 8)
357 #define DQSGE_CFG(n) ((n) << 8)
358
359 /* SCTL */
360 #define INIT_STATE (0)
361 #define CFG_STATE (1)
362 #define GO_STATE (2)
363 #define SLEEP_STATE (3)
364 #define WAKEUP_STATE (4)
365
366 /* STAT */
367 #define LP_TRIG_VAL(n) (((n) >> 4) & 7)
368 #define PCTL_STAT_MSK (7)
369 #define INIT_MEM (0)
370 #define CONF (1)
371 #define CONF_REQ (2)
372 #define ACCESS (3)
373 #define ACCESS_REQ (4)
374 #define LOW_POWER (5)
375 #define LOW_POWER_ENTRY_REQ (6)
376 #define LOW_POWER_EXIT_REQ (7)
377
378 /* ZQCR*/
379 #define PD_OUTPUT(n) ((n) << 0)
380 #define PU_OUTPUT(n) ((n) << 5)
381 #define PD_ONDIE(n) ((n) << 10)
382 #define PU_ONDIE(n) ((n) << 15)
383 #define ZDEN(n) ((n) << 28)
384
385 /* DDLGCR */
386 #define SBIAS_BYPASS (1 << 23)
387
388 /* MCFG */
389 #define MDDR_LPDDR2_CLK_STOP_IDLE(n) ((n) << 24)
390 #define PD_IDLE(n) ((n) << 8)
391 #define MDDR_EN (2 << 22)
392 #define LPDDR2_EN (3 << 22)
393 #define DDR2_EN (0 << 5)
394 #define DDR3_EN (1 << 5)
395 #define LPDDR2_S2 (0 << 6)
396 #define LPDDR2_S4 (1 << 6)
397 #define MDDR_LPDDR2_BL_2 (0 << 20)
398 #define MDDR_LPDDR2_BL_4 (1 << 20)
399 #define MDDR_LPDDR2_BL_8 (2 << 20)
400 #define MDDR_LPDDR2_BL_16 (3 << 20)
401 #define DDR2_DDR3_BL_4 (0)
402 #define DDR2_DDR3_BL_8 (1)
403 #define TFAW_CFG(n) (((n)-4) << 18)
404 #define PD_EXIT_SLOW (0 << 17)
405 #define PD_EXIT_FAST (1 << 17)
406 #define PD_TYPE(n) ((n) << 16)
407 #define BURSTLENGTH_CFG(n) (((n) >> 1) << 20)
408
409 /* POWCTL */
410 #define POWER_UP_START (1 << 0)
411
412 /* POWSTAT */
413 #define POWER_UP_DONE (1 << 0)
414
415 /* MCMD */
416 #define DESELECT_CMD (0)
417 #define PREA_CMD (1)
418 #define REF_CMD (2)
419 #define MRS_CMD (3)
420 #define ZQCS_CMD (4)
421 #define ZQCL_CMD (5)
422 #define RSTL_CMD (6)
423 #define MRR_CMD (8)
424 #define DPDE_CMD (9)
425
426 #define LPDDR2_MA(n) (((n) & 0xff) << 4)
427 #define LPDDR2_OP(n) (((n) & 0xff) << 12)
428
429 #define START_CMD (1u << 31)
430
431 /* DEVTODEV */
432 #define BUSWRTORD(n) ((n) << 4)
433 #define BUSRDTOWR(n) ((n) << 2)
434 #define BUSRDTORD(n) ((n) << 0)
435
436 /* GRF_SOC_CON0 */
437 #define MSCH_MAINDDR3(ch, n) (((n) << (3 + (ch))) \
438 | ((1 << (3 + (ch))) << 16))
439
440 /* GRF_SOC_CON2 */
441 #define PCTL_LPDDR3_ODT_EN(ch, n) RK_CLRSETBITS(1 << (10 + (3 * (ch))), \
442 (n) << (10 + (3 * (ch))))
443 #define PCTL_BST_DISABLE(ch, n) RK_CLRSETBITS(1 << (9 + (3 * (ch))), \
444 (n) << (9 + (3 * (ch))))
445 #define PUBL_LPDDR3_EN(ch, n) RK_CLRSETBITS(1 << (8 + (3 * (ch))), \
446 (n) << (8 + (3 * (ch))))
447
448 /* mr1 for ddr3 */
449 #define DDR3_DLL_ENABLE (0)
450 #define DDR3_DLL_DISABLE (1)
451
452 /*
453 * sys_reg bitfield struct
454 * [31] row_3_4_ch1
455 * [30] row_3_4_ch0
456 * [29:28] chinfo
457 * [27] rank_ch1
458 * [26:25] col_ch1
459 * [24] bk_ch1
460 * [23:22] cs0_row_ch1
461 * [21:20] cs1_row_ch1
462 * [19:18] bw_ch1
463 * [17:16] dbw_ch1;
464 * [15:13] ddrtype
465 * [12] channelnum
466 * [11] rank_ch0
467 * [10:9] col_ch0
468 * [8] bk_ch0
469 * [7:6] cs0_row_ch0
470 * [5:4] cs1_row_ch0
471 * [3:2] bw_ch0
472 * [1:0] dbw_ch0
473 */
474 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
475 #define SYS_REG_DEC_ROW_3_4(n, ch) ((n >> (30 + ch)) & 0x1)
476 #define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch)))
477 #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
478 #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12)
479 #define SYS_REG_DEC_NUM_CH(n) (1 + ((n >> 12) & 0x1))
480 #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + ((ch) * 16)))
481 #define SYS_REG_DEC_RANK(n, ch) (1 + ((n >> (11 + 16 * ch)) & 0x1))
482 #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16)))
483 #define SYS_REG_DEC_COL(n, ch) (9 + ((n >> (9 + 16 * ch)) & 0x3))
484 #define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) \
485 << (8 + ((ch) * 16)))
486 #define SYS_REG_DEC_BK(n, ch) (3 - ((n >> (8 + 16 * ch)) & 0x1))
487 #define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << (6 + ((ch) * 16)))
488 #define SYS_REG_DEC_CS0_ROW(n, ch) (13 + ((n >> (6 + 16 * ch)) & 0x3))
489 #define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << (4 + ((ch) * 16)))
490 #define SYS_REG_DEC_CS1_ROW(n, ch) (13 + ((n >> (4 + 16 * ch)) & 0x3))
491 #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + ((ch) * 16)))
492 #define SYS_REG_DEC_BW(n, ch) (2 >> ((n >> (2 + 16 * ch)) & 0x3))
493 #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16)))
494 #define SYS_REG_DEC_DBW(n, ch) (2 >> ((n >> (0 + 16 * ch)) & 0x3))
495
496 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
497 {
498 int i;
499 for (i = 0; i < n / sizeof(u32); i++) {
500 write32(dest, *src);
501 src++;
502 dest++;
503 }
504 }
505
506 static void phy_pctrl_reset(struct rk3288_ddr_publ_regs *ddr_publ_regs,
507 u32 channel)
508 {
509 int i;
510 rkclk_ddr_reset(channel, 1, 1);
511 udelay(1);
512 clrbits32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLSRST);
513 for (i = 0; i < 4; i++)
514 clrbits32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
515
516 udelay(10);
517 setbits32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLSRST);
518 for (i = 0; i < 4; i++)
519 setbits32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
520
521 udelay(10);
522 rkclk_ddr_reset(channel, 1, 0);
523 udelay(10);
524 rkclk_ddr_reset(channel, 0, 0);
525 udelay(10);
526 }
527
528 static void phy_dll_bypass_set(struct rk3288_ddr_publ_regs *ddr_publ_regs,
529 u32 freq)
530 {
531 int i;
532 if (freq <= 250*MHz) {
533 if (freq <= 150*MHz)
534 clrbits32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS);
535 else
536 setbits32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS);
537 setbits32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLDIS);
538 for (i = 0; i < 4; i++)
539 setbits32(&ddr_publ_regs->datx8[i].dxdllcr,
540 DXDLLCR_DLLDIS);
541
542 setbits32(&ddr_publ_regs->pir, PIR_DLLBYP);
543 } else {
544 clrbits32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS);
545 clrbits32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLDIS);
546 for (i = 0; i < 4; i++)
547 clrbits32(&ddr_publ_regs->datx8[i].dxdllcr,
548 DXDLLCR_DLLDIS);
549
550 clrbits32(&ddr_publ_regs->pir, PIR_DLLBYP);
551 }
552 }
553
554 static void dfi_cfg(struct rk3288_ddr_pctl_regs *ddr_pctl_regs, u32 dramtype)
555 {
556 write32(&ddr_pctl_regs->dfistcfg0, DFI_INIT_START);
557 write32(&ddr_pctl_regs->dfistcfg1,
558 DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN);
559 write32(&ddr_pctl_regs->dfistcfg2, DFI_PARITY_INTR_EN | DFI_PARITY_EN);
560 write32(&ddr_pctl_regs->dfilpcfg0,
561 TLP_RESP_TIME(7) | LP_SR_EN | LP_PD_EN);
562
563 write32(&ddr_pctl_regs->dfitctrldelay, TCTRL_DELAY_TIME(2));
564 write32(&ddr_pctl_regs->dfitphywrdata, TPHY_WRDATA_TIME(1));
565 write32(&ddr_pctl_regs->dfitphyrdlat, TPHY_RDLAT_TIME(0xf));
566 write32(&ddr_pctl_regs->dfitdramclkdis, TDRAM_CLK_DIS_TIME(2));
567 write32(&ddr_pctl_regs->dfitdramclken, TDRAM_CLK_EN_TIME(2));
568 write32(&ddr_pctl_regs->dfitphyupdtype0, 0x1);
569
570 /* cs0 and cs1 write odt enable */
571 write32(&ddr_pctl_regs->dfiodtcfg,
572 (RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL));
573 /* odt write length */
574 write32(&ddr_pctl_regs->dfiodtcfg1, ODT_LEN_BL8_W(7));
575 /* phyupd and ctrlupd disabled */
576 write32(&ddr_pctl_regs->dfiupdcfg, 0);
577 }
578
579 static void pctl_cfg(u32 channel,
580 const struct rk3288_sdram_params *sdram_params)
581 {
582 unsigned int burstlen;
583 struct rk3288_ddr_pctl_regs *ddr_pctl_regs = rk3288_ddr_pctl[channel];
584 burstlen = (sdram_params->noc_timing >> 18) & 0x7;
585 copy_to_reg(&ddr_pctl_regs->togcnt1u,
586 &(sdram_params->pctl_timing.togcnt1u),
587 sizeof(sdram_params->pctl_timing));
588 switch (sdram_params->dramtype) {
589 case LPDDR3:
590 write32(&ddr_pctl_regs->dfitrddataen,
591 sdram_params->pctl_timing.tcl - 1);
592 write32(&ddr_pctl_regs->dfitphywrlat,
593 sdram_params->pctl_timing.tcwl);
594 write32(&ddr_pctl_regs->mcfg, LPDDR2_S4 |
595 MDDR_LPDDR2_CLK_STOP_IDLE(0) | LPDDR2_EN |
596 BURSTLENGTH_CFG(burstlen) | TFAW_CFG(6) |
597 PD_EXIT_FAST | PD_TYPE(1) | PD_IDLE(0));
598 write32(&rk3288_grf->soc_con0, MSCH_MAINDDR3(channel, 0));
599
600 write32(&rk3288_grf->soc_con2, PUBL_LPDDR3_EN(channel, 1) |
601 PCTL_BST_DISABLE(channel, 1) |
602 PCTL_LPDDR3_ODT_EN(channel, sdram_params->odt));
603
604 break;
605 case DDR3:
606 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE)
607 write32(&ddr_pctl_regs->dfitrddataen,
608 sdram_params->pctl_timing.tcl - 3);
609 else
610 write32(&ddr_pctl_regs->dfitrddataen,
611 sdram_params->pctl_timing.tcl - 2);
612 write32(&ddr_pctl_regs->dfitphywrlat,
613 sdram_params->pctl_timing.tcwl - 1);
614 write32(&ddr_pctl_regs->mcfg,
615 MDDR_LPDDR2_CLK_STOP_IDLE(0) | DDR3_EN |
616 DDR2_DDR3_BL_8 | TFAW_CFG(6) |
617 PD_EXIT_SLOW | PD_TYPE(1) | PD_IDLE(0));
618 write32(&rk3288_grf->soc_con0, MSCH_MAINDDR3(channel, 1));
619
620 write32(&rk3288_grf->soc_con2, PUBL_LPDDR3_EN(channel, 0) |
621 PCTL_BST_DISABLE(channel, 0) |
622 PCTL_LPDDR3_ODT_EN(channel, 0));
623
624 break;
625 }
626
627 setbits32(&ddr_pctl_regs->scfg, 1);
628 }
629
630 static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params)
631 {
632 u32 i;
633 u32 dinit2 = DIV_ROUND_UP(sdram_params->ddr_freq/MHz * 200000, 1000);
634 struct rk3288_ddr_publ_regs *ddr_publ_regs = rk3288_ddr_publ[channel];
635 struct rk3288_msch_regs *msch_regs = rk3288_msch[channel];
636
637 /* DDR PHY Timing */
638 copy_to_reg(&ddr_publ_regs->dtpr[0],
639 &(sdram_params->phy_timing.dtpr0),
640 sizeof(sdram_params->phy_timing));
641 write32(&msch_regs->ddrtiming, sdram_params->noc_timing);
642 write32(&msch_regs->readlatency, 0x3f);
643 write32(&msch_regs->activate, sdram_params->noc_activate);
644 write32(&msch_regs->devtodev,
645 BUSWRTORD(2) | BUSRDTOWR(2) | BUSRDTORD(1));
646 write32(&ddr_publ_regs->ptr[0],
647 PRT_DLLLOCK(DIV_ROUND_UP(sdram_params->ddr_freq / MHz * 5120, 1000))
648 | PRT_DLLSRST(DIV_ROUND_UP(sdram_params->ddr_freq / MHz * 50, 1000))
649 | PRT_ITMSRST(8));
650 write32(&ddr_publ_regs->ptr[1],
651 PRT_DINIT0(DIV_ROUND_UP(sdram_params->ddr_freq / MHz * 500000, 1000))
652 | PRT_DINIT1(DIV_ROUND_UP(sdram_params->ddr_freq / MHz * 400, 1000)));
653 write32(&ddr_publ_regs->ptr[2], PRT_DINIT2(MIN(dinit2, 0x1ffff))
654 | PRT_DINIT3(DIV_ROUND_UP(sdram_params->ddr_freq / MHz * 1000, 1000)));
655
656 switch (sdram_params->dramtype) {
657 case LPDDR3:
658 clrsetbits32(&ddr_publ_regs->pgcr, 0x1F, PGCR_DFTLMT(0)
659 | PGCR_DFTCMP(0) | PGCR_DQSCFG(1) | PGCR_ITMDMD(0));
660 /* DDRMODE select LPDDR3 */
661 clrsetbits32(&ddr_publ_regs->dcr, DDRMD_MSK,
662 DDRMD_CFG(DDRMD_LPDDR2_LPDDR3));
663 clrsetbits32(&ddr_publ_regs->dxccr, DQSNRES_MSK | DQSRES_MSK,
664 DQSRES_CFG(4) | DQSNRES_CFG(0xc));
665 i = TDQSCKMAX_VAL(read32(&ddr_publ_regs->dtpr[1]))
666 - TDQSCK_VAL(read32(&ddr_publ_regs->dtpr[1]));
667 clrsetbits32(&ddr_publ_regs->dsgcr, DQSGE_MSK | DQSGX_MSK,
668 DQSGE_CFG(i) | DQSGX_CFG(i));
669 break;
670 case DDR3:
671 clrbits32(&ddr_publ_regs->pgcr, 0x1f);
672 clrsetbits32(&ddr_publ_regs->dcr, DDRMD_MSK,
673 DDRMD_CFG(DDRMD_DDR3));
674 break;
675 }
676 if (sdram_params->odt) {
677 /*dynamic RTT enable */
678 for (i = 0; i < 4; i++)
679 setbits32(&ddr_publ_regs->datx8[i].dxgcr,
680 DQSRTT | DQRTT);
681 } else {
682 /*dynamic RTT disable */
683 for (i = 0; i < 4; i++)
684 clrbits32(&ddr_publ_regs->datx8[i].dxgcr,
685 DQSRTT | DQRTT);
686 }
687 }
688
689 static void phy_init(struct rk3288_ddr_publ_regs *ddr_publ_regs)
690 {
691 setbits32(&ddr_publ_regs->pir, PIR_INIT | PIR_DLLSRST
692 | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR);
693 udelay(1);
694 while ((read32(&ddr_publ_regs->pgsr) &
695 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) !=
696 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE))
697 ;
698 }
699
700 static void send_command(struct rk3288_ddr_pctl_regs *ddr_pctl_regs, u32 rank,
701 u32 cmd, u32 arg)
702 {
703 write32(&ddr_pctl_regs->mcmd, (START_CMD | (rank << 20) | arg | cmd));
704 udelay(1);
705 while (read32(&ddr_pctl_regs->mcmd) & START_CMD)
706 ;
707 }
708
709 static void memory_init(struct rk3288_ddr_publ_regs *ddr_publ_regs,
710 u32 dramtype)
711 {
712 setbits32(&ddr_publ_regs->pir,
713 (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP
714 | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC
715 | (dramtype == DDR3 ? PIR_DRAMRST : 0)));
716 udelay(1);
717 while ((read32(&ddr_publ_regs->pgsr) & (PGSR_IDONE | PGSR_DLDONE))
718 != (PGSR_IDONE | PGSR_DLDONE))
719 ;
720 }
721
722 static void move_to_config_state(struct rk3288_ddr_publ_regs *ddr_publ_regs,
723 struct rk3288_ddr_pctl_regs *ddr_pctl_regs)
724 {
725 unsigned int state;
726
727 while (1) {
728 state = read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK;
729
730 switch (state) {
731 case LOW_POWER:
732 write32(&ddr_pctl_regs->sctl, WAKEUP_STATE);
733 while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK)
734 != ACCESS)
735 ;
736 /* wait DLL lock */
737 while ((read32(&ddr_publ_regs->pgsr) & PGSR_DLDONE)
738 != PGSR_DLDONE)
739 ;
740 /* if at low power state, need wakeup first, then enter the config */
741 __fallthrough;
742 case ACCESS:
743 case INIT_MEM:
744 write32(&ddr_pctl_regs->sctl, CFG_STATE);
745 while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK)
746 != CONF)
747 ;
748 break;
749 case CONF:
750 return;
751 default:
752 break;
753 }
754 }
755 }
756
757 static void set_bandwidth_ratio(u32 channel, u32 n)
758 {
759 struct rk3288_ddr_pctl_regs *ddr_pctl_regs = rk3288_ddr_pctl[channel];
760 struct rk3288_ddr_publ_regs *ddr_publ_regs = rk3288_ddr_publ[channel];
761 struct rk3288_msch_regs *msch_regs = rk3288_msch[channel];
762
763 if (n == 1) {
764 setbits32(&ddr_pctl_regs->ppcfg, 1);
765 write32(&rk3288_grf->soc_con0, RK_SETBITS(1 << (8 + channel)));
766 setbits32(&msch_regs->ddrtiming, 1 << 31);
767 /* Data Byte disable*/
768 clrbits32(&ddr_publ_regs->datx8[2].dxgcr, 1);
769 clrbits32(&ddr_publ_regs->datx8[3].dxgcr, 1);
770 /*disable DLL */
771 setbits32(&ddr_publ_regs->datx8[2].dxdllcr,
772 DXDLLCR_DLLDIS);
773 setbits32(&ddr_publ_regs->datx8[3].dxdllcr,
774 DXDLLCR_DLLDIS);
775 } else {
776 clrbits32(&ddr_pctl_regs->ppcfg, 1);
777 write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << (8 + channel)));
778 clrbits32(&msch_regs->ddrtiming, 1 << 31);
779 /* Data Byte enable*/
780 setbits32(&ddr_publ_regs->datx8[2].dxgcr, 1);
781 setbits32(&ddr_publ_regs->datx8[3].dxgcr, 1);
782
783 /*enable DLL */
784 clrbits32(&ddr_publ_regs->datx8[2].dxdllcr,
785 DXDLLCR_DLLDIS);
786 clrbits32(&ddr_publ_regs->datx8[3].dxdllcr,
787 DXDLLCR_DLLDIS);
788 /* reset DLL */
789 clrbits32(&ddr_publ_regs->datx8[2].dxdllcr,
790 DXDLLCR_DLLSRST);
791 clrbits32(&ddr_publ_regs->datx8[3].dxdllcr,
792 DXDLLCR_DLLSRST);
793 udelay(10);
794 setbits32(&ddr_publ_regs->datx8[2].dxdllcr,
795 DXDLLCR_DLLSRST);
796 setbits32(&ddr_publ_regs->datx8[3].dxdllcr,
797 DXDLLCR_DLLSRST);
798 }
799 setbits32(&ddr_pctl_regs->dfistcfg0, 1 << 2);
800 }
801
802 static int data_training(u32 channel,
803 const struct rk3288_sdram_params *sdram_params)
804 {
805 unsigned int j;
806 int ret = 0;
807 u32 rank;
808 int i;
809 u32 step[2] = { PIR_QSTRN, PIR_RVTRN };
810 struct rk3288_ddr_publ_regs *ddr_publ_regs = rk3288_ddr_publ[channel];
811 struct rk3288_ddr_pctl_regs *ddr_pctl_regs = rk3288_ddr_pctl[channel];
812
813 /* disable auto refresh */
814 write32(&ddr_pctl_regs->trefi, 0);
815
816 if (sdram_params->dramtype != LPDDR3)
817 setbits32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1));
818 rank = sdram_params->ch[channel].rank | 1;
819 for (j = 0; j < ARRAY_SIZE(step); j++) {
820 /*
821 * trigger QSTRN and RVTRN
822 * clear DTDONE status
823 */
824 setbits32(&ddr_publ_regs->pir, PIR_CLRSR);
825
826 /* trigger DTT */
827 setbits32(&ddr_publ_regs->pir,
828 PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP |
829 PIR_CLRSR);
830 udelay(1);
831 /* wait echo byte DTDONE */
832 while ((read32(&ddr_publ_regs->datx8[0].dxgsr[0]) & rank)
833 != rank)
834 ;
835 while ((read32(&ddr_publ_regs->datx8[1].dxgsr[0]) & rank)
836 != rank)
837 ;
838 if (!(read32(&ddr_pctl_regs->ppcfg) & 1)) {
839 while ((read32(&ddr_publ_regs->datx8[2].dxgsr[0])
840 & rank) != rank)
841 ;
842 while ((read32(&ddr_publ_regs->datx8[3].dxgsr[0])
843 & rank) != rank)
844 ;
845 }
846 if (read32(&ddr_publ_regs->pgsr) &
847 (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) {
848 ret = -1;
849 break;
850 }
851 }
852 /* send some auto refresh to complement the lost while DTT */
853 for (i = 0; i < (rank > 1 ? 8 : 4); i++)
854 send_command(ddr_pctl_regs, rank, REF_CMD, 0);
855
856 if (sdram_params->dramtype != LPDDR3)
857 clrbits32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1));
858
859 /* resume auto refresh */
860 write32(&ddr_pctl_regs->trefi, sdram_params->pctl_timing.trefi);
861
862 return ret;
863 }
864
865 static void move_to_access_state(u32 chnum)
866 {
867 struct rk3288_ddr_publ_regs *ddr_publ_regs = rk3288_ddr_publ[chnum];
868 struct rk3288_ddr_pctl_regs *ddr_pctl_regs = rk3288_ddr_pctl[chnum];
869
870 unsigned int state;
871
872 while (1) {
873 state = read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK;
874
875 switch (state) {
876 case LOW_POWER:
877 if (LP_TRIG_VAL(read32(&ddr_pctl_regs->stat)) == 1)
878 return;
879
880 write32(&ddr_pctl_regs->sctl, WAKEUP_STATE);
881 while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK)
882 != ACCESS)
883 ;
884 /* wait DLL lock */
885 while ((read32(&ddr_publ_regs->pgsr) & PGSR_DLDONE)
886 != PGSR_DLDONE)
887 ;
888 break;
889 case INIT_MEM:
890 write32(&ddr_pctl_regs->sctl, CFG_STATE);
891 while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK)
892 != CONF)
893 ;
894 /* enter config next to get to access state */
895 __fallthrough;
896 case CONF:
897 write32(&ddr_pctl_regs->sctl, GO_STATE);
898 while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK)
899 == CONF)
900 ;
901 break;
902 case ACCESS:
903 return;
904 default:
905 break;
906 }
907 }
908 }
909
910 static void dram_cfg_rbc(u32 chnum,
911 const struct rk3288_sdram_params *sdram_params)
912 {
913 struct rk3288_ddr_publ_regs *ddr_publ_regs = rk3288_ddr_publ[chnum];
914 struct rk3288_msch_regs *msch_regs = rk3288_msch[chnum];
915
916 if (sdram_params->ch[chnum].bk == 3)
917 clrsetbits32(&ddr_publ_regs->dcr, PDQ_MSK, PDQ_CFG(1));
918 else
919 clrbits32(&ddr_publ_regs->dcr, PDQ_MSK);
920
921 write32(&msch_regs->ddrconf, sdram_params->ddrconfig);
922 }
923
924 static void dram_all_config(const struct rk3288_sdram_params *sdram_params)
925 {
926 u32 sys_reg = 0;
927 unsigned int channel;
928
929 sys_reg |= SYS_REG_ENC_DDRTYPE(sdram_params->dramtype);
930 sys_reg |= SYS_REG_ENC_NUM_CH(sdram_params->num_channels);
931 for (channel = 0; channel < sdram_params->num_channels; channel++) {
932 const struct rk3288_sdram_channel *info =
933 &(sdram_params->ch[channel]);
934 sys_reg |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel);
935 sys_reg |= SYS_REG_ENC_CHINFO(channel);
936 sys_reg |= SYS_REG_ENC_RANK(info->rank, channel);
937 sys_reg |= SYS_REG_ENC_COL(info->col, channel);
938 sys_reg |= SYS_REG_ENC_BK(info->bk, channel);
939 sys_reg |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel);
940 sys_reg |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel);
941 sys_reg |= SYS_REG_ENC_BW(info->bw, channel);
942 sys_reg |= SYS_REG_ENC_DBW(info->dbw, channel);
943
944 dram_cfg_rbc(channel, sdram_params);
945 }
946 write32(&rk3288_pmu->sys_reg[2], sys_reg);
947 write32(&rk3288_sgrf->soc_con2,
948 RK_CLRSETBITS(0x1F, sdram_params->stride));
949 }
950
951 void sdram_init(const struct rk3288_sdram_params *sdram_params)
952 {
953 int channel;
954 int zqcr;
955 printk(BIOS_INFO, "Starting SDRAM initialization...\n");
956
957 if ((sdram_params->dramtype == DDR3
958 && sdram_params->ddr_freq > 800*MHz)
959 || (sdram_params->dramtype == LPDDR3
960 && sdram_params->ddr_freq > 533*MHz))
961 die("SDRAM frequency is to high!");
962
963 rkclk_configure_ddr(sdram_params->ddr_freq);
964
965 for (channel = 0; channel < 2; channel++) {
966 struct rk3288_ddr_pctl_regs *ddr_pctl_regs =
967 rk3288_ddr_pctl[channel];
968 struct rk3288_ddr_publ_regs *ddr_publ_regs =
969 rk3288_ddr_publ[channel];
970
971 phy_pctrl_reset(ddr_publ_regs, channel);
972 phy_dll_bypass_set(ddr_publ_regs, sdram_params->ddr_freq);
973
974 if (channel >= sdram_params->num_channels)
975 continue;
976
977 dfi_cfg(ddr_pctl_regs, sdram_params->dramtype);
978
979 pctl_cfg(channel, sdram_params);
980
981 phy_cfg(channel, sdram_params);
982
983 phy_init(ddr_publ_regs);
984
985 write32(&ddr_pctl_regs->powctl, POWER_UP_START);
986 while (!(read32(&ddr_pctl_regs->powstat) & POWER_UP_DONE))
987 ;
988
989 memory_init(ddr_publ_regs, sdram_params->dramtype);
990 move_to_config_state(ddr_publ_regs, ddr_pctl_regs);
991
992 if (sdram_params->dramtype == LPDDR3) {
993 send_command(ddr_pctl_regs, 3, DESELECT_CMD, 0);
994 udelay(1);
995 send_command(ddr_pctl_regs, 3, PREA_CMD, 0);
996 udelay(1);
997 send_command(ddr_pctl_regs, 3, MRS_CMD, LPDDR2_MA(63) |
998 LPDDR2_OP(0xFC));
999 udelay(1);
1000 send_command(ddr_pctl_regs, 3, MRS_CMD, LPDDR2_MA(1) |
1001 LPDDR2_OP(sdram_params->phy_timing.mr[1]));
1002 udelay(1);
1003 send_command(ddr_pctl_regs, 3, MRS_CMD, LPDDR2_MA(2) |
1004 LPDDR2_OP(sdram_params->phy_timing.mr[2]));
1005 udelay(1);
1006 send_command(ddr_pctl_regs, 3, MRS_CMD, LPDDR2_MA(3) |
1007 LPDDR2_OP(sdram_params->phy_timing.mr[3]));
1008 udelay(1);
1009 }
1010
1011 set_bandwidth_ratio(channel, sdram_params->ch[channel].bw);
1012 /*
1013 * set cs
1014 * CS0, n=1
1015 * CS1, n=2
1016 * CS0 & CS1, n = 3
1017 */
1018 clrsetbits32(&ddr_publ_regs->pgcr, 0xF << 18,
1019 (sdram_params->ch[channel].rank | 1) << 18);
1020 /* DS=40ohm,ODT=155ohm */
1021 zqcr = ZDEN(1) | PU_ONDIE(0x2) | PD_ONDIE(0x2)
1022 | PU_OUTPUT(0x19) | PD_OUTPUT(0x19);
1023 write32(&ddr_publ_regs->zq1cr[0], zqcr);
1024 write32(&ddr_publ_regs->zq0cr[0], zqcr);
1025
1026 if (sdram_params->dramtype == LPDDR3) {
1027 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
1028 udelay(10);
1029 send_command(ddr_pctl_regs,
1030 (sdram_params->ch[channel].rank | 1),
1031 MRS_CMD, LPDDR2_MA(11) | (sdram_params->odt ?
1032 LPDDR2_OP(0x3) : LPDDR2_OP(0x0)));
1033 if (channel == 0) {
1034 write32(&ddr_pctl_regs->mrrcfg0, 0);
1035 send_command(ddr_pctl_regs, 1, MRR_CMD,
1036 LPDDR2_MA(0x8));
1037 /* S8 */
1038 if ((read32(&ddr_pctl_regs->mrrstat0) & 0x3)
1039 != 3)
1040 die("SDRAM initialization failed!");
1041 }
1042 }
1043
1044 if (-1 == data_training(channel, sdram_params)) {
1045 if (sdram_params->dramtype == LPDDR3) {
1046 rkclk_ddr_phy_ctl_reset(channel, 1);
1047 udelay(10);
1048 rkclk_ddr_phy_ctl_reset(channel, 0);
1049 udelay(10);
1050 }
1051 die("SDRAM initialization failed!");
1052 }
1053
1054 if (sdram_params->dramtype == LPDDR3) {
1055 u32 i;
1056 write32(&ddr_pctl_regs->mrrcfg0, 0);
1057 for (i = 0; i < 17; i++)
1058 send_command(ddr_pctl_regs, 1, MRR_CMD,
1059 LPDDR2_MA(i));
1060 }
1061 move_to_access_state(channel);
1062 }
1063 dram_all_config(sdram_params);
1064 printk(BIOS_INFO, "Finish SDRAM initialization...\n");
1065 }
1066
1067 size_t sdram_size_mb(void)
1068 {
1069 u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
1070 size_t chipsize_mb = 0;
1071 static size_t size_mb = 0;
1072 u32 ch;
1073
1074 if (!size_mb) {
1075 u32 sys_reg = read32(&rk3288_pmu->sys_reg[2]);
1076 u32 ch_num = SYS_REG_DEC_NUM_CH(sys_reg);
1077
1078 for (ch = 0; ch < ch_num; ch++) {
1079 rank = SYS_REG_DEC_RANK(sys_reg, ch);
1080 col = SYS_REG_DEC_COL(sys_reg, ch);
1081 bk = SYS_REG_DEC_BK(sys_reg, ch);
1082 cs0_row = SYS_REG_DEC_CS0_ROW(sys_reg, ch);
1083 cs1_row = SYS_REG_DEC_CS1_ROW(sys_reg, ch);
1084 bw = SYS_REG_DEC_BW(sys_reg, ch);
1085 row_3_4 = SYS_REG_DEC_ROW_3_4(sys_reg, ch);
1086
1087 chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
1088
1089 if (rank > 1)
1090 chipsize_mb += chipsize_mb >>
1091 (cs0_row - cs1_row);
1092 if (row_3_4)
1093 chipsize_mb = chipsize_mb * 3 / 4;
1094 size_mb += chipsize_mb;
1095 }
1096
1097 /*
1098 * we use the 0x00000000~0xfeffffff space
1099 * since 0xff000000~0xffffffff is soc register space
1100 * so we reserve it
1101 */
1102 size_mb = MIN(size_mb, 0xff000000/MiB);
1103 }
1104
1105 return size_mb;
1106 }
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