src/soc/samsung/exynos5250/clock_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* Clock setup for SMDK5250 board based on EXYNOS5 */
   4
   5 #include <device/mmio.h>
   6 #include <soc/clk.h>
   7 #include <soc/dp.h>
   8 #include <soc/setup.h>
   9
  10 void system_clock_init(struct mem_timings *mem,
  11                 struct arm_clk_ratios *arm_clk_ratio)
  12 {
  13         u32 val, tmp;
  14
  15         /* Turn on the MCT as early as possible. */
  16         exynos_mct->g_tcon |= (1 << 8);
  17
  18         clrbits32(&exynos_clock->src_cpu, MUX_APLL_SEL_MASK);
  19         do {
  20                 val = read32(&exynos_clock->mux_stat_cpu);
  21         } while ((val | MUX_APLL_SEL_MASK) != val);
  22
  23         clrbits32(&exynos_clock->src_core1, MUX_MPLL_SEL_MASK);
  24         do {
  25                 val = read32(&exynos_clock->mux_stat_core1);
  26         } while ((val | MUX_MPLL_SEL_MASK) != val);
  27
  28         clrbits32(&exynos_clock->src_top2, MUX_CPLL_SEL_MASK);
  29         clrbits32(&exynos_clock->src_top2, MUX_EPLL_SEL_MASK);
  30         clrbits32(&exynos_clock->src_top2, MUX_VPLL_SEL_MASK);
  31         clrbits32(&exynos_clock->src_top2, MUX_GPLL_SEL_MASK);
  32         tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
  33                 | MUX_GPLL_SEL_MASK;
  34         do {
  35                 val = read32(&exynos_clock->mux_stat_top2);
  36         } while ((val | tmp) != val);
  37
  38         clrbits32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK);
  39         do {
  40                 val = read32(&exynos_clock->mux_stat_cdrex);
  41         } while ((val | MUX_BPLL_SEL_MASK) != val);
  42
  43         /* PLL locktime */
  44         write32(&exynos_clock->apll_lock, APLL_LOCK_VAL);
  45
  46         write32(&exynos_clock->mpll_lock, MPLL_LOCK_VAL);
  47
  48         write32(&exynos_clock->bpll_lock, BPLL_LOCK_VAL);
  49
  50         write32(&exynos_clock->cpll_lock, CPLL_LOCK_VAL);
  51
  52         write32(&exynos_clock->gpll_lock, GPLL_LOCK_VAL);
  53
  54         write32(&exynos_clock->epll_lock, EPLL_LOCK_VAL);
  55
  56         write32(&exynos_clock->vpll_lock, VPLL_LOCK_VAL);
  57
  58         write32(&exynos_clock->pll_div2_sel, CLK_REG_DISABLE);
  59
  60         write32(&exynos_clock->src_cpu, MUX_HPM_SEL_MASK);
  61         do {
  62                 val = read32(&exynos_clock->mux_stat_cpu);
  63         } while ((val | HPM_SEL_SCLK_MPLL) != val);
  64
  65         val = arm_clk_ratio->arm2_ratio << 28
  66                 | arm_clk_ratio->apll_ratio << 24
  67                 | arm_clk_ratio->pclk_dbg_ratio << 20
  68                 | arm_clk_ratio->atb_ratio << 16
  69                 | arm_clk_ratio->periph_ratio << 12
  70                 | arm_clk_ratio->acp_ratio << 8
  71                 | arm_clk_ratio->cpud_ratio << 4
  72                 | arm_clk_ratio->arm_ratio;
  73         write32(&exynos_clock->div_cpu0, val);
  74         do {
  75                 val = read32(&exynos_clock->div_stat_cpu0);
  76         } while (0 != val);
  77
  78         write32(&exynos_clock->div_cpu1, CLK_DIV_CPU1_VAL);
  79         do {
  80                 val = read32(&exynos_clock->div_stat_cpu1);
  81         } while (0 != val);
  82
  83         /* switch A15 clock source to OSC clock before changing APLL */
  84         clrbits32(&exynos_clock->src_cpu, APLL_FOUT);
  85
  86         /* Set APLL */
  87         write32(&exynos_clock->apll_con1, APLL_CON1_VAL);
  88         val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
  89                         arm_clk_ratio->apll_sdiv);
  90         write32(&exynos_clock->apll_con0, val);
  91         while ((read32(&exynos_clock->apll_con0) & APLL_CON0_LOCKED) == 0)
  92                 ;
  93
  94         /* now it is safe to switch to APLL */
  95         setbits32(&exynos_clock->src_cpu, APLL_FOUT);
  96
  97         /* Set MPLL */
  98         write32(&exynos_clock->mpll_con1, MPLL_CON1_VAL);
  99         val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
 100         write32(&exynos_clock->mpll_con0, val);
 101         while ((read32(&exynos_clock->mpll_con0) & MPLL_CON0_LOCKED) == 0)
 102                 ;
 103
 104         /*
 105          * Configure MUX_MPLL_FOUT to choose the direct clock source
 106          * path and avoid the fixed DIV/2 block to save power
 107          */
 108         setbits32(&exynos_clock->pll_div2_sel, MUX_MPLL_FOUT_SEL);
 109
 110         /* Set BPLL */
 111         if (mem->use_bpll) {
 112                 write32(&exynos_clock->bpll_con1, BPLL_CON1_VAL);
 113                 val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
 114                 write32(&exynos_clock->bpll_con0, val);
 115                 while ((read32(&exynos_clock->bpll_con0) & BPLL_CON0_LOCKED) == 0)
 116                         ;
 117
 118                 setbits32(&exynos_clock->pll_div2_sel, MUX_BPLL_FOUT_SEL);
 119         }
 120
 121         /* Set CPLL */
 122         write32(&exynos_clock->cpll_con1, CPLL_CON1_VAL);
 123         val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
 124         write32(&exynos_clock->cpll_con0, val);
 125         while ((read32(&exynos_clock->cpll_con0) & CPLL_CON0_LOCKED) == 0)
 126                 ;
 127
 128         /* Set GPLL */
 129         write32(&exynos_clock->gpll_con1, GPLL_CON1_VAL);
 130         val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
 131         write32(&exynos_clock->gpll_con0, val);
 132         while ((read32(&exynos_clock->gpll_con0) & GPLL_CON0_LOCKED) == 0)
 133                 ;
 134
 135         /* Set EPLL */
 136         write32(&exynos_clock->epll_con2, EPLL_CON2_VAL);
 137         write32(&exynos_clock->epll_con1, EPLL_CON1_VAL);
 138         val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
 139         write32(&exynos_clock->epll_con0, val);
 140         while ((read32(&exynos_clock->epll_con0) & EPLL_CON0_LOCKED) == 0)
 141                 ;
 142
 143         /* Set VPLL */
 144         write32(&exynos_clock->vpll_con2, VPLL_CON2_VAL);
 145         write32(&exynos_clock->vpll_con1, VPLL_CON1_VAL);
 146         val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
 147         write32(&exynos_clock->vpll_con0, val);
 148         while ((read32(&exynos_clock->vpll_con0) & VPLL_CON0_LOCKED) == 0)
 149                 ;
 150
 151         write32(&exynos_clock->src_core0, CLK_SRC_CORE0_VAL);
 152         write32(&exynos_clock->div_core0, CLK_DIV_CORE0_VAL);
 153         while (read32(&exynos_clock->div_stat_core0) != 0)
 154                 ;
 155
 156         write32(&exynos_clock->div_core1, CLK_DIV_CORE1_VAL);
 157         while (read32(&exynos_clock->div_stat_core1) != 0)
 158                 ;
 159
 160         write32(&exynos_clock->div_sysrgt, CLK_DIV_SYSRGT_VAL);
 161         while (read32(&exynos_clock->div_stat_sysrgt) != 0)
 162                 ;
 163
 164         write32(&exynos_clock->div_acp, CLK_DIV_ACP_VAL);
 165         while (read32(&exynos_clock->div_stat_acp) != 0)
 166                 ;
 167
 168         write32(&exynos_clock->div_syslft, CLK_DIV_SYSLFT_VAL);
 169         while (read32(&exynos_clock->div_stat_syslft) != 0)
 170                 ;
 171
 172         write32(&exynos_clock->src_top0, CLK_SRC_TOP0_VAL);
 173         write32(&exynos_clock->src_top1, CLK_SRC_TOP1_VAL);
 174         write32(&exynos_clock->src_top2, TOP2_VAL);
 175         write32(&exynos_clock->src_top3, CLK_SRC_TOP3_VAL);
 176
 177         write32(&exynos_clock->div_top0, CLK_DIV_TOP0_VAL);
 178         while (read32(&exynos_clock->div_stat_top0))
 179                 ;
 180
 181         write32(&exynos_clock->div_top1, CLK_DIV_TOP1_VAL);
 182         while (read32(&exynos_clock->div_stat_top1))
 183                 ;
 184
 185         write32(&exynos_clock->src_lex, CLK_SRC_LEX_VAL);
 186         while (1) {
 187                 val = read32(&exynos_clock->mux_stat_lex);
 188                 if (val == (val | 1))
 189                         break;
 190         }
 191
 192         write32(&exynos_clock->div_lex, CLK_DIV_LEX_VAL);
 193         while (read32(&exynos_clock->div_stat_lex))
 194                 ;
 195
 196         write32(&exynos_clock->div_r0x, CLK_DIV_R0X_VAL);
 197         while (read32(&exynos_clock->div_stat_r0x))
 198                 ;
 199
 200         write32(&exynos_clock->div_r0x, CLK_DIV_R0X_VAL);
 201         while (read32(&exynos_clock->div_stat_r0x))
 202                 ;
 203
 204         write32(&exynos_clock->div_r1x, CLK_DIV_R1X_VAL);
 205         while (read32(&exynos_clock->div_stat_r1x))
 206                 ;
 207
 208         if (mem->use_bpll) {
 209                 write32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK |
 210                         MUX_MCLK_CDREX_SEL | MUX_MCLK_DPHY_SEL);
 211         } else {
 212                 write32(&exynos_clock->src_cdrex, CLK_REG_DISABLE);
 213         }
 214
 215         write32(&exynos_clock->div_cdrex, CLK_DIV_CDREX_VAL);
 216         while (read32(&exynos_clock->div_stat_cdrex))
 217                 ;
 218
 219         val = read32(&exynos_clock->src_cpu);
 220         val |= CLK_SRC_CPU_VAL;
 221         write32(&exynos_clock->src_cpu, val);
 222
 223         val = read32(&exynos_clock->src_top2);
 224         val |= CLK_SRC_TOP2_VAL;
 225         write32(&exynos_clock->src_top2, val);
 226
 227         val = read32(&exynos_clock->src_core1);
 228         val |= CLK_SRC_CORE1_VAL;
 229         write32(&exynos_clock->src_core1, val);
 230
 231         write32(&exynos_clock->src_fsys, CLK_SRC_FSYS0_VAL);
 232         write32(&exynos_clock->div_fsys0, CLK_DIV_FSYS0_VAL);
 233         while (read32(&exynos_clock->div_stat_fsys0))
 234                 ;
 235
 236         write32(&exynos_clock->clkout_cmu_cpu, CLK_REG_DISABLE);
 237         write32(&exynos_clock->clkout_cmu_core, CLK_REG_DISABLE);
 238         write32(&exynos_clock->clkout_cmu_acp, CLK_REG_DISABLE);
 239         write32(&exynos_clock->clkout_cmu_top, CLK_REG_DISABLE);
 240         write32(&exynos_clock->clkout_cmu_lex, CLK_REG_DISABLE);
 241         write32(&exynos_clock->clkout_cmu_r0x, CLK_REG_DISABLE);
 242         write32(&exynos_clock->clkout_cmu_r1x, CLK_REG_DISABLE);
 243         write32(&exynos_clock->clkout_cmu_cdrex, CLK_REG_DISABLE);
 244
 245         write32(&exynos_clock->src_peric0, CLK_SRC_PERIC0_VAL);
 246         write32(&exynos_clock->div_peric0, CLK_DIV_PERIC0_VAL);
 247
 248         write32(&exynos_clock->src_peric1, CLK_SRC_PERIC1_VAL);
 249         write32(&exynos_clock->div_peric1, CLK_DIV_PERIC1_VAL);
 250         write32(&exynos_clock->div_peric2, CLK_DIV_PERIC2_VAL);
 251         write32(&exynos_clock->sclk_src_isp, SCLK_SRC_ISP_VAL);
 252         write32(&exynos_clock->sclk_div_isp, SCLK_DIV_ISP_VAL);
 253         write32(&exynos_clock->div_isp0, CLK_DIV_ISP0_VAL);
 254         write32(&exynos_clock->div_isp1, CLK_DIV_ISP1_VAL);
 255         write32(&exynos_clock->div_isp2, CLK_DIV_ISP2_VAL);
 256
 257         /* FIMD1 SRC CLK SELECTION */
 258         write32(&exynos_clock->src_disp1_0, CLK_SRC_DISP1_0_VAL);
 259
 260         val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
 261                 | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
 262                 | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
 263                 | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
 264         write32(&exynos_clock->div_fsys2, val);
 265 }
 266
 267 void clock_gate(void)
 268 {
 269         /* CLK_GATE_IP_SYSRGT */
 270         clrbits32(&exynos_clock->gate_ip_sysrgt, CLK_C2C_MASK);
 271
 272         /* CLK_GATE_IP_ACP */
 273         clrbits32(&exynos_clock->gate_ip_acp, CLK_SMMUG2D_MASK |
 274                                               CLK_SMMUSSS_MASK |
 275                                               CLK_SMMUMDMA_MASK |
 276                                               CLK_ID_REMAPPER_MASK |
 277                                               CLK_G2D_MASK |
 278                                               CLK_SSS_MASK |
 279                                               CLK_MDMA_MASK |
 280                                               CLK_SECJTAG_MASK);
 281
 282         /* CLK_GATE_BUS_SYSLFT */
 283         clrbits32(&exynos_clock->gate_bus_syslft, CLK_EFCLK_MASK);
 284
 285         /* CLK_GATE_IP_ISP0 */
 286         clrbits32(&exynos_clock->gate_ip_isp0, CLK_UART_ISP_MASK |
 287                                                CLK_WDT_ISP_MASK |
 288                                                CLK_PWM_ISP_MASK |
 289                                                CLK_MTCADC_ISP_MASK |
 290                                                CLK_I2C1_ISP_MASK |
 291                                                CLK_I2C0_ISP_MASK |
 292                                                CLK_MPWM_ISP_MASK |
 293                                                CLK_MCUCTL_ISP_MASK |
 294                                                CLK_INT_COMB_ISP_MASK |
 295                                                CLK_SMMU_MCUISP_MASK |
 296                                                CLK_SMMU_SCALERP_MASK |
 297                                                CLK_SMMU_SCALERC_MASK |
 298                                                CLK_SMMU_FD_MASK |
 299                                                CLK_SMMU_DRC_MASK |
 300                                                CLK_SMMU_ISP_MASK |
 301                                                CLK_GICISP_MASK |
 302                                                CLK_ARM9S_MASK |
 303                                                CLK_MCUISP_MASK |
 304                                                CLK_SCALERP_MASK |
 305                                                CLK_SCALERC_MASK |
 306                                                CLK_FD_MASK |
 307                                                CLK_DRC_MASK |
 308                                                CLK_ISP_MASK);
 309
 310         /* CLK_GATE_IP_ISP1 */
 311         clrbits32(&exynos_clock->gate_ip_isp1, CLK_SPI1_ISP_MASK |
 312                                                CLK_SPI0_ISP_MASK |
 313                                                CLK_SMMU3DNR_MASK |
 314                                                CLK_SMMUDIS1_MASK |
 315                                                CLK_SMMUDIS0_MASK |
 316                                                CLK_SMMUODC_MASK |
 317                                                CLK_3DNR_MASK |
 318                                                CLK_DIS_MASK |
 319                                                CLK_ODC_MASK);
 320
 321         /* CLK_GATE_SCLK_ISP */
 322         clrbits32(&exynos_clock->gate_sclk_isp, SCLK_MPWM_ISP_MASK);
 323
 324         /* CLK_GATE_IP_GSCL */
 325         clrbits32(&exynos_clock->gate_ip_gscl, CLK_SMMUFIMC_LITE2_MASK |
 326                                                CLK_SMMUFIMC_LITE1_MASK |
 327                                                CLK_SMMUFIMC_LITE0_MASK |
 328                                                CLK_SMMUGSCL3_MASK |
 329                                                CLK_SMMUGSCL2_MASK |
 330                                                CLK_SMMUGSCL1_MASK |
 331                                                CLK_SMMUGSCL0_MASK |
 332                                                CLK_GSCL_WRAP_B_MASK |
 333                                                CLK_GSCL_WRAP_A_MASK |
 334                                                CLK_CAMIF_TOP_MASK |
 335                                                CLK_GSCL3_MASK |
 336                                                CLK_GSCL2_MASK |
 337                                                CLK_GSCL1_MASK |
 338                                                CLK_GSCL0_MASK);
 339
 340         /* CLK_GATE_IP_DISP1 */
 341         clrbits32(&exynos_clock->gate_ip_disp1, CLK_SMMUTVX_MASK |
 342                                                 CLK_ASYNCTVX_MASK |
 343                                                 CLK_HDMI_MASK |
 344                                                 CLK_MIXER_MASK |
 345                                                 CLK_DSIM1_MASK);
 346
 347         /* CLK_GATE_IP_MFC */
 348         clrbits32(&exynos_clock->gate_ip_mfc, CLK_SMMUMFCR_MASK |
 349                                               CLK_SMMUMFCL_MASK |
 350                                               CLK_MFC_MASK);
 351
 352         /* CLK_GATE_IP_GEN */
 353         clrbits32(&exynos_clock->gate_ip_gen, CLK_SMMUMDMA1_MASK |
 354                                               CLK_SMMUJPEG_MASK |
 355                                               CLK_SMMUROTATOR_MASK |
 356                                               CLK_MDMA1_MASK |
 357                                               CLK_JPEG_MASK |
 358                                               CLK_ROTATOR_MASK);
 359
 360         /* CLK_GATE_IP_FSYS */
 361         clrbits32(&exynos_clock->gate_ip_fsys, CLK_WDT_IOP_MASK |
 362                                                CLK_SMMUMCU_IOP_MASK |
 363                                                CLK_SATA_PHY_I2C_MASK |
 364                                                CLK_SATA_PHY_CTRL_MASK |
 365                                                CLK_MCUCTL_MASK |
 366                                                CLK_NFCON_MASK |
 367                                                CLK_SMMURTIC_MASK |
 368                                                CLK_RTIC_MASK |
 369                                                CLK_MIPI_HSI_MASK |
 370                                                CLK_USBOTG_MASK |
 371                                                CLK_SATA_MASK |
 372                                                CLK_PDMA1_MASK |
 373                                                CLK_PDMA0_MASK |
 374                                                CLK_MCU_IOP_MASK);
 375
 376         /* CLK_GATE_IP_PERIC */
 377         clrbits32(&exynos_clock->gate_ip_peric, CLK_HS_I2C3_MASK |
 378                                                 CLK_HS_I2C2_MASK |
 379                                                 CLK_HS_I2C1_MASK |
 380                                                 CLK_HS_I2C0_MASK |
 381                                                 CLK_AC97_MASK |
 382                                                 CLK_SPDIF_MASK |
 383                                                 CLK_PCM2_MASK |
 384                                                 CLK_PCM1_MASK |
 385                                                 CLK_I2S2_MASK |
 386                                                 CLK_SPI2_MASK |
 387                                                 CLK_SPI0_MASK);
 388
 389         /*
 390          * CLK_GATE_IP_PERIS
 391          * Note: Keep CHIPID_APBIF ungated to ensure reading the product ID
 392          * register (PRO_ID) works correctly when the OS kernel determines
 393          * which chip it is running on.
 394          */
 395         clrbits32(&exynos_clock->gate_ip_peris, CLK_RTC_MASK |
 396                                                 CLK_TZPC9_MASK |
 397                                                 CLK_TZPC8_MASK |
 398                                                 CLK_TZPC7_MASK |
 399                                                 CLK_TZPC6_MASK |
 400                                                 CLK_TZPC5_MASK |
 401                                                 CLK_TZPC4_MASK |
 402                                                 CLK_TZPC3_MASK |
 403                                                 CLK_TZPC2_MASK |
 404                                                 CLK_TZPC1_MASK |
 405                                                 CLK_TZPC0_MASK);
 406
 407         /* CLK_GATE_BLOCK */
 408         clrbits32(&exynos_clock->gate_block, CLK_ACP_MASK);
 409
 410         /* CLK_GATE_IP_CDREX */
 411         clrbits32(&exynos_clock->gate_ip_cdrex, CLK_DPHY0_MASK |
 412                                                 CLK_DPHY1_MASK |
 413                                                 CLK_TZASC_DRBXR_MASK);
 414 }
 415
 416 void clock_init_dp_clock(void)
 417 {
 418         /* DP clock enable */
 419         setbits32(&exynos_clock->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
 420
 421         /* We run DP at 267 Mhz */
 422         setbits32(&exynos_clock->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
 423 }