src/soc/samsung/exynos5250/power.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* Power setup code for EXYNOS5 */
   4
   5 #include <device/mmio.h>
   6 #include <halt.h>
   7 #include <reset.h>
   8 #include <soc/dmc.h>
   9 #include <soc/power.h>
  10 #include <soc/setup.h>
  11
  12 /* Set the PS-Hold drive value */
  13 static void ps_hold_setup(void)
  14 {
  15         /* Set PS-Hold high */
  16         setbits32(&exynos_power->ps_hold_ctrl,
  17                      POWER_PS_HOLD_CONTROL_DATA_HIGH);
  18 }
  19
  20 void power_reset(void)
  21 {
  22         /* Clear inform1 so there's no change we think we've got a wake reset */
  23         exynos_power->inform1 = 0;
  24
  25         setbits32(&exynos_power->sw_reset, 1);
  26 }
  27
  28 void do_board_reset(void)
  29 {
  30         power_reset();
  31 }
  32
  33 /* This function never returns */
  34 void power_shutdown(void)
  35 {
  36         clrbits32(&exynos_power->ps_hold_ctrl,
  37                      POWER_PS_HOLD_CONTROL_DATA_HIGH);
  38
  39         halt();
  40 }
  41
  42 void power_enable_dp_phy(void)
  43 {
  44         setbits32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE);
  45 }
  46
  47 void power_enable_hw_thermal_trip(void)
  48 {
  49         /* Enable HW thermal trip */
  50         setbits32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP);
  51 }
  52
  53 uint32_t power_read_reset_status(void)
  54 {
  55         return exynos_power->inform1;
  56 }
  57
  58 void power_exit_wakeup(void)
  59 {
  60         typedef void (*resume_func)(void);
  61
  62         ((resume_func)exynos_power->inform0)();
  63 }
  64
  65 int power_init(void)
  66 {
  67         ps_hold_setup();
  68         return 0;
  69 }
  70
  71 void power_enable_xclkout(void)
  72 {
  73         /* use xxti for xclk out */
  74         clrsetbits32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
  75                         PMU_DEBUG_XXTI);
  76 }
  77
  78 void power_release_uart_retention(void)
  79 {
  80         write32(&exynos_power->padret_uart_opt, 1 << 28);
  81 }