src/vendorcode/google/chromeos/chromeos.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef __CHROMEOS_H__
   4 #define __CHROMEOS_H__
   5
   6 #include <stddef.h>
   7 #include <stdint.h>
   8 #include <types.h>
   9
  10 #if CONFIG(CHROMEOS)
  11 /* functions implemented in watchdog.c */
  12 void mark_watchdog_tombstone(void);
  13 void reboot_from_watchdog(void);
  14 bool reset_watchdog_tombstone(void);
  15 #else
  16 static inline void mark_watchdog_tombstone(void) { return; }
  17 static inline void reboot_from_watchdog(void) { return; }
  18 #endif /* CONFIG_CHROMEOS */
  19
  20 #define UNDEFINED_FACTORY_CONFIG        ~((uint64_t)0)
  21
  22 /**
  23  * Perform any platform specific actions required prior to resetting the Cr50.
  24  * Defined as weak function in cr50_enable_update.c
  25  */
  26 void mainboard_prepare_cr50_reset(void);
  27
  28 void cbmem_add_vpd_calibration_data(void);
  29 void chromeos_set_me_hash(u32*, int);
  30 void chromeos_set_ramoops(void *ram_oops, size_t size);
  31 /*
  32  * The factory config space is a one-time programmable info page.
  33  * For the unprovisioned one, the read will be 0x0.
  34  * Return "UNDEFINED_FACTORY_CONFIG" in case of error.
  35  */
  36 uint64_t chromeos_get_factory_config(void);
  37 /*
  38  * Determines whether a ChromeOS device is branded as a Chromebook-Plus
  39  * based on specific bit flags:
  40  *
  41  * - Bit 4 (0x10): Indicates whether the device chassis has the
  42  *                 "chromebook-plus" branding.
  43  * - Bits 3-0 (0x1): Must be 0x1 to signify compliance with Chromebook-Plus
  44  *                   hardware specifications.
  45  *
  46  * To be considered a Chromebook-Plus, both of these conditions need to be met.
  47  */
  48 bool chromeos_device_branded_plus_hard(void);
  49
  50 /*
  51  * Determines whether a ChromeOS device is soft-branded as a Chromebook-Plus
  52  * after meeting below conditions:
  53  *
  54  * - Device is compliant to the Chromebook-Plus Hardware Specification.
  55  * - Business decision makes this device qualified as Chromebook-Plus.
  56  *
  57  * To be considered a soft-branded Chromebook-Plus, both of these conditions need to be met.
  58  */
  59 bool chromeos_device_branded_plus_soft(void);
  60
  61 /*
  62  * Declaration for mainboards to use to generate ACPI-specific ChromeOS needs.
  63  */
  64 void chromeos_acpi_gpio_generate(void);
  65
  66 enum {
  67         CROS_GPIO_REC = 1, /* Recovery */
  68         CROS_GPIO_DEPRECATED_DEV = 2, /* Developer;
  69                                        * deprecated (chromium:942901) */
  70         CROS_GPIO_WP = 3, /* Write Protect */
  71         CROS_GPIO_PE = 4, /* Phase enforcement for final product */
  72
  73         CROS_GPIO_ACTIVE_LOW = 0,
  74         CROS_GPIO_ACTIVE_HIGH = 1,
  75
  76         CROS_GPIO_VIRTUAL = -1,
  77 };
  78
  79 struct cros_gpio {
  80         int type;
  81         int polarity;
  82         int gpio_num;
  83         const char *device;
  84 };
  85
  86 #define CROS_GPIO_INITIALIZER(typ, pol, num, dev) \
  87         {                               \
  88                 .type = (typ),          \
  89                 .polarity = (pol),      \
  90                 .gpio_num = (num),      \
  91                 .device = (dev),        \
  92         }
  93
  94 #define CROS_GPIO_REC_INITIALIZER(pol, num, dev) \
  95         CROS_GPIO_INITIALIZER(CROS_GPIO_REC, pol, num, dev)
  96
  97 #define CROS_GPIO_REC_AL(num, dev) \
  98         CROS_GPIO_REC_INITIALIZER(CROS_GPIO_ACTIVE_LOW, num, dev)
  99
 100 #define CROS_GPIO_REC_AH(num, dev) \
 101         CROS_GPIO_REC_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev)
 102
 103 #define CROS_GPIO_WP_INITIALIZER(pol, num, dev) \
 104         CROS_GPIO_INITIALIZER(CROS_GPIO_WP, pol, num, dev)
 105
 106 #define CROS_GPIO_WP_AL(num, dev) \
 107         CROS_GPIO_WP_INITIALIZER(CROS_GPIO_ACTIVE_LOW, num, dev)
 108
 109 #define CROS_GPIO_WP_AH(num, dev) \
 110         CROS_GPIO_WP_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev)
 111
 112 #define CROS_GPIO_PE_INITIALIZER(pol, num, dev) \
 113         CROS_GPIO_INITIALIZER(CROS_GPIO_PE, pol, num, dev)
 114
 115 #define CROS_GPIO_PE_AL(num, dev) \
 116         CROS_GPIO_PE_INITIALIZER(CROS_GPIO_ACTIVE_LOW, num, dev)
 117
 118 #define CROS_GPIO_PE_AH(num, dev) \
 119         CROS_GPIO_PE_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev)
 120
 121 struct cros_gpio_pack {
 122         int count;
 123         const struct cros_gpio *gpios;
 124 };
 125
 126 extern const struct cros_gpio_pack variant_cros_gpio;
 127
 128 #define DECLARE_NO_CROS_GPIOS() \
 129         const struct cros_gpio_pack variant_cros_gpio = \
 130                 { .count = 0, .gpios = NULL }
 131
 132 #define DECLARE_CROS_GPIOS(x) \
 133         const struct cros_gpio_pack variant_cros_gpio = \
 134                 { .count = ARRAY_SIZE(x), .gpios = x }
 135
 136 #define DECLARE_WEAK_CROS_GPIOS(x) \
 137         const struct cros_gpio_pack __weak variant_cros_gpio = \
 138                 { .count = ARRAY_SIZE(x), .gpios = x }
 139
 140 #endif /* __CHROMEOS_H__ */