src/vendorcode/mediatek/mt8192/include/dramc_register.h

   1 /* SPDX-License-Identifier: BSD-3-Clause */
   2
   3 #ifndef _A60868_REGISTER_H_
   4 #define _A60868_REGISTER_H_
   5
   6 #include "dramc_pi_api.h"
   7
   8 #define POS_BANK_NUM 16  // SW Virtual base address position
   9
  10 #if (fcFOR_CHIP_ID == fcMargaux)
  11 #include "Margaux_Register_DDRPHY_MD32.h"
  12 #include "Margaux_Register_DDRPHY_NAO.h"
  13 #include "Margaux_Register_DDRPHY_AO.h"
  14 #include "Margaux_Register_DRAMC_AO.h"
  15 #include "Margaux_Register_DRAMC_NAO.h"
  16 #else
  17 #include "Register_DDRPHY_MD32.h"
  18 #include "Register_DDRPHY_NAO.h"
  19 #include "Register_DDRPHY_AO.h"
  20 #include "Register_DRAMC_AO.h"
  21 #include "Register_DRAMC_NAO.h"
  22 #include "Register_SYSTEM.h"
  23 #endif
  24
  25 // SW Virtual base address
  26 #define Channel_A_DRAMC_NAO_BASE_VIRTUAL        0x40000
  27 #define Channel_B_DRAMC_NAO_BASE_VIRTUAL        0x50000
  28 #define Channel_A_DRAMC_AO_BASE_VIRTUAL         0x60000
  29 #define Channel_B_DRAMC_AO_BASE_VIRTUAL         0x70000
  30 #define Channel_A_DDRPHY_NAO_BASE_VIRTUAL       0x80000
  31 #define Channel_B_DDRPHY_NAO_BASE_VIRTUAL       0x90000
  32 #define Channel_A_DDRPHY_AO_BASE_VIRTUAL        0xa0000
  33 #define Channel_B_DDRPHY_AO_BASE_VIRTUAL        0xb0000
  34 #define Channel_A_DDRPHY_DPM_BASE_VIRTUAL       0xc0000
  35 #define MAX_BASE_VIRTUAL                        0xd0000
  36
  37 #define DRAMC_WBR 0x100010B4
  38 #if (CHANNEL_NUM==4)
  39 #define DRAMC_BROADCAST_ON 0x27f7f  //4CH
  40 #else
  41 #define DRAMC_BROADCAST_ON 0x7f  //2CH
  42 #endif
  43 #define DRAMC_BROADCAST_OFF 0x0
  44
  45 //Definitions indicating DRAMC, DDRPHY register shuffle offset
  46 #define SHU_GRP_DRAMC_OFFSET      0x700
  47 #define SHU_GRP_DDRPHY_OFFSET     0x700
  48
  49 #define DRAMC_REG_AO_SHU_OFFSET                 (0x700)
  50 #define DRAMC_REG_AO_RANK_OFFSET                (0x200)
  51 #define DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR (DRAMC_REG_RK_TEST2_A1 - DRAMC_AO_BASE_ADDRESS) // 0x0500
  52 #define DRAMC_REG_AO_RANK0_WO_SHUFFLE_END_ADDR  (DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR + DRAMC_REG_AO_RANK_OFFSET)
  53 #define DRAMC_REG_AO_RANK0_W_SHUFFLE0_BASE_ADDR (DRAMC_REG_SHURK_SELPH_DQ0 - DRAMC_AO_BASE_ADDRESS) // 0x1200
  54 #define DRAMC_REG_AO_RANK0_W_SHUFFLE0_END_ADDR  (DRAMC_REG_AO_RANK0_W_SHUFFLE0_BASE_ADDR + DRAMC_REG_AO_RANK_OFFSET)
  55 #define DRAMC_REG_AO_SHUFFLE0_BASE_ADDR         (DRAMC_REG_SHURK_SELPH_DQ0 - DRAMC_AO_BASE_ADDRESS) // 0x1200
  56 #define DRAMC_REG_AO_SHUFFLE0_END_ADDR          (DRAMC_REG_SHU_ACTIM7 - DRAMC_AO_BASE_ADDRESS) // 0x16E8
  57
  58 #define DDRPHY_AO_B0_B1_OFFSET                  (0x180)
  59 #define DDRPHY_AO_SHU_OFFSET                    (0x700)
  60 #define DDRPHY_AO_RANK_OFFSET                   (0x80)
  61 #define DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR    (DDRPHY_REG_RK_B0_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x0060
  62 #define DDRPHY_AO_RANK0_B0_NON_SHU_END_ADDR     (DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
  63 #define DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR    (DDRPHY_REG_RK_B1_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x01E0
  64 #define DDRPHY_AO_RANK0_B1_NON_SHU_END_ADDR     (DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
  65 #define DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR    (DDRPHY_REG_RK_CA_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x0360
  66 #define DDRPHY_AO_RANK0_CA_NON_SHU_END_ADDR     (DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
  67 #define DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR       (DDRPHY_REG_SHU_R0_B0_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x0760
  68 #define DDRPHY_AO_RANK0_B0_SHU0_END_ADDR        (DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
  69 #define DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR       (DDRPHY_REG_SHU_R0_B1_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x08E0
  70 #define DDRPHY_AO_RANK0_B1_SHU0_END_ADDR        (DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
  71 #define DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR       (DDRPHY_REG_SHU_R0_CA_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x0A60
  72 #define DDRPHY_AO_RANK0_CA_SHU0_END_ADDR        (DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
  73 #define DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR     (DDRPHY_REG_MISC_SHU_RK_DQSCTL - DDRPHY_AO_BASE_ADDRESS) // 0x0BE0
  74 #define DDRPHY_AO_RANK0_MISC_SHU0_END_ADDR      (DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
  75 #define DDRPHY_AO_SHUFFLE0_BASE_ADDR            (DDRPHY_REG_SHU_PHYPLL0 - DDRPHY_AO_BASE_ADDRESS) // 0x700
  76 #define DDRPHY_AO_SHUFFLE0_END_ADDR             (DDRPHY_REG_MISC_SHU_CG_CTRL0 - DDRPHY_AO_BASE_ADDRESS) // 0xDA4
  77
  78 #define DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET        (0x20)
  79 #define DDRPHY_NAO_GATING_STATUS_RK_OFFSET              (0x10)
  80 #define DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START   (DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0600
  81 #define DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_END     (DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET)
  82 #define DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_START   (DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0640
  83 #define DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_END     (DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET)
  84 #define DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_START   (DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0680
  85 #define DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_END     (DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET)
  86 #define DDRPHY_NAO_RANK0_GATING_STATUS_START            (DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0420
  87 #define DDRPHY_NAO_RANK0_GATING_STATUS_END              (DDRPHY_NAO_RANK0_GATING_STATUS_START + DDRPHY_NAO_GATING_STATUS_RK_OFFSET)
  88
  89 #define DRAMC_REG_NAO_RANK_OFFSET                (0x200)
  90 #define DRAMC_REG_NAO_RANK0_ROW_OFFSET_BASE_ADDR (DRAMC_REG_MR_BACKUP_00_RK0_FSP0 - DRAMC_NAO_BASE_ADDRESS) // 0x0900
  91 #define DRAMC_REG_NAO_RANK0_ROW_OFFSET_END_ADDR  (DRAMC_REG_NAO_RANK0_ROW_OFFSET_BASE_ADDR + DRAMC_REG_NAO_RANK_OFFSET)
  92
  93 // HW Physical base address
  94 #if defined(__MD32__)
  95 /* MD32 address */
  96 #undef Channel_A_DRAMC_AO_BASE_ADDRESS
  97 #define Channel_A_DRAMC_AO_BASE_ADDRESS         0x300A2000
  98 #undef Channel_B_DRAMC_AO_BASE_ADDRESS
  99 #define Channel_B_DRAMC_AO_BASE_ADDRESS         0x300B2000
 100 #undef Channel_C_DRAMC_AO_BASE_ADDRESS
 101 #define Channel_C_DRAMC_AO_BASE_ADDRESS         0x0
 102 #undef Channel_D_DRAMC_AO_BASE_ADDRESS
 103 #define Channel_D_DRAMC_AO_BASE_ADDRESS         0x0
 104 #undef Channel_A_DRAMC_NAO_BASE_ADDRESS
 105 #define Channel_A_DRAMC_NAO_BASE_ADDRESS        0x300A8000
 106 #undef Channel_B_DRAMC_NAO_BASE_ADDRESS
 107 #define Channel_B_DRAMC_NAO_BASE_ADDRESS        0x300B8000
 108 #undef Channel_C_DRAMC_NAO_BASE_ADDRESS
 109 #define Channel_C_DRAMC_NAO_BASE_ADDRESS        0x0
 110 #undef Channel_D_DRAMC_NAO_BASE_ADDRESS
 111 #define Channel_D_DRAMC_NAO_BASE_ADDRESS        0x0
 112 #undef Channel_A_DDRPHY_AO_BASE_ADDRESS
 113 #define Channel_A_DDRPHY_AO_BASE_ADDRESS        0x300A6000
 114 #undef Channel_B_DDRPHY_AO_BASE_ADDRESS
 115 #define Channel_B_DDRPHY_AO_BASE_ADDRESS        0x300B6000
 116 #undef Channel_C_DDRPHY_AO_BASE_ADDRESS
 117 #define Channel_C_DDRPHY_AO_BASE_ADDRESS        0x0
 118 #undef Channel_D_DDRPHY_AO_BASE_ADDRESS
 119 #define Channel_D_DDRPHY_AO_BASE_ADDRESS        0x0
 120 #undef Channel_A_DDRPHY_NAO_BASE_ADDRESS
 121 #define Channel_A_DDRPHY_NAO_BASE_ADDRESS       0x300AA000
 122 #undef Channel_B_DDRPHY_NAO_BASE_ADDRESS
 123 #define Channel_B_DDRPHY_NAO_BASE_ADDRESS       0x300BA000
 124 #undef Channel_C_DDRPHY_NAO_BASE_ADDRESS
 125 #define Channel_C_DDRPHY_NAO_BASE_ADDRESS       0x0
 126 #undef Channel_D_DDRPHY_NAO_BASE_ADDRESS
 127 #define Channel_D_DDRPHY_NAO_BASE_ADDRESS       0x0
 128 #undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
 129 #define Channel_A_DDRPHY_DPM_BASE_ADDRESS       0x30040000
 130 #elif (FOR_DV_SIMULATION_USED)
 131 #undef Channel_A_DRAMC_AO_BASE_ADDRESS
 132 #define Channel_A_DRAMC_AO_BASE_ADDRESS         0x10000
 133 #undef Channel_B_DRAMC_AO_BASE_ADDRESS
 134 #define Channel_B_DRAMC_AO_BASE_ADDRESS         0x40000
 135 #undef Channel_C_DRAMC_AO_BASE_ADDRESS
 136 #define Channel_C_DRAMC_AO_BASE_ADDRESS         0x0
 137 #undef Channel_D_DRAMC_AO_BASE_ADDRESS
 138 #define Channel_D_DRAMC_AO_BASE_ADDRESS         0x0
 139
 140 #undef Channel_A_DRAMC_NAO_BASE_ADDRESS
 141 #define Channel_A_DRAMC_NAO_BASE_ADDRESS        0x20000
 142 #undef Channel_B_DRAMC_NAO_BASE_ADDRESS
 143 #define Channel_B_DRAMC_NAO_BASE_ADDRESS        0x50000
 144 #undef Channel_C_DRAMC_NAO_BASE_ADDRESS
 145 #define Channel_C_DRAMC_NAO_BASE_ADDRESS         0x0
 146 #undef Channel_D_DRAMC_NAO_BASE_ADDRESS
 147 #define Channel_D_DRAMC_NAO_BASE_ADDRESS         0x0
 148
 149 #undef Channel_A_DDRPHY_AO_BASE_ADDRESS
 150 #define Channel_A_DDRPHY_AO_BASE_ADDRESS        0x30000
 151 #undef Channel_B_DDRPHY_AO_BASE_ADDRESS
 152 #define Channel_B_DDRPHY_AO_BASE_ADDRESS        0x60000
 153 #undef Channel_C_DDRPHY_AO_BASE_ADDRESS
 154 #define Channel_C_DDRPHY_AO_BASE_ADDRESS        0x0
 155 #undef Channel_D_DDRPHY_AO_BASE_ADDRESS
 156 #define Channel_D_DDRPHY_AO_BASE_ADDRESS        0x0
 157
 158 #undef Channel_A_DDRPHY_NAO_BASE_ADDRESS
 159 #define Channel_A_DDRPHY_NAO_BASE_ADDRESS       0x70000
 160 #undef Channel_B_DDRPHY_NAO_BASE_ADDRESS
 161 #define Channel_B_DDRPHY_NAO_BASE_ADDRESS       0x80000
 162 #undef Channel_C_DDRPHY_NAO_BASE_ADDRESS
 163 #define Channel_C_DDRPHY_NAO_BASE_ADDRESS        0x0
 164 #undef Channel_D_DDRPHY_NAO_BASE_ADDRESS
 165 #define Channel_D_DDRPHY_NAO_BASE_ADDRESS        0x0
 166
 167 #undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
 168 #define Channel_A_DDRPHY_DPM_BASE_ADDRESS       0xD0000 //@Darren, 0x90000 + 0x40000 for DV sim
 169 #elif(HAPS_FPFG_A60868 ==0)
 170 #undef Channel_A_DRAMC_AO_BASE_ADDRESS
 171 #define Channel_A_DRAMC_AO_BASE_ADDRESS         0x10230000
 172 #undef Channel_B_DRAMC_AO_BASE_ADDRESS
 173 #define Channel_B_DRAMC_AO_BASE_ADDRESS         0x10240000
 174 #undef Channel_C_DRAMC_AO_BASE_ADDRESS
 175 #define Channel_C_DRAMC_AO_BASE_ADDRESS         0x10250000
 176 #undef Channel_D_DRAMC_AO_BASE_ADDRESS
 177 #define Channel_D_DRAMC_AO_BASE_ADDRESS         0x10260000
 178 #undef Channel_A_DRAMC_NAO_BASE_ADDRESS
 179 #define Channel_A_DRAMC_NAO_BASE_ADDRESS        0x10234000
 180 #undef Channel_B_DRAMC_NAO_BASE_ADDRESS
 181 #define Channel_B_DRAMC_NAO_BASE_ADDRESS        0x10244000
 182 #undef Channel_C_DRAMC_NAO_BASE_ADDRESS
 183 #define Channel_C_DRAMC_NAO_BASE_ADDRESS        0x10254000
 184 #undef Channel_D_DRAMC_NAO_BASE_ADDRESS
 185 #define Channel_D_DRAMC_NAO_BASE_ADDRESS        0x10264000
 186 #undef Channel_A_DDRPHY_AO_BASE_ADDRESS
 187 #define Channel_A_DDRPHY_AO_BASE_ADDRESS        0x10238000
 188 #undef Channel_B_DDRPHY_AO_BASE_ADDRESS
 189 #define Channel_B_DDRPHY_AO_BASE_ADDRESS        0x10248000
 190 #undef Channel_C_DDRPHY_AO_BASE_ADDRESS
 191 #define Channel_C_DDRPHY_AO_BASE_ADDRESS        0x10258000
 192 #undef Channel_D_DDRPHY_AO_BASE_ADDRESS
 193 #define Channel_D_DDRPHY_AO_BASE_ADDRESS        0x10268000
 194 #undef Channel_A_DDRPHY_NAO_BASE_ADDRESS
 195 #define Channel_A_DDRPHY_NAO_BASE_ADDRESS       0x10236000
 196 #undef Channel_B_DDRPHY_NAO_BASE_ADDRESS
 197 #define Channel_B_DDRPHY_NAO_BASE_ADDRESS       0x10246000
 198 #undef Channel_C_DDRPHY_NAO_BASE_ADDRESS
 199 #define Channel_C_DDRPHY_NAO_BASE_ADDRESS       0x10256000
 200 #undef Channel_D_DDRPHY_NAO_BASE_ADDRESS
 201 #define Channel_D_DDRPHY_NAO_BASE_ADDRESS       0x10266000
 202 #undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
 203 #define Channel_A_DDRPHY_DPM_BASE_ADDRESS       0x10940000
 204 #undef Channel_B_DDRPHY_DPM_BASE_ADDRESS
 205 #define Channel_B_DDRPHY_DPM_BASE_ADDRESS       0x10A40000
 206 #else  // A60868 FPGA Base Address
 207 #undef Channel_A_DRAMC_AO_BASE_ADDRESS
 208 #define Channel_A_DRAMC_AO_BASE_ADDRESS         0x40000
 209 #undef Channel_B_DRAMC_AO_BASE_ADDRESS
 210 #define Channel_B_DRAMC_AO_BASE_ADDRESS         0x0
 211 #undef Channel_C_DRAMC_AO_BASE_ADDRESS
 212 #define Channel_C_DRAMC_AO_BASE_ADDRESS         0x0
 213 #undef Channel_D_DRAMC_AO_BASE_ADDRESS
 214 #define Channel_D_DRAMC_AO_BASE_ADDRESS         0x0
 215 #undef Channel_A_DRAMC_NAO_BASE_ADDRESS
 216 #define Channel_A_DRAMC_NAO_BASE_ADDRESS        0x10000
 217 #undef Channel_B_DRAMC_NAO_BASE_ADDRESS
 218 #define Channel_B_DRAMC_NAO_BASE_ADDRESS        0x0
 219 #undef Channel_C_DRAMC_NAO_BASE_ADDRESS
 220 #define Channel_C_DRAMC_NAO_BASE_ADDRESS        0x0
 221 #undef Channel_D_DRAMC_NAO_BASE_ADDRESS
 222 #define Channel_D_DRAMC_NAO_BASE_ADDRESS        0x0
 223 #undef Channel_A_DDRPHY_AO_BASE_ADDRESS
 224 #define Channel_A_DDRPHY_AO_BASE_ADDRESS        0x70000
 225 #undef Channel_B_DDRPHY_AO_BASE_ADDRESS
 226 #define Channel_B_DDRPHY_AO_BASE_ADDRESS        0x0
 227 #undef Channel_C_DDRPHY_AO_BASE_ADDRESS
 228 #define Channel_C_DDRPHY_AO_BASE_ADDRESS        0x0
 229 #undef Channel_D_DDRPHY_AO_BASE_ADDRESS
 230 #define Channel_D_DDRPHY_AO_BASE_ADDRESS        0x0
 231 #undef Channel_A_DDRPHY_NAO_BASE_ADDRESS
 232 #define Channel_A_DDRPHY_NAO_BASE_ADDRESS       0x80000
 233 #undef Channel_B_DDRPHY_NAO_BASE_ADDRESS
 234 #define Channel_B_DDRPHY_NAO_BASE_ADDRESS       0x0
 235 #undef Channel_C_DDRPHY_NAO_BASE_ADDRESS
 236 #define Channel_C_DDRPHY_NAO_BASE_ADDRESS       0x0
 237 #undef Channel_D_DDRPHY_NAO_BASE_ADDRESS
 238 #define Channel_D_DDRPHY_NAO_BASE_ADDRESS       0x0
 239 #undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
 240 #define Channel_A_DDRPHY_DPM_BASE_ADDRESS       0x100000
 241 #undef Channel_B_DDRPHY_DPM_BASE_ADDRESS
 242 #define Channel_B_DDRPHY_DPM_BASE_ADDRESS       0x0
 243 #endif
 244
 245 #define CHK_INCLUDE_LOCAL_HEADER "\n ==> Include local header but not one at DV SERVER\n\n"
 246
 247
 248 #endif // _A60868_REGISTER_H_