src/soc/intel/braswell/Kconfig

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2
   3 config SOC_INTEL_BRASWELL
   4         bool
   5         select ACPI_COMMON_MADT_IOAPIC
   6         select ACPI_COMMON_MADT_LAPIC
   7         select ACPI_INTEL_HARDWARE_SLEEP_VALUES
   8         select ARCH_X86
   9         select BOOT_DEVICE_SUPPORTS_WRITES
  10         select CACHE_MRC_SETTINGS
  11         select SUPPORT_CPU_UCODE_IN_CBFS
  12         select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
  13         select HAVE_SMI_HANDLER
  14         select PCIEXP_ASPM
  15         select PCIEXP_CLK_PM
  16         select PCIEXP_COMMON_CLOCK
  17         select PLATFORM_USES_FSP1_1
  18         select REG_SCRIPT
  19         select RTC
  20         select SOC_INTEL_COMMON
  21         select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
  22         select SOC_INTEL_COMMON_BLOCK
  23         select SOC_INTEL_COMMON_BLOCK_HDA
  24         select SOC_INTEL_COMMON_RESET
  25         select SPI_FLASH
  26         select SSE2
  27         select TSC_MONOTONIC_TIMER
  28         select TSC_SYNC_MFENCE
  29         select UDELAY_TSC
  30         select USE_GENERIC_FSP_CAR_INC
  31         select INTEL_DESCRIPTOR_MODE_CAPABLE
  32         select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT
  33         select HAVE_FSP_GOP
  34         select GENERIC_GPIO_LIB
  35         select INTEL_GMA_ACPI
  36         select INTEL_GMA_SWSMISCI
  37         select CPU_INTEL_COMMON
  38         select SOUTHBRIDGE_INTEL_COMMON_SMBUS
  39         select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
  40         select NO_CBFS_MCACHE
  41         select TCO_SPACE_NOT_YET_SPLIT
  42         help
  43           Braswell M/D part support.
  44
  45 if SOC_INTEL_BRASWELL
  46
  47 config DCACHE_BSP_STACK_SIZE
  48         hex
  49         default 0x2000
  50         help
  51           The amount of anticipated stack usage in CAR by bootblock and
  52           other stages.
  53
  54 config VBOOT
  55         select VBOOT_MUST_REQUEST_DISPLAY
  56         select VBOOT_STARTS_IN_ROMSTAGE
  57
  58 config ECAM_MMCONF_BASE_ADDRESS
  59         default 0xe0000000
  60
  61 config ECAM_MMCONF_BUS_NUMBER
  62         int
  63         default 256
  64
  65 config MAX_CPUS
  66         int
  67         default 4
  68
  69 config SMM_TSEG_SIZE
  70         hex
  71         default 0x800000
  72
  73 config SMM_RESERVED_SIZE
  74         hex
  75         default 0x100000
  76
  77 # Cache As RAM region layout:
  78 #
  79 # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE
  80 # |  Stack      |
  81 # |    |        |
  82 # |    v        |
  83 # +-------------+
  84 # |    ^        |
  85 # |    |        |
  86 # | CAR Globals |
  87 # +-------------+ DCACHE_RAM_BASE
  88 #
  89
  90 config DCACHE_RAM_BASE
  91         hex
  92         default 0xfef00000
  93
  94 config DCACHE_RAM_SIZE
  95         hex
  96         default 0x8000
  97         help
  98           The size of the cache-as-ram region required during bootblock
  99           and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
 100           must add up to a power of 2.
 101
 102 config PRERAM_CBFS_CACHE_SIZE
 103         default 0x0
 104
 105 config ENABLE_BUILTIN_COM1
 106         bool "Enable builtin COM1 Serial Port"
 107         default n
 108         help
 109           The PMC has a legacy COM1 serial port. Choose this option to
 110           configure the pads and enable it. This serial port can be used for
 111           the debug console.
 112
 113 config DISABLE_HPET
 114         bool "Disable the HPET device"
 115         default n
 116         help
 117          Enable this to disable the HPET support
 118          Solves the Linux MP-BIOS bug timer not connected.
 119
 120 config HPET_MIN_TICKS
 121         default 0x80
 122
 123 config USE_GOOGLE_FSP
 124         bool
 125         help
 126          Select this to use Google's custom Braswell FSP header/binary
 127          instead of the public release on Github. Only google/cyan
 128          variants require this; all other boards should use the public release.
 129
 130 config FSP_HEADER_PATH
 131         string
 132         default "\$(src)/vendorcode/intel/fsp/fsp1_1/braswell" if USE_GOOGLE_FSP
 133         default "3rdparty/fsp/BraswellFspBinPkg/Include/"
 134         help
 135          Location of FSP header file FspUpdVpd.h
 136
 137 endif