soc/intel/xeon_sp/spr: Drop microcode constraints
[coreboot2.git] / src / soc / intel / meteorlake / pcie_rp.c
blob9f59ce1f9701d9dac449245074c0917fef9c77c1
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <intelblocks/pcie_rp.h>
4 #include <soc/pci_devs.h>
5 #include <soc/pcie.h>
6 #include <soc/soc_info.h>
8 static const struct pcie_rp_group mtlp_rp_groups[] = {
9 { .slot = PCI_DEV_SLOT_PCIE_1, .start = 0, .count = 8, .lcap_port_base = 1 },
10 { .slot = PCI_DEV_SLOT_PCIE_2, .start = 0, .count = 3, .lcap_port_base = 1 },
11 { .slot = PCI_DEV_SLOT_PCIE_3, .start = 0, .count = 1, .lcap_port_base = 1 },
12 { 0 }
15 const struct pcie_rp_group *get_pcie_rp_table(void)
17 return mtlp_rp_groups;
20 enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev)
22 return PCIE_RP_PCH;
25 int soc_get_cpu_rp_vw_idx(const struct device *dev)
27 return -1;