tests: Replace 'unsigned long int' by 'unsigned long'
[coreboot2.git] / src / soc / amd / cezanne / chip.h
blob738282f5c332d8013c81a16b6ca82fe9a917c247
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef CEZANNE_CHIP_H
4 #define CEZANNE_CHIP_H
6 #include <amdblocks/chip.h>
7 #include <amdblocks/i2c.h>
8 #include <amdblocks/pci_clk_req.h>
9 #include <gpio.h>
10 #include <soc/i2c.h>
11 #include <soc/southbridge.h>
12 #include <drivers/i2c/designware/dw_i2c.h>
13 #include <types.h>
14 #include <vendorcode/amd/fsp/cezanne/FspUsb.h>
16 struct soc_amd_cezanne_config {
17 struct soc_amd_common_config common_config;
18 u8 i2c_scl_reset;
19 struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
20 struct i2c_pad_control i2c_pad[I2C_CTRLR_COUNT];
22 /* Enable S0iX support */
23 bool s0ix_enable;
25 enum {
26 DOWNCORE_AUTO = 0,
27 DOWNCORE_1 = 1, /* Run with 1 physical core */
28 DOWNCORE_2 = 3, /* Run with 2 physical cores */
29 DOWNCORE_3 = 4, /* Run with 3 physical cores */
30 DOWNCORE_4 = 6, /* Run with 4 physical cores */
31 DOWNCORE_5 = 8, /* Run with 5 physical cores */
32 DOWNCORE_6 = 9, /* Run with 6 physical cores */
33 DOWNCORE_7 = 10, /* Run with 7 physical cores */
34 } downcore_mode;
35 bool disable_smt; /* disable second thread on all physical cores */
37 uint8_t stt_control;
38 uint8_t stt_pcb_sensor_count;
39 uint16_t stt_min_limit;
40 uint16_t stt_m1;
41 uint16_t stt_m2;
42 uint16_t stt_m3;
43 uint16_t stt_m4;
44 uint16_t stt_m5;
45 uint16_t stt_m6;
46 uint16_t stt_c_apu;
47 uint16_t stt_c_gpu;
48 uint16_t stt_c_hs2;
49 uint16_t stt_alpha_apu;
50 uint16_t stt_alpha_gpu;
51 uint16_t stt_alpha_hs2;
52 uint16_t stt_skin_temp_apu;
53 uint16_t stt_skin_temp_gpu;
54 uint16_t stt_skin_temp_hs2;
55 uint16_t stt_error_coeff;
56 uint16_t stt_error_rate_coefficient;
58 uint8_t stapm_boost;
59 uint32_t stapm_time_constant_s;
60 uint32_t apu_only_sppt_limit;
61 uint32_t sustained_power_limit_mW;
62 uint32_t fast_ppt_limit_mW;
63 uint32_t slow_ppt_limit_mW;
64 uint32_t slow_ppt_time_constant_s;
65 uint32_t thermctl_limit_degreeC;
67 uint8_t smartshift_enable;
69 uint8_t system_configuration;
71 uint8_t cppc_ctrl;
72 uint8_t cppc_perf_limit_max_range;
73 uint8_t cppc_perf_limit_min_range;
74 uint8_t cppc_epp_max_range;
75 uint8_t cppc_epp_min_range;
76 uint8_t cppc_preferred_cores;
78 /* telemetry settings */
79 uint32_t telemetry_vddcrvddfull_scale_current_mA;
80 uint32_t telemetry_vddcrvddoffset;
81 uint32_t telemetry_vddcrsocfull_scale_current_mA;
82 uint32_t telemetry_vddcrsocoffset;
84 /* The array index is the general purpose PCIe clock output number. Values in here
85 aren't the values written to the register to have the default to be always on. */
86 enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
88 /* performance policy for the PCIe links: power consumption vs. link speed */
89 enum {
90 DXIO_PSPP_DISABLED = 0,
91 DXIO_PSPP_PERFORMANCE,
92 DXIO_PSPP_BALANCED,
93 DXIO_PSPP_POWERSAVE,
94 } pspp_policy;
96 uint8_t usb_phy_custom;
97 struct usb_phy_config usb_phy;
99 /* eDP phy tuning settings */
100 uint8_t edp_phy_override;
101 /* bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 */
102 uint8_t edp_physel;
104 struct {
105 uint8_t dp_vs_pemph_level;
106 uint8_t tx_eq_main;
107 uint8_t tx_eq_pre;
108 uint8_t tx_eq_post;
109 uint8_t tx_vboost_lvl;
110 } edp_tuningset;
112 /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */
113 bool acp_i2s_use_external_48mhz_osc;
116 #endif /* CEZANNE_CHIP_H */