src/mainboard/intel/emeraldlake2/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootblock_common.h>
   4 #include <stdint.h>
   5 #include <arch/io.h>
   6 #include <superio/smsc/sio1007/sio1007.h>
   7 #include <northbridge/intel/sandybridge/raminit.h>
   8 #include <southbridge/intel/bd82x6x/pch.h>
   9
  10 #define SIO_PORT 0x164e
  11
  12 void bootblock_mainboard_early_init(void)
  13 {
  14         const u16 port = SIO_PORT;
  15         const u16 runtime_port = 0x180;
  16
  17         sio1007_enable_uart_at(port);
  18
  19         /* Turn on configuration mode. */
  20         outb(0x55, port);
  21
  22         /* Set the GPIO direction, polarity, and type. */
  23         sio1007_setreg(port, 0x31, 1 << 0, 1 << 0);
  24         sio1007_setreg(port, 0x32, 0 << 0, 1 << 0);
  25         sio1007_setreg(port, 0x33, 0 << 0, 1 << 0);
  26
  27         /* Set the base address for the runtime register block. */
  28         sio1007_setreg(port, 0x30, runtime_port >> 4, 0xff);
  29         sio1007_setreg(port, 0x21, runtime_port >> 12, 0xff);
  30
  31         /* Turn on address decoding for it. */
  32         sio1007_setreg(port, 0x3a, 1 << 1, 1 << 1);
  33
  34         /* Set the value of GPIO 10 by changing GP1, bit 0. */
  35         u8 byte;
  36         byte = inb(runtime_port + 0xc);
  37         byte |= (1 << 0);
  38         outb(byte, runtime_port + 0xc);
  39
  40         /* Turn off address decoding for it. */
  41         sio1007_setreg(port, 0x3a, 0 << 1, 1 << 1);
  42
  43         /* Turn off configuration mode. */
  44         outb(0xaa, port);
  45 }
  46
  47 void mainboard_fill_pei_data(struct pei_data *pei_data)
  48 {
  49 }
  50
  51 const struct southbridge_usb_port mainboard_usb_ports[] = {
  52         /* enabled power  USB oc pin  */
  53         { 1, 0, 0 }, /* P0: Front port  (OC0) */
  54         { 1, 0, 1 }, /* P1: Back port   (OC1) */
  55         { 1, 0, -1 }, /* P2: MINIPCIE1   (no OC) */
  56         { 1, 0, -1 }, /* P3: MMC         (no OC) */
  57         { 1, 0, 2 }, /* P4: Front port  (OC2) */
  58         { 0, 0, -1 }, /* P5: Empty */
  59         { 0, 0, -1 }, /* P6: Empty */
  60         { 0, 0, -1 }, /* P7: Empty */
  61         { 1, 0, 4 }, /* P8: Back port   (OC4) */
  62         { 1, 0, -1 }, /* P9: MINIPCIE3   (no OC) */
  63         { 1, 0, -1 }, /* P10: BLUETOOTH  (no OC) */
  64         { 0, 0, -1 }, /* P11: Empty */
  65         { 1, 0, 6 }, /* P12: Back port  (OC6) */
  66         { 1, 0, 5 }, /* P13: Back port  (OC5) */
  67 };