src/mainboard/system76/cml-u/variants/galp4/overridetree.cb

   1 chip soc/intel/cannonlake
   2         device domain 0 on
   3                 subsystemid 0x1558 0x1403 inherit
   4
   5                 device pci 14.0 on      # USB xHCI
   6                         register "usb2_ports" = "{
   7                                 [0] = USB2_PORT_MID(OC_SKIP),           /* Type-A port 1 */
   8                                 [1] = USB2_PORT_MID(OC_SKIP),           /* 3G / LTE */
   9                                 [2] = USB2_PORT_TYPE_C(OC_SKIP),        /* Type-C port 3 */
  10                                 [3] = USB2_PORT_MID(OC_SKIP),           /* USB Board port 4 */
  11                                 [6] = USB2_PORT_MAX(OC_SKIP),           /* Camera */
  12                                 [9] = USB2_PORT_MID(OC_SKIP),           /* Bluetooth */
  13                         }"
  14                         register "usb3_ports" = "{
  15                                 [0] = USB3_PORT_DEFAULT(OC_SKIP),       /* Type-A port 1 */
  16                                 [1] = USB3_PORT_DEFAULT(OC_SKIP),       /* 4G */
  17                                 [2] = USB3_PORT_DEFAULT(OC_SKIP),       /* Type-C port 3 */
  18                                 [3] = USB3_PORT_DEFAULT(OC_SKIP),       /* USB Board port 4 */
  19                                 [4] = USB3_PORT_EMPTY,                  /* Used by TBT */
  20                                 [5] = USB3_PORT_EMPTY,                  /* Used by TBT */
  21                         }"
  22                 end
  23                 device pci 15.0 on      # I2C #0
  24                         # I2C HID not supported on galp4
  25                 end
  26                 device pci 17.0 on      # SATA
  27                         register "SataPortsEnable" = "{
  28                                 [0] = 1,
  29                                 [2] = 1,
  30                         }"
  31                 end
  32                 device pci 1c.4 on      # PCI Express Port 5
  33                         # PCI Express Root port #5 x4, Clock 4 (TBT)
  34                         register "PcieRpEnable[4]" = "1"
  35                         register "PcieRpLtrEnable[4]" = "1"
  36                         register "PcieRpHotPlug[4]" = "1"
  37                         register "PcieClkSrcUsage[4]" = "4"
  38                         register "PcieClkSrcClkReq[4]" = "4"
  39                 end
  40                 device pci 1d.0 on      # PCI Express Port 9
  41                         # PCI Express Root port #9 x1, Clock 3 (LAN)
  42                         register "PcieRpEnable[8]" = "1"
  43                         register "PcieRpLtrEnable[8]" = "1"
  44                         register "PcieClkSrcUsage[3]" = "8"
  45                         register "PcieClkSrcClkReq[3]" = "3"
  46                 end
  47                 device pci 1d.1 on      # PCI Express Port 10
  48                         # PCI Express Root port #10 x1, Clock 2 (WLAN)
  49                         register "PcieRpEnable[9]" = "1"
  50                         register "PcieRpLtrEnable[9]" = "0"
  51                         register "PcieClkSrcUsage[2]" = "9"
  52                         register "PcieClkSrcClkReq[2]" = "2"
  53                 end
  54                 device pci 1d.4 on      # PCI Express Port 13
  55                         # PCI Express Root port #13 x4, Clock 5 (NVMe)
  56                         register "PcieRpEnable[12]" = "1"
  57                         register "PcieRpLtrEnable[12]" = "1"
  58                         register "PcieClkSrcUsage[5]" = "12"
  59                         register "PcieClkSrcClkReq[5]" = "5"
  60                 end
  61                 device pci 1f.3 on      # Intel HDA
  62                         register "PchHdaAudioLinkDmic0" = "1"
  63                         register "PchHdaAudioLinkDmic1" = "1"
  64                 end
  65         end
  66 end