src/soc/intel/denverton_ns/memmap.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <arch/romstage.h>
   4 #include <cbmem.h>
   5 #include <assert.h>
   6 #include <cpu/x86/mtrr.h>
   7 #include <cpu/x86/smm.h>
   8 #include <device/device.h>
   9 #include <device/pci_def.h>
  10 #include <device/pci_ops.h>
  11 #include <soc/pci_devs.h>
  12 #include <soc/systemagent.h>
  13
  14 /* Returns base of requested region encoded in the system agent. */
  15 static inline uintptr_t system_agent_region_base(size_t reg)
  16 {
  17 #if defined(__SIMPLE_DEVICE__)
  18         pci_devfn_t dev = SA_DEV_ROOT;
  19 #else
  20         struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
  21 #endif
  22         /* All regions concerned for have 1 MiB alignment. */
  23         return ALIGN_DOWN(pci_read_config32(dev, reg), 1 * MiB);
  24 }
  25
  26 static inline uintptr_t smm_region_start(void)
  27 {
  28         return system_agent_region_base(TSEGMB);
  29 }
  30
  31 static inline size_t smm_region_size(void)
  32 {
  33         return system_agent_region_base(TOLUD) - smm_region_start();
  34 }
  35
  36 void smm_region(uintptr_t *start, size_t *size)
  37 {
  38         *start = smm_region_start();
  39         *size = smm_region_size();
  40 }
  41
  42 void fill_postcar_frame(struct postcar_frame *pcf)
  43 {
  44         uintptr_t top_of_ram;
  45
  46         /*
  47          * We need to make sure ramstage will be run cached. At this point exact
  48          * location of ramstage in cbmem is not known. Instruct postcar to cache
  49          * 16 megs under cbmem top which is a safe bet to cover ramstage.
  50          */
  51         top_of_ram = (uintptr_t)cbmem_top();
  52         postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB,
  53                                MTRR_TYPE_WRBACK);
  54
  55         /* Cache the TSEG region */
  56         postcar_enable_tseg_cache(pcf);
  57 }