src/soc/intel/meteorlake/finalize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <bootstate.h>
   5 #include <console/console.h>
   6 #include <cpu/x86/smm.h>
   7 #include <delay.h>
   8 #include <device/pci.h>
   9 #include <gpio.h>
  10 #include <intelblocks/cse.h>
  11 #include <intelblocks/lpc_lib.h>
  12 #include <intelblocks/pcr.h>
  13 #include <intelblocks/pmclib.h>
  14 #include <intelblocks/systemagent.h>
  15 #include <intelblocks/tco.h>
  16 #include <intelblocks/thermal.h>
  17 #include <spi-generic.h>
  18 #include <intelpch/lockdown.h>
  19 #include <soc/p2sb.h>
  20 #include <soc/pci_devs.h>
  21 #include <soc/pcr_ids.h>
  22 #include <soc/pm.h>
  23 #include <soc/smbus.h>
  24 #include <soc/soc_chip.h>
  25 #include <soc/systemagent.h>
  26 #include <timer.h>
  27
  28 static void pch_handle_sideband(config_t *config)
  29 {
  30 }
  31
  32 static void pch_finalize(void)
  33 {
  34         config_t *config = config_of_soc();
  35
  36         /* TCO Lock down */
  37         tco_lockdown();
  38
  39         /* TODO: Add Thermal Configuration */
  40
  41         pch_handle_sideband(config);
  42
  43         pmc_clear_pmcon_sts();
  44 }
  45
  46 static void tbt_finalize(void)
  47 {
  48         int i;
  49         const struct device *dev;
  50
  51         /* Disable Thunderbolt PCIe root ports bus master */
  52         for (i = 0; i < NUM_TBT_FUNCTIONS; i++) {
  53                 dev = pcidev_path_on_root(PCI_DEVFN_TBT(i));
  54                 if (dev)
  55                         pci_dev_disable_bus_master(dev);
  56         }
  57 }
  58
  59 static void sa_finalize(void)
  60 {
  61         if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT)
  62                 sa_lock_pam();
  63 }
  64
  65 static void heci_finalize(void)
  66 {
  67         heci_set_to_d0i3();
  68         if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
  69                 heci1_disable();
  70 }
  71
  72 static void soc_finalize(void *unused)
  73 {
  74         printk(BIOS_DEBUG, "Finalizing chipset.\n");
  75
  76         pch_finalize();
  77         apm_control(APM_CNT_FINALIZE);
  78         tbt_finalize();
  79         sa_finalize();
  80         if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) &&
  81                          CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
  82                 heci_finalize();
  83
  84         /* Indicate finalize step with post code */
  85         post_code(POSTCODE_OS_BOOT);
  86 }
  87
  88 BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
  89 /*
  90  * The purpose of this change is to accommodate more time to push out sending
  91  * CSE EOP messages at post.
  92  */
  93 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, soc_finalize, NULL);