src/soc/intel/tigerlake/acpi/southbridge.asl

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <intelblocks/itss.h>
   4 #include <intelblocks/pcr.h>
   5 #include <soc/itss.h>
   6 #include <soc/pcr_ids.h>
   7
   8 /* PCR access */
   9 #include <soc/intel/common/acpi/pch_pcr.asl>
  10
  11 /* PCH clock */
  12 #include "camera_clock_ctl.asl"
  13
  14 /* GPIO controller */
  15 #if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
  16 #include "gpio_pch_h.asl"
  17 #else
  18 #include "gpio.asl"
  19 #endif
  20
  21 /* ESPI 0:1f.0 */
  22 #include <soc/intel/common/block/acpi/acpi/lpc.asl>
  23
  24 /* PCH HDA */
  25 #include "pch_hda.asl"
  26
  27 /* PCIE Ports */
  28 #include "pcie.asl"
  29
  30 /* Serial IO */
  31 #include "serialio.asl"
  32
  33 /* SMBus 0:1f.4 */
  34 #include <soc/intel/common/block/acpi/acpi/smbus.asl>
  35
  36 /* ISH 0:12.0 */
  37 #include <soc/intel/common/block/acpi/acpi/ish.asl>
  38
  39 /* USB XHCI 0:14.0 */
  40 #include "xhci.asl"
  41
  42 /* PCI _OSC */
  43 #include <soc/intel/common/acpi/pci_osc.asl>
  44
  45 /* GbE 0:1f.6 */
  46 #include <soc/intel/common/block/acpi/acpi/pch_glan.asl>