soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
[coreboot2.git] / spd / lp4x / 
tree265c7208524cb45c55cba8b25c52314999c35fe4
drwxr-xr-x   ..
-rw-r--r-- 12389 memory_parts.json
-rw-r--r-- 118 platforms_manifest.generated.txt
drwxr-xr-x - set-0
drwxr-xr-x - set-1