soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
[coreboot2.git] / spd / 
treee1abed1bcab59f84f58ecd090a9c537f1afc778c
drwxr-xr-x   ..
drwxr-xr-x - ddr4
drwxr-xr-x - lp4x
drwxr-xr-x - lp5