soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
[coreboot2.git] / spd / lp5 / 
tree29e0a3c56dc800b1053c903b2bbe47416a86e0de
drwxr-xr-x   ..
-rw-r--r-- 8034 memory_parts.json
-rw-r--r-- 126 platforms_manifest.generated.txt
drwxr-xr-x - set-0
drwxr-xr-x - set-1