soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR

[coreboot2.git] / spd / lp5 / platforms_manifest.generated.txt

# Generated by:
# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

PTL,set-0
MTL,set-0
ADL,set-0
PHX,set-1
MDN,set-1