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Linux 4.6-rc6
[cris-mirror.git] / include / linux / fsl / guts.h
blob649e9171a9b3baa63f0ad8343e718c8b8e999061
1 /**
2 * Freecale 85xx and 86xx Global Utilties register set
3 *
4 * Authors: Jeff Brown
5 * Timur Tabi <timur@freescale.com>
6 *
7 * Copyright 2004,2007,2012 Freescale Semiconductor, Inc
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15 #ifndef __FSL_GUTS_H__
16 #define __FSL_GUTS_H__
17
18 #include <linux/types.h>
19
20 /**
21 * Global Utility Registers.
22 *
23 * Not all registers defined in this structure are available on all chips, so
24 * you are expected to know whether a given register actually exists on your
25 * chip before you access it.
26 *
27 * Also, some registers are similar on different chips but have slightly
28 * different names. In these cases, one name is chosen to avoid extraneous
29 * #ifdefs.
30 */
31 struct ccsr_guts {
32 __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
33 __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
34 __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
35 __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
36 __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
37 __be32 pordevsr2; /* 0x.0014 - POR device status register 2 */
38 u8 res018[0x20 - 0x18];
39 __be32 porcir; /* 0x.0020 - POR Configuration Information Register */
40 u8 res024[0x30 - 0x24];
41 __be32 gpiocr; /* 0x.0030 - GPIO Control Register */
42 u8 res034[0x40 - 0x34];
43 __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
44 u8 res044[0x50 - 0x44];
45 __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */
46 u8 res054[0x60 - 0x54];
47 __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
48 __be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */
49 __be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
50 u8 res06c[0x70 - 0x6c];
51 __be32 devdisr; /* 0x.0070 - Device Disable Control */
52 #define CCSR_GUTS_DEVDISR_TB1 0x00001000
53 #define CCSR_GUTS_DEVDISR_TB0 0x00004000
54 __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
55 u8 res078[0x7c - 0x78];
56 __be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */
57 __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
58 __be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */
59 __be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */
60 __be32 pmcdr; /* 0x.008c - 4Power management clock disable register */
61 __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
62 __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */
63 __be32 ectrstcr; /* 0x.0098 - Exception reset control register */
64 __be32 autorstsr; /* 0x.009c - Automatic reset status register */
65 __be32 pvr; /* 0x.00a0 - Processor Version Register */
66 __be32 svr; /* 0x.00a4 - System Version Register */
67 u8 res0a8[0xb0 - 0xa8];
68 __be32 rstcr; /* 0x.00b0 - Reset Control Register */
69 u8 res0b4[0xc0 - 0xb4];
70 __be32 iovselsr; /* 0x.00c0 - I/O voltage select status register
71 Called 'elbcvselcr' on 86xx SOCs */
72 u8 res0c4[0x100 - 0xc4];
73 __be32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
74 There are 16 registers */
75 u8 res140[0x224 - 0x140];
76 __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
77 __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
78 u8 res22c[0x604 - 0x22c];
79 __be32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
80 u8 res608[0x800 - 0x608];
81 __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
82 u8 res804[0x900 - 0x804];
83 __be32 ircr; /* 0x.0900 - Infrared Control Register */
84 u8 res904[0x908 - 0x904];
85 __be32 dmacr; /* 0x.0908 - DMA Control Register */
86 u8 res90c[0x914 - 0x90c];
87 __be32 elbccr; /* 0x.0914 - eLBC Control Register */
88 u8 res918[0xb20 - 0x918];
89 __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
90 __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
91 __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
92 u8 resb2c[0xe00 - 0xb2c];
93 __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */
94 u8 rese04[0xe10 - 0xe04];
95 __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
96 u8 rese14[0xe20 - 0xe14];
97 __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
98 __be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */
99 u8 rese28[0xf04 - 0xe28];
100 __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
101 __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
102 u8 resf0c[0xf2c - 0xf0c];
103 __be32 itcr; /* 0x.0f2c - Internal transaction control register */
104 u8 resf30[0xf40 - 0xf30];
105 __be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
106 __be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
107 } __attribute__ ((packed));
108
109
110 /* Alternate function signal multiplex control */
111 #define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
112
113 #ifdef CONFIG_PPC_86xx
114
115 #define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */
116 #define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */
117
118 /*
119 * Set the DMACR register in the GUTS
120 *
121 * The DMACR register determines the source of initiated transfers for each
122 * channel on each DMA controller. Rather than have a bunch of repetitive
123 * macros for the bit patterns, we just have a function that calculates
124 * them.
125 *
126 * guts: Pointer to GUTS structure
127 * co: The DMA controller (0 or 1)
128 * ch: The channel on the DMA controller (0, 1, 2, or 3)
129 * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
130 */
131 static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
132 unsigned int co, unsigned int ch, unsigned int device)
133 {
134 unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
135
136 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
137 }
138
139 #define CCSR_GUTS_PMUXCR_LDPSEL 0x00010000
140 #define CCSR_GUTS_PMUXCR_SSI1_MASK 0x0000C000 /* Bitmask for SSI1 */
141 #define CCSR_GUTS_PMUXCR_SSI1_LA 0x00000000 /* Latched address */
142 #define CCSR_GUTS_PMUXCR_SSI1_HI 0x00004000 /* High impedance */
143 #define CCSR_GUTS_PMUXCR_SSI1_SSI 0x00008000 /* Used for SSI1 */
144 #define CCSR_GUTS_PMUXCR_SSI2_MASK 0x00003000 /* Bitmask for SSI2 */
145 #define CCSR_GUTS_PMUXCR_SSI2_LA 0x00000000 /* Latched address */
146 #define CCSR_GUTS_PMUXCR_SSI2_HI 0x00001000 /* High impedance */
147 #define CCSR_GUTS_PMUXCR_SSI2_SSI 0x00002000 /* Used for SSI2 */
148 #define CCSR_GUTS_PMUXCR_LA_22_25_LA 0x00000000 /* Latched Address */
149 #define CCSR_GUTS_PMUXCR_LA_22_25_HI 0x00000400 /* High impedance */
150 #define CCSR_GUTS_PMUXCR_DBGDRV 0x00000200 /* Signals not driven */
151 #define CCSR_GUTS_PMUXCR_DMA2_0 0x00000008
152 #define CCSR_GUTS_PMUXCR_DMA2_3 0x00000004
153 #define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002
154 #define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001
155
156 /*
157 * Set the DMA external control bits in the GUTS
158 *
159 * The DMA external control bits in the PMUXCR are only meaningful for
160 * channels 0 and 3. Any other channels are ignored.
161 *
162 * guts: Pointer to GUTS structure
163 * co: The DMA controller (0 or 1)
164 * ch: The channel on the DMA controller (0, 1, 2, or 3)
165 * value: the new value for the bit (0 or 1)
166 */
167 static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
168 unsigned int co, unsigned int ch, unsigned int value)
169 {
170 if ((ch == 0) || (ch == 3)) {
171 unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;
172
173 clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
174 }
175 }
176
177 #define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000
178 #define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000
179 #define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000
180 #define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25
181 #define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK 0x06000000
182 #define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \
183 (((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT)
184 #define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT 16
185 #define CCSR_GUTS_CLKDVDR_PXCLK_MASK 0x001F0000
186 #define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT)
187 #define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF
188 #define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
189
190 #endif
191
192 struct ccsr_rcpm_v1 {
193 u8 res0000[4];
194 __be32 cdozsr; /* 0x0004 Core Doze Status Register */
195 u8 res0008[4];
196 __be32 cdozcr; /* 0x000c Core Doze Control Register */
197 u8 res0010[4];
198 __be32 cnapsr; /* 0x0014 Core Nap Status Register */
199 u8 res0018[4];
200 __be32 cnapcr; /* 0x001c Core Nap Control Register */
201 u8 res0020[4];
202 __be32 cdozpsr; /* 0x0024 Core Doze Previous Status Register */
203 u8 res0028[4];
204 __be32 cnappsr; /* 0x002c Core Nap Previous Status Register */
205 u8 res0030[4];
206 __be32 cwaitsr; /* 0x0034 Core Wait Status Register */
207 u8 res0038[4];
208 __be32 cwdtdsr; /* 0x003c Core Watchdog Detect Status Register */
209 __be32 powmgtcsr; /* 0x0040 PM Control&Status Register */
210 #define RCPM_POWMGTCSR_SLP 0x00020000
211 u8 res0044[12];
212 __be32 ippdexpcr; /* 0x0050 IP Powerdown Exception Control Register */
213 u8 res0054[16];
214 __be32 cpmimr; /* 0x0064 Core PM IRQ Mask Register */
215 u8 res0068[4];
216 __be32 cpmcimr; /* 0x006c Core PM Critical IRQ Mask Register */
217 u8 res0070[4];
218 __be32 cpmmcmr; /* 0x0074 Core PM Machine Check Mask Register */
219 u8 res0078[4];
220 __be32 cpmnmimr; /* 0x007c Core PM NMI Mask Register */
221 u8 res0080[4];
222 __be32 ctbenr; /* 0x0084 Core Time Base Enable Register */
223 u8 res0088[4];
224 __be32 ctbckselr; /* 0x008c Core Time Base Clock Select Register */
225 u8 res0090[4];
226 __be32 ctbhltcr; /* 0x0094 Core Time Base Halt Control Register */
227 u8 res0098[4];
228 __be32 cmcpmaskcr; /* 0x00a4 Core Machine Check Mask Register */
229 };
230
231 struct ccsr_rcpm_v2 {
232 u8 res_00[12];
233 __be32 tph10sr0; /* Thread PH10 Status Register */
234 u8 res_10[12];
235 __be32 tph10setr0; /* Thread PH10 Set Control Register */
236 u8 res_20[12];
237 __be32 tph10clrr0; /* Thread PH10 Clear Control Register */
238 u8 res_30[12];
239 __be32 tph10psr0; /* Thread PH10 Previous Status Register */
240 u8 res_40[12];
241 __be32 twaitsr0; /* Thread Wait Status Register */
242 u8 res_50[96];
243 __be32 pcph15sr; /* Physical Core PH15 Status Register */
244 __be32 pcph15setr; /* Physical Core PH15 Set Control Register */
245 __be32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
246 __be32 pcph15psr; /* Physical Core PH15 Prev Status Register */
247 u8 res_c0[16];
248 __be32 pcph20sr; /* Physical Core PH20 Status Register */
249 __be32 pcph20setr; /* Physical Core PH20 Set Control Register */
250 __be32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
251 __be32 pcph20psr; /* Physical Core PH20 Prev Status Register */
252 __be32 pcpw20sr; /* Physical Core PW20 Status Register */
253 u8 res_e0[12];
254 __be32 pcph30sr; /* Physical Core PH30 Status Register */
255 __be32 pcph30setr; /* Physical Core PH30 Set Control Register */
256 __be32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
257 __be32 pcph30psr; /* Physical Core PH30 Prev Status Register */
258 u8 res_100[32];
259 __be32 ippwrgatecr; /* IP Power Gating Control Register */
260 u8 res_124[12];
261 __be32 powmgtcsr; /* Power Management Control & Status Reg */
262 #define RCPM_POWMGTCSR_LPM20_RQ 0x00100000
263 #define RCPM_POWMGTCSR_LPM20_ST 0x00000200
264 #define RCPM_POWMGTCSR_P_LPM20_ST 0x00000100
265 u8 res_134[12];
266 __be32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
267 u8 res_150[12];
268 __be32 tpmimr0; /* Thread PM Interrupt Mask Reg */
269 u8 res_160[12];
270 __be32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */
271 u8 res_170[12];
272 __be32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */
273 u8 res_180[12];
274 __be32 tpmnmimr0; /* Thread PM NMI Mask Reg */
275 u8 res_190[12];
276 __be32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */
277 __be32 pctbenr; /* Physical Core Time Base Enable Reg */
278 __be32 pctbclkselr; /* Physical Core Time Base Clock Select */
279 __be32 tbclkdivr; /* Time Base Clock Divider Register */
280 u8 res_1ac[4];
281 __be32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
282 __be32 clpcl10sr; /* Cluster PCL10 Status Register */
283 __be32 clpcl10setr; /* Cluster PCL30 Set Control Register */
284 __be32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */
285 __be32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
286 __be32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
287 __be32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
288 __be32 cdpwroksetr; /* Core Domain Power OK Set Register */
289 __be32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
290 __be32 cdpwrensr; /* Core Domain Power Enable Status Register */
291 __be32 cddslsr; /* Core Domain Deep Sleep Status Register */
292 u8 res_1e8[8];
293 __be32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */
294 u8 res_300[3568];
295 };
296
297 #endif
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