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mips/signal: In force_fcr31_sig return in the impossible case
[cris-mirror.git] / arch / mips / kernel / traps.c
blob2bf41499334777e7a8682453222427dd084765ee
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
13 * Copyright (C) 2014, Imagination Technologies Ltd.
14 */
15 #include <linux/bitops.h>
16 #include <linux/bug.h>
17 #include <linux/compiler.h>
18 #include <linux/context_tracking.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/kexec.h>
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/extable.h>
25 #include <linux/mm.h>
26 #include <linux/sched/mm.h>
27 #include <linux/sched/debug.h>
28 #include <linux/smp.h>
29 #include <linux/spinlock.h>
30 #include <linux/kallsyms.h>
31 #include <linux/bootmem.h>
32 #include <linux/interrupt.h>
33 #include <linux/ptrace.h>
34 #include <linux/kgdb.h>
35 #include <linux/kdebug.h>
36 #include <linux/kprobes.h>
37 #include <linux/notifier.h>
38 #include <linux/kdb.h>
39 #include <linux/irq.h>
40 #include <linux/perf_event.h>
41
42 #include <asm/addrspace.h>
43 #include <asm/bootinfo.h>
44 #include <asm/branch.h>
45 #include <asm/break.h>
46 #include <asm/cop2.h>
47 #include <asm/cpu.h>
48 #include <asm/cpu-type.h>
49 #include <asm/dsp.h>
50 #include <asm/fpu.h>
51 #include <asm/fpu_emulator.h>
52 #include <asm/idle.h>
53 #include <asm/mips-cm.h>
54 #include <asm/mips-r2-to-r6-emul.h>
55 #include <asm/mips-cm.h>
56 #include <asm/mipsregs.h>
57 #include <asm/mipsmtregs.h>
58 #include <asm/module.h>
59 #include <asm/msa.h>
60 #include <asm/pgtable.h>
61 #include <asm/ptrace.h>
62 #include <asm/sections.h>
63 #include <asm/siginfo.h>
64 #include <asm/tlbdebug.h>
65 #include <asm/traps.h>
66 #include <linux/uaccess.h>
67 #include <asm/watch.h>
68 #include <asm/mmu_context.h>
69 #include <asm/types.h>
70 #include <asm/stacktrace.h>
71 #include <asm/uasm.h>
72
73 extern void check_wait(void);
74 extern asmlinkage void rollback_handle_int(void);
75 extern asmlinkage void handle_int(void);
76 extern u32 handle_tlbl[];
77 extern u32 handle_tlbs[];
78 extern u32 handle_tlbm[];
79 extern asmlinkage void handle_adel(void);
80 extern asmlinkage void handle_ades(void);
81 extern asmlinkage void handle_ibe(void);
82 extern asmlinkage void handle_dbe(void);
83 extern asmlinkage void handle_sys(void);
84 extern asmlinkage void handle_bp(void);
85 extern asmlinkage void handle_ri(void);
86 extern asmlinkage void handle_ri_rdhwr_tlbp(void);
87 extern asmlinkage void handle_ri_rdhwr(void);
88 extern asmlinkage void handle_cpu(void);
89 extern asmlinkage void handle_ov(void);
90 extern asmlinkage void handle_tr(void);
91 extern asmlinkage void handle_msa_fpe(void);
92 extern asmlinkage void handle_fpe(void);
93 extern asmlinkage void handle_ftlb(void);
94 extern asmlinkage void handle_msa(void);
95 extern asmlinkage void handle_mdmx(void);
96 extern asmlinkage void handle_watch(void);
97 extern asmlinkage void handle_mt(void);
98 extern asmlinkage void handle_dsp(void);
99 extern asmlinkage void handle_mcheck(void);
100 extern asmlinkage void handle_reserved(void);
101 extern void tlb_do_page_fault_0(void);
102
103 void (*board_be_init)(void);
104 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
105 void (*board_nmi_handler_setup)(void);
106 void (*board_ejtag_handler_setup)(void);
107 void (*board_bind_eic_interrupt)(int irq, int regset);
108 void (*board_ebase_setup)(void);
109 void(*board_cache_error_setup)(void);
110
111 static void show_raw_backtrace(unsigned long reg29)
112 {
113 unsigned long *sp = (unsigned long *)(reg29 & ~3);
114 unsigned long addr;
115
116 printk("Call Trace:");
117 #ifdef CONFIG_KALLSYMS
118 printk("\n");
119 #endif
120 while (!kstack_end(sp)) {
121 unsigned long __user *p =
122 (unsigned long __user *)(unsigned long)sp++;
123 if (__get_user(addr, p)) {
124 printk(" (Bad stack address)");
125 break;
126 }
127 if (__kernel_text_address(addr))
128 print_ip_sym(addr);
129 }
130 printk("\n");
131 }
132
133 #ifdef CONFIG_KALLSYMS
134 int raw_show_trace;
135 static int __init set_raw_show_trace(char *str)
136 {
137 raw_show_trace = 1;
138 return 1;
139 }
140 __setup("raw_show_trace", set_raw_show_trace);
141 #endif
142
143 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
144 {
145 unsigned long sp = regs->regs[29];
146 unsigned long ra = regs->regs[31];
147 unsigned long pc = regs->cp0_epc;
148
149 if (!task)
150 task = current;
151
152 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) {
153 show_raw_backtrace(sp);
154 return;
155 }
156 printk("Call Trace:\n");
157 do {
158 print_ip_sym(pc);
159 pc = unwind_stack(task, &sp, pc, &ra);
160 } while (pc);
161 pr_cont("\n");
162 }
163
164 /*
165 * This routine abuses get_user()/put_user() to reference pointers
166 * with at least a bit of error checking ...
167 */
168 static void show_stacktrace(struct task_struct *task,
169 const struct pt_regs *regs)
170 {
171 const int field = 2 * sizeof(unsigned long);
172 long stackdata;
173 int i;
174 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
175
176 printk("Stack :");
177 i = 0;
178 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
179 if (i && ((i % (64 / field)) == 0)) {
180 pr_cont("\n");
181 printk(" ");
182 }
183 if (i > 39) {
184 pr_cont(" ...");
185 break;
186 }
187
188 if (__get_user(stackdata, sp++)) {
189 pr_cont(" (Bad stack address)");
190 break;
191 }
192
193 pr_cont(" %0*lx", field, stackdata);
194 i++;
195 }
196 pr_cont("\n");
197 show_backtrace(task, regs);
198 }
199
200 void show_stack(struct task_struct *task, unsigned long *sp)
201 {
202 struct pt_regs regs;
203 mm_segment_t old_fs = get_fs();
204
205 regs.cp0_status = KSU_KERNEL;
206 if (sp) {
207 regs.regs[29] = (unsigned long)sp;
208 regs.regs[31] = 0;
209 regs.cp0_epc = 0;
210 } else {
211 if (task && task != current) {
212 regs.regs[29] = task->thread.reg29;
213 regs.regs[31] = 0;
214 regs.cp0_epc = task->thread.reg31;
215 #ifdef CONFIG_KGDB_KDB
216 } else if (atomic_read(&kgdb_active) != -1 &&
217 kdb_current_regs) {
218 memcpy(&regs, kdb_current_regs, sizeof(regs));
219 #endif /* CONFIG_KGDB_KDB */
220 } else {
221 prepare_frametrace(&regs);
222 }
223 }
224 /*
225 * show_stack() deals exclusively with kernel mode, so be sure to access
226 * the stack in the kernel (not user) address space.
227 */
228 set_fs(KERNEL_DS);
229 show_stacktrace(task, &regs);
230 set_fs(old_fs);
231 }
232
233 static void show_code(unsigned int __user *pc)
234 {
235 long i;
236 unsigned short __user *pc16 = NULL;
237
238 printk("Code:");
239
240 if ((unsigned long)pc & 1)
241 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
242 for(i = -3 ; i < 6 ; i++) {
243 unsigned int insn;
244 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
245 pr_cont(" (Bad address in epc)\n");
246 break;
247 }
248 pr_cont("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
249 }
250 pr_cont("\n");
251 }
252
253 static void __show_regs(const struct pt_regs *regs)
254 {
255 const int field = 2 * sizeof(unsigned long);
256 unsigned int cause = regs->cp0_cause;
257 unsigned int exccode;
258 int i;
259
260 show_regs_print_info(KERN_DEFAULT);
261
262 /*
263 * Saved main processor registers
264 */
265 for (i = 0; i < 32; ) {
266 if ((i % 4) == 0)
267 printk("$%2d :", i);
268 if (i == 0)
269 pr_cont(" %0*lx", field, 0UL);
270 else if (i == 26 || i == 27)
271 pr_cont(" %*s", field, "");
272 else
273 pr_cont(" %0*lx", field, regs->regs[i]);
274
275 i++;
276 if ((i % 4) == 0)
277 pr_cont("\n");
278 }
279
280 #ifdef CONFIG_CPU_HAS_SMARTMIPS
281 printk("Acx : %0*lx\n", field, regs->acx);
282 #endif
283 printk("Hi : %0*lx\n", field, regs->hi);
284 printk("Lo : %0*lx\n", field, regs->lo);
285
286 /*
287 * Saved cp0 registers
288 */
289 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
290 (void *) regs->cp0_epc);
291 printk("ra : %0*lx %pS\n", field, regs->regs[31],
292 (void *) regs->regs[31]);
293
294 printk("Status: %08x ", (uint32_t) regs->cp0_status);
295
296 if (cpu_has_3kex) {
297 if (regs->cp0_status & ST0_KUO)
298 pr_cont("KUo ");
299 if (regs->cp0_status & ST0_IEO)
300 pr_cont("IEo ");
301 if (regs->cp0_status & ST0_KUP)
302 pr_cont("KUp ");
303 if (regs->cp0_status & ST0_IEP)
304 pr_cont("IEp ");
305 if (regs->cp0_status & ST0_KUC)
306 pr_cont("KUc ");
307 if (regs->cp0_status & ST0_IEC)
308 pr_cont("IEc ");
309 } else if (cpu_has_4kex) {
310 if (regs->cp0_status & ST0_KX)
311 pr_cont("KX ");
312 if (regs->cp0_status & ST0_SX)
313 pr_cont("SX ");
314 if (regs->cp0_status & ST0_UX)
315 pr_cont("UX ");
316 switch (regs->cp0_status & ST0_KSU) {
317 case KSU_USER:
318 pr_cont("USER ");
319 break;
320 case KSU_SUPERVISOR:
321 pr_cont("SUPERVISOR ");
322 break;
323 case KSU_KERNEL:
324 pr_cont("KERNEL ");
325 break;
326 default:
327 pr_cont("BAD_MODE ");
328 break;
329 }
330 if (regs->cp0_status & ST0_ERL)
331 pr_cont("ERL ");
332 if (regs->cp0_status & ST0_EXL)
333 pr_cont("EXL ");
334 if (regs->cp0_status & ST0_IE)
335 pr_cont("IE ");
336 }
337 pr_cont("\n");
338
339 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
340 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode);
341
342 if (1 <= exccode && exccode <= 5)
343 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
344
345 printk("PrId : %08x (%s)\n", read_c0_prid(),
346 cpu_name_string());
347 }
348
349 /*
350 * FIXME: really the generic show_regs should take a const pointer argument.
351 */
352 void show_regs(struct pt_regs *regs)
353 {
354 __show_regs((struct pt_regs *)regs);
355 }
356
357 void show_registers(struct pt_regs *regs)
358 {
359 const int field = 2 * sizeof(unsigned long);
360 mm_segment_t old_fs = get_fs();
361
362 __show_regs(regs);
363 print_modules();
364 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
365 current->comm, current->pid, current_thread_info(), current,
366 field, current_thread_info()->tp_value);
367 if (cpu_has_userlocal) {
368 unsigned long tls;
369
370 tls = read_c0_userlocal();
371 if (tls != current_thread_info()->tp_value)
372 printk("*HwTLS: %0*lx\n", field, tls);
373 }
374
375 if (!user_mode(regs))
376 /* Necessary for getting the correct stack content */
377 set_fs(KERNEL_DS);
378 show_stacktrace(current, regs);
379 show_code((unsigned int __user *) regs->cp0_epc);
380 printk("\n");
381 set_fs(old_fs);
382 }
383
384 static DEFINE_RAW_SPINLOCK(die_lock);
385
386 void __noreturn die(const char *str, struct pt_regs *regs)
387 {
388 static int die_counter;
389 int sig = SIGSEGV;
390
391 oops_enter();
392
393 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
394 SIGSEGV) == NOTIFY_STOP)
395 sig = 0;
396
397 console_verbose();
398 raw_spin_lock_irq(&die_lock);
399 bust_spinlocks(1);
400
401 printk("%s[#%d]:\n", str, ++die_counter);
402 show_registers(regs);
403 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
404 raw_spin_unlock_irq(&die_lock);
405
406 oops_exit();
407
408 if (in_interrupt())
409 panic("Fatal exception in interrupt");
410
411 if (panic_on_oops)
412 panic("Fatal exception");
413
414 if (regs && kexec_should_crash(current))
415 crash_kexec(regs);
416
417 do_exit(sig);
418 }
419
420 extern struct exception_table_entry __start___dbe_table[];
421 extern struct exception_table_entry __stop___dbe_table[];
422
423 __asm__(
424 " .section __dbe_table, \"a\"\n"
425 " .previous \n");
426
427 /* Given an address, look for it in the exception tables. */
428 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
429 {
430 const struct exception_table_entry *e;
431
432 e = search_extable(__start___dbe_table,
433 __stop___dbe_table - __start___dbe_table, addr);
434 if (!e)
435 e = search_module_dbetables(addr);
436 return e;
437 }
438
439 asmlinkage void do_be(struct pt_regs *regs)
440 {
441 const int field = 2 * sizeof(unsigned long);
442 const struct exception_table_entry *fixup = NULL;
443 int data = regs->cp0_cause & 4;
444 int action = MIPS_BE_FATAL;
445 enum ctx_state prev_state;
446
447 prev_state = exception_enter();
448 /* XXX For now. Fixme, this searches the wrong table ... */
449 if (data && !user_mode(regs))
450 fixup = search_dbe_tables(exception_epc(regs));
451
452 if (fixup)
453 action = MIPS_BE_FIXUP;
454
455 if (board_be_handler)
456 action = board_be_handler(regs, fixup != NULL);
457 else
458 mips_cm_error_report();
459
460 switch (action) {
461 case MIPS_BE_DISCARD:
462 goto out;
463 case MIPS_BE_FIXUP:
464 if (fixup) {
465 regs->cp0_epc = fixup->nextinsn;
466 goto out;
467 }
468 break;
469 default:
470 break;
471 }
472
473 /*
474 * Assume it would be too dangerous to continue ...
475 */
476 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
477 data ? "Data" : "Instruction",
478 field, regs->cp0_epc, field, regs->regs[31]);
479 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr,
480 SIGBUS) == NOTIFY_STOP)
481 goto out;
482
483 die_if_kernel("Oops", regs);
484 force_sig(SIGBUS, current);
485
486 out:
487 exception_exit(prev_state);
488 }
489
490 /*
491 * ll/sc, rdhwr, sync emulation
492 */
493
494 #define OPCODE 0xfc000000
495 #define BASE 0x03e00000
496 #define RT 0x001f0000
497 #define OFFSET 0x0000ffff
498 #define LL 0xc0000000
499 #define SC 0xe0000000
500 #define SPEC0 0x00000000
501 #define SPEC3 0x7c000000
502 #define RD 0x0000f800
503 #define FUNC 0x0000003f
504 #define SYNC 0x0000000f
505 #define RDHWR 0x0000003b
506
507 /* microMIPS definitions */
508 #define MM_POOL32A_FUNC 0xfc00ffff
509 #define MM_RDHWR 0x00006b3c
510 #define MM_RS 0x001f0000
511 #define MM_RT 0x03e00000
512
513 /*
514 * The ll_bit is cleared by r*_switch.S
515 */
516
517 unsigned int ll_bit;
518 struct task_struct *ll_task;
519
520 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
521 {
522 unsigned long value, __user *vaddr;
523 long offset;
524
525 /*
526 * analyse the ll instruction that just caused a ri exception
527 * and put the referenced address to addr.
528 */
529
530 /* sign extend offset */
531 offset = opcode & OFFSET;
532 offset <<= 16;
533 offset >>= 16;
534
535 vaddr = (unsigned long __user *)
536 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
537
538 if ((unsigned long)vaddr & 3)
539 return SIGBUS;
540 if (get_user(value, vaddr))
541 return SIGSEGV;
542
543 preempt_disable();
544
545 if (ll_task == NULL || ll_task == current) {
546 ll_bit = 1;
547 } else {
548 ll_bit = 0;
549 }
550 ll_task = current;
551
552 preempt_enable();
553
554 regs->regs[(opcode & RT) >> 16] = value;
555
556 return 0;
557 }
558
559 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
560 {
561 unsigned long __user *vaddr;
562 unsigned long reg;
563 long offset;
564
565 /*
566 * analyse the sc instruction that just caused a ri exception
567 * and put the referenced address to addr.
568 */
569
570 /* sign extend offset */
571 offset = opcode & OFFSET;
572 offset <<= 16;
573 offset >>= 16;
574
575 vaddr = (unsigned long __user *)
576 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
577 reg = (opcode & RT) >> 16;
578
579 if ((unsigned long)vaddr & 3)
580 return SIGBUS;
581
582 preempt_disable();
583
584 if (ll_bit == 0 || ll_task != current) {
585 regs->regs[reg] = 0;
586 preempt_enable();
587 return 0;
588 }
589
590 preempt_enable();
591
592 if (put_user(regs->regs[reg], vaddr))
593 return SIGSEGV;
594
595 regs->regs[reg] = 1;
596
597 return 0;
598 }
599
600 /*
601 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
602 * opcodes are supposed to result in coprocessor unusable exceptions if
603 * executed on ll/sc-less processors. That's the theory. In practice a
604 * few processors such as NEC's VR4100 throw reserved instruction exceptions
605 * instead, so we're doing the emulation thing in both exception handlers.
606 */
607 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
608 {
609 if ((opcode & OPCODE) == LL) {
610 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
611 1, regs, 0);
612 return simulate_ll(regs, opcode);
613 }
614 if ((opcode & OPCODE) == SC) {
615 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
616 1, regs, 0);
617 return simulate_sc(regs, opcode);
618 }
619
620 return -1; /* Must be something else ... */
621 }
622
623 /*
624 * Simulate trapping 'rdhwr' instructions to provide user accessible
625 * registers not implemented in hardware.
626 */
627 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
628 {
629 struct thread_info *ti = task_thread_info(current);
630
631 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
632 1, regs, 0);
633 switch (rd) {
634 case MIPS_HWR_CPUNUM: /* CPU number */
635 regs->regs[rt] = smp_processor_id();
636 return 0;
637 case MIPS_HWR_SYNCISTEP: /* SYNCI length */
638 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
639 current_cpu_data.icache.linesz);
640 return 0;
641 case MIPS_HWR_CC: /* Read count register */
642 regs->regs[rt] = read_c0_count();
643 return 0;
644 case MIPS_HWR_CCRES: /* Count register resolution */
645 switch (current_cpu_type()) {
646 case CPU_20KC:
647 case CPU_25KF:
648 regs->regs[rt] = 1;
649 break;
650 default:
651 regs->regs[rt] = 2;
652 }
653 return 0;
654 case MIPS_HWR_ULR: /* Read UserLocal register */
655 regs->regs[rt] = ti->tp_value;
656 return 0;
657 default:
658 return -1;
659 }
660 }
661
662 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
663 {
664 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
665 int rd = (opcode & RD) >> 11;
666 int rt = (opcode & RT) >> 16;
667
668 simulate_rdhwr(regs, rd, rt);
669 return 0;
670 }
671
672 /* Not ours. */
673 return -1;
674 }
675
676 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode)
677 {
678 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
679 int rd = (opcode & MM_RS) >> 16;
680 int rt = (opcode & MM_RT) >> 21;
681 simulate_rdhwr(regs, rd, rt);
682 return 0;
683 }
684
685 /* Not ours. */
686 return -1;
687 }
688
689 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
690 {
691 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
692 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
693 1, regs, 0);
694 return 0;
695 }
696
697 return -1; /* Must be something else ... */
698 }
699
700 asmlinkage void do_ov(struct pt_regs *regs)
701 {
702 enum ctx_state prev_state;
703 siginfo_t info = {
704 .si_signo = SIGFPE,
705 .si_code = FPE_INTOVF,
706 .si_addr = (void __user *)regs->cp0_epc,
707 };
708
709 prev_state = exception_enter();
710 die_if_kernel("Integer overflow", regs);
711
712 force_sig_info(SIGFPE, &info, current);
713 exception_exit(prev_state);
714 }
715
716 /*
717 * Send SIGFPE according to FCSR Cause bits, which must have already
718 * been masked against Enable bits. This is impotant as Inexact can
719 * happen together with Overflow or Underflow, and `ptrace' can set
720 * any bits.
721 */
722 void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
723 struct task_struct *tsk)
724 {
725 struct siginfo si = { .si_addr = fault_addr, .si_signo = SIGFPE };
726
727 if (fcr31 & FPU_CSR_INV_X)
728 si.si_code = FPE_FLTINV;
729 else if (fcr31 & FPU_CSR_DIV_X)
730 si.si_code = FPE_FLTDIV;
731 else if (fcr31 & FPU_CSR_OVF_X)
732 si.si_code = FPE_FLTOVF;
733 else if (fcr31 & FPU_CSR_UDF_X)
734 si.si_code = FPE_FLTUND;
735 else if (fcr31 & FPU_CSR_INE_X)
736 si.si_code = FPE_FLTRES;
737 else
738 return; /* Broken hardware? */
739 force_sig_info(SIGFPE, &si, tsk);
740 }
741
742 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
743 {
744 struct siginfo si = { 0 };
745 struct vm_area_struct *vma;
746
747 switch (sig) {
748 case 0:
749 return 0;
750
751 case SIGFPE:
752 force_fcr31_sig(fcr31, fault_addr, current);
753 return 1;
754
755 case SIGBUS:
756 si.si_addr = fault_addr;
757 si.si_signo = sig;
758 si.si_code = BUS_ADRERR;
759 force_sig_info(sig, &si, current);
760 return 1;
761
762 case SIGSEGV:
763 si.si_addr = fault_addr;
764 si.si_signo = sig;
765 down_read(&current->mm->mmap_sem);
766 vma = find_vma(current->mm, (unsigned long)fault_addr);
767 if (vma && (vma->vm_start <= (unsigned long)fault_addr))
768 si.si_code = SEGV_ACCERR;
769 else
770 si.si_code = SEGV_MAPERR;
771 up_read(&current->mm->mmap_sem);
772 force_sig_info(sig, &si, current);
773 return 1;
774
775 default:
776 force_sig(sig, current);
777 return 1;
778 }
779 }
780
781 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
782 unsigned long old_epc, unsigned long old_ra)
783 {
784 union mips_instruction inst = { .word = opcode };
785 void __user *fault_addr;
786 unsigned long fcr31;
787 int sig;
788
789 /* If it's obviously not an FP instruction, skip it */
790 switch (inst.i_format.opcode) {
791 case cop1_op:
792 case cop1x_op:
793 case lwc1_op:
794 case ldc1_op:
795 case swc1_op:
796 case sdc1_op:
797 break;
798
799 default:
800 return -1;
801 }
802
803 /*
804 * do_ri skipped over the instruction via compute_return_epc, undo
805 * that for the FPU emulator.
806 */
807 regs->cp0_epc = old_epc;
808 regs->regs[31] = old_ra;
809
810 /* Save the FP context to struct thread_struct */
811 lose_fpu(1);
812
813 /* Run the emulator */
814 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
815 &fault_addr);
816
817 /*
818 * We can't allow the emulated instruction to leave any
819 * enabled Cause bits set in $fcr31.
820 */
821 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
822 current->thread.fpu.fcr31 &= ~fcr31;
823
824 /* Restore the hardware register state */
825 own_fpu(1);
826
827 /* Send a signal if required. */
828 process_fpemu_return(sig, fault_addr, fcr31);
829
830 return 0;
831 }
832
833 /*
834 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
835 */
836 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
837 {
838 enum ctx_state prev_state;
839 void __user *fault_addr;
840 int sig;
841
842 prev_state = exception_enter();
843 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
844 SIGFPE) == NOTIFY_STOP)
845 goto out;
846
847 /* Clear FCSR.Cause before enabling interrupts */
848 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~mask_fcr31_x(fcr31));
849 local_irq_enable();
850
851 die_if_kernel("FP exception in kernel code", regs);
852
853 if (fcr31 & FPU_CSR_UNI_X) {
854 /*
855 * Unimplemented operation exception. If we've got the full
856 * software emulator on-board, let's use it...
857 *
858 * Force FPU to dump state into task/thread context. We're
859 * moving a lot of data here for what is probably a single
860 * instruction, but the alternative is to pre-decode the FP
861 * register operands before invoking the emulator, which seems
862 * a bit extreme for what should be an infrequent event.
863 */
864 /* Ensure 'resume' not overwrite saved fp context again. */
865 lose_fpu(1);
866
867 /* Run the emulator */
868 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
869 &fault_addr);
870
871 /*
872 * We can't allow the emulated instruction to leave any
873 * enabled Cause bits set in $fcr31.
874 */
875 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
876 current->thread.fpu.fcr31 &= ~fcr31;
877
878 /* Restore the hardware register state */
879 own_fpu(1); /* Using the FPU again. */
880 } else {
881 sig = SIGFPE;
882 fault_addr = (void __user *) regs->cp0_epc;
883 }
884
885 /* Send a signal if required. */
886 process_fpemu_return(sig, fault_addr, fcr31);
887
888 out:
889 exception_exit(prev_state);
890 }
891
892 void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
893 const char *str)
894 {
895 siginfo_t info = { 0 };
896 char b[40];
897
898 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
899 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr,
900 SIGTRAP) == NOTIFY_STOP)
901 return;
902 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
903
904 if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr,
905 SIGTRAP) == NOTIFY_STOP)
906 return;
907
908 /*
909 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
910 * insns, even for trap and break codes that indicate arithmetic
911 * failures. Weird ...
912 * But should we continue the brokenness??? --macro
913 */
914 switch (code) {
915 case BRK_OVERFLOW:
916 case BRK_DIVZERO:
917 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
918 die_if_kernel(b, regs);
919 if (code == BRK_DIVZERO)
920 info.si_code = FPE_INTDIV;
921 else
922 info.si_code = FPE_INTOVF;
923 info.si_signo = SIGFPE;
924 info.si_addr = (void __user *) regs->cp0_epc;
925 force_sig_info(SIGFPE, &info, current);
926 break;
927 case BRK_BUG:
928 die_if_kernel("Kernel bug detected", regs);
929 force_sig(SIGTRAP, current);
930 break;
931 case BRK_MEMU:
932 /*
933 * This breakpoint code is used by the FPU emulator to retake
934 * control of the CPU after executing the instruction from the
935 * delay slot of an emulated branch.
936 *
937 * Terminate if exception was recognized as a delay slot return
938 * otherwise handle as normal.
939 */
940 if (do_dsemulret(regs))
941 return;
942
943 die_if_kernel("Math emu break/trap", regs);
944 force_sig(SIGTRAP, current);
945 break;
946 default:
947 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
948 die_if_kernel(b, regs);
949 if (si_code) {
950 info.si_signo = SIGTRAP;
951 info.si_code = si_code;
952 force_sig_info(SIGTRAP, &info, current);
953 } else {
954 force_sig(SIGTRAP, current);
955 }
956 }
957 }
958
959 asmlinkage void do_bp(struct pt_regs *regs)
960 {
961 unsigned long epc = msk_isa16_mode(exception_epc(regs));
962 unsigned int opcode, bcode;
963 enum ctx_state prev_state;
964 mm_segment_t seg;
965
966 seg = get_fs();
967 if (!user_mode(regs))
968 set_fs(KERNEL_DS);
969
970 prev_state = exception_enter();
971 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
972 if (get_isa16_mode(regs->cp0_epc)) {
973 u16 instr[2];
974
975 if (__get_user(instr[0], (u16 __user *)epc))
976 goto out_sigsegv;
977
978 if (!cpu_has_mmips) {
979 /* MIPS16e mode */
980 bcode = (instr[0] >> 5) & 0x3f;
981 } else if (mm_insn_16bit(instr[0])) {
982 /* 16-bit microMIPS BREAK */
983 bcode = instr[0] & 0xf;
984 } else {
985 /* 32-bit microMIPS BREAK */
986 if (__get_user(instr[1], (u16 __user *)(epc + 2)))
987 goto out_sigsegv;
988 opcode = (instr[0] << 16) | instr[1];
989 bcode = (opcode >> 6) & ((1 << 20) - 1);
990 }
991 } else {
992 if (__get_user(opcode, (unsigned int __user *)epc))
993 goto out_sigsegv;
994 bcode = (opcode >> 6) & ((1 << 20) - 1);
995 }
996
997 /*
998 * There is the ancient bug in the MIPS assemblers that the break
999 * code starts left to bit 16 instead to bit 6 in the opcode.
1000 * Gas is bug-compatible, but not always, grrr...
1001 * We handle both cases with a simple heuristics. --macro
1002 */
1003 if (bcode >= (1 << 10))
1004 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
1005
1006 /*
1007 * notify the kprobe handlers, if instruction is likely to
1008 * pertain to them.
1009 */
1010 switch (bcode) {
1011 case BRK_UPROBE:
1012 if (notify_die(DIE_UPROBE, "uprobe", regs, bcode,
1013 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1014 goto out;
1015 else
1016 break;
1017 case BRK_UPROBE_XOL:
1018 if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode,
1019 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1020 goto out;
1021 else
1022 break;
1023 case BRK_KPROBE_BP:
1024 if (notify_die(DIE_BREAK, "debug", regs, bcode,
1025 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1026 goto out;
1027 else
1028 break;
1029 case BRK_KPROBE_SSTEPBP:
1030 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
1031 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1032 goto out;
1033 else
1034 break;
1035 default:
1036 break;
1037 }
1038
1039 do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break");
1040
1041 out:
1042 set_fs(seg);
1043 exception_exit(prev_state);
1044 return;
1045
1046 out_sigsegv:
1047 force_sig(SIGSEGV, current);
1048 goto out;
1049 }
1050
1051 asmlinkage void do_tr(struct pt_regs *regs)
1052 {
1053 u32 opcode, tcode = 0;
1054 enum ctx_state prev_state;
1055 u16 instr[2];
1056 mm_segment_t seg;
1057 unsigned long epc = msk_isa16_mode(exception_epc(regs));
1058
1059 seg = get_fs();
1060 if (!user_mode(regs))
1061 set_fs(get_ds());
1062
1063 prev_state = exception_enter();
1064 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1065 if (get_isa16_mode(regs->cp0_epc)) {
1066 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
1067 __get_user(instr[1], (u16 __user *)(epc + 2)))
1068 goto out_sigsegv;
1069 opcode = (instr[0] << 16) | instr[1];
1070 /* Immediate versions don't provide a code. */
1071 if (!(opcode & OPCODE))
1072 tcode = (opcode >> 12) & ((1 << 4) - 1);
1073 } else {
1074 if (__get_user(opcode, (u32 __user *)epc))
1075 goto out_sigsegv;
1076 /* Immediate versions don't provide a code. */
1077 if (!(opcode & OPCODE))
1078 tcode = (opcode >> 6) & ((1 << 10) - 1);
1079 }
1080
1081 do_trap_or_bp(regs, tcode, 0, "Trap");
1082
1083 out:
1084 set_fs(seg);
1085 exception_exit(prev_state);
1086 return;
1087
1088 out_sigsegv:
1089 force_sig(SIGSEGV, current);
1090 goto out;
1091 }
1092
1093 asmlinkage void do_ri(struct pt_regs *regs)
1094 {
1095 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
1096 unsigned long old_epc = regs->cp0_epc;
1097 unsigned long old31 = regs->regs[31];
1098 enum ctx_state prev_state;
1099 unsigned int opcode = 0;
1100 int status = -1;
1101
1102 /*
1103 * Avoid any kernel code. Just emulate the R2 instruction
1104 * as quickly as possible.
1105 */
1106 if (mipsr2_emulation && cpu_has_mips_r6 &&
1107 likely(user_mode(regs)) &&
1108 likely(get_user(opcode, epc) >= 0)) {
1109 unsigned long fcr31 = 0;
1110
1111 status = mipsr2_decoder(regs, opcode, &fcr31);
1112 switch (status) {
1113 case 0:
1114 case SIGEMT:
1115 return;
1116 case SIGILL:
1117 goto no_r2_instr;
1118 default:
1119 process_fpemu_return(status,
1120 &current->thread.cp0_baduaddr,
1121 fcr31);
1122 return;
1123 }
1124 }
1125
1126 no_r2_instr:
1127
1128 prev_state = exception_enter();
1129 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1130
1131 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
1132 SIGILL) == NOTIFY_STOP)
1133 goto out;
1134
1135 die_if_kernel("Reserved instruction in kernel code", regs);
1136
1137 if (unlikely(compute_return_epc(regs) < 0))
1138 goto out;
1139
1140 if (!get_isa16_mode(regs->cp0_epc)) {
1141 if (unlikely(get_user(opcode, epc) < 0))
1142 status = SIGSEGV;
1143
1144 if (!cpu_has_llsc && status < 0)
1145 status = simulate_llsc(regs, opcode);
1146
1147 if (status < 0)
1148 status = simulate_rdhwr_normal(regs, opcode);
1149
1150 if (status < 0)
1151 status = simulate_sync(regs, opcode);
1152
1153 if (status < 0)
1154 status = simulate_fp(regs, opcode, old_epc, old31);
1155 } else if (cpu_has_mmips) {
1156 unsigned short mmop[2] = { 0 };
1157
1158 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
1159 status = SIGSEGV;
1160 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
1161 status = SIGSEGV;
1162 opcode = mmop[0];
1163 opcode = (opcode << 16) | mmop[1];
1164
1165 if (status < 0)
1166 status = simulate_rdhwr_mm(regs, opcode);
1167 }
1168
1169 if (status < 0)
1170 status = SIGILL;
1171
1172 if (unlikely(status > 0)) {
1173 regs->cp0_epc = old_epc; /* Undo skip-over. */
1174 regs->regs[31] = old31;
1175 force_sig(status, current);
1176 }
1177
1178 out:
1179 exception_exit(prev_state);
1180 }
1181
1182 /*
1183 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1184 * emulated more than some threshold number of instructions, force migration to
1185 * a "CPU" that has FP support.
1186 */
1187 static void mt_ase_fp_affinity(void)
1188 {
1189 #ifdef CONFIG_MIPS_MT_FPAFF
1190 if (mt_fpemul_threshold > 0 &&
1191 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1192 /*
1193 * If there's no FPU present, or if the application has already
1194 * restricted the allowed set to exclude any CPUs with FPUs,
1195 * we'll skip the procedure.
1196 */
1197 if (cpumask_intersects(&current->cpus_allowed, &mt_fpu_cpumask)) {
1198 cpumask_t tmask;
1199
1200 current->thread.user_cpus_allowed
1201 = current->cpus_allowed;
1202 cpumask_and(&tmask, &current->cpus_allowed,
1203 &mt_fpu_cpumask);
1204 set_cpus_allowed_ptr(current, &tmask);
1205 set_thread_flag(TIF_FPUBOUND);
1206 }
1207 }
1208 #endif /* CONFIG_MIPS_MT_FPAFF */
1209 }
1210
1211 /*
1212 * No lock; only written during early bootup by CPU 0.
1213 */
1214 static RAW_NOTIFIER_HEAD(cu2_chain);
1215
1216 int __ref register_cu2_notifier(struct notifier_block *nb)
1217 {
1218 return raw_notifier_chain_register(&cu2_chain, nb);
1219 }
1220
1221 int cu2_notifier_call_chain(unsigned long val, void *v)
1222 {
1223 return raw_notifier_call_chain(&cu2_chain, val, v);
1224 }
1225
1226 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1227 void *data)
1228 {
1229 struct pt_regs *regs = data;
1230
1231 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1232 "instruction", regs);
1233 force_sig(SIGILL, current);
1234
1235 return NOTIFY_OK;
1236 }
1237
1238 static int wait_on_fp_mode_switch(atomic_t *p)
1239 {
1240 /*
1241 * The FP mode for this task is currently being switched. That may
1242 * involve modifications to the format of this tasks FP context which
1243 * make it unsafe to proceed with execution for the moment. Instead,
1244 * schedule some other task.
1245 */
1246 schedule();
1247 return 0;
1248 }
1249
1250 static int enable_restore_fp_context(int msa)
1251 {
1252 int err, was_fpu_owner, prior_msa;
1253
1254 /*
1255 * If an FP mode switch is currently underway, wait for it to
1256 * complete before proceeding.
1257 */
1258 wait_on_atomic_t(&current->mm->context.fp_mode_switching,
1259 wait_on_fp_mode_switch, TASK_KILLABLE);
1260
1261 if (!used_math()) {
1262 /* First time FP context user. */
1263 preempt_disable();
1264 err = init_fpu();
1265 if (msa && !err) {
1266 enable_msa();
1267 init_msa_upper();
1268 set_thread_flag(TIF_USEDMSA);
1269 set_thread_flag(TIF_MSA_CTX_LIVE);
1270 }
1271 preempt_enable();
1272 if (!err)
1273 set_used_math();
1274 return err;
1275 }
1276
1277 /*
1278 * This task has formerly used the FP context.
1279 *
1280 * If this thread has no live MSA vector context then we can simply
1281 * restore the scalar FP context. If it has live MSA vector context
1282 * (that is, it has or may have used MSA since last performing a
1283 * function call) then we'll need to restore the vector context. This
1284 * applies even if we're currently only executing a scalar FP
1285 * instruction. This is because if we were to later execute an MSA
1286 * instruction then we'd either have to:
1287 *
1288 * - Restore the vector context & clobber any registers modified by
1289 * scalar FP instructions between now & then.
1290 *
1291 * or
1292 *
1293 * - Not restore the vector context & lose the most significant bits
1294 * of all vector registers.
1295 *
1296 * Neither of those options is acceptable. We cannot restore the least
1297 * significant bits of the registers now & only restore the most
1298 * significant bits later because the most significant bits of any
1299 * vector registers whose aliased FP register is modified now will have
1300 * been zeroed. We'd have no way to know that when restoring the vector
1301 * context & thus may load an outdated value for the most significant
1302 * bits of a vector register.
1303 */
1304 if (!msa && !thread_msa_context_live())
1305 return own_fpu(1);
1306
1307 /*
1308 * This task is using or has previously used MSA. Thus we require
1309 * that Status.FR == 1.
1310 */
1311 preempt_disable();
1312 was_fpu_owner = is_fpu_owner();
1313 err = own_fpu_inatomic(0);
1314 if (err)
1315 goto out;
1316
1317 enable_msa();
1318 write_msa_csr(current->thread.fpu.msacsr);
1319 set_thread_flag(TIF_USEDMSA);
1320
1321 /*
1322 * If this is the first time that the task is using MSA and it has
1323 * previously used scalar FP in this time slice then we already nave
1324 * FP context which we shouldn't clobber. We do however need to clear
1325 * the upper 64b of each vector register so that this task has no
1326 * opportunity to see data left behind by another.
1327 */
1328 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1329 if (!prior_msa && was_fpu_owner) {
1330 init_msa_upper();
1331
1332 goto out;
1333 }
1334
1335 if (!prior_msa) {
1336 /*
1337 * Restore the least significant 64b of each vector register
1338 * from the existing scalar FP context.
1339 */
1340 _restore_fp(current);
1341
1342 /*
1343 * The task has not formerly used MSA, so clear the upper 64b
1344 * of each vector register such that it cannot see data left
1345 * behind by another task.
1346 */
1347 init_msa_upper();
1348 } else {
1349 /* We need to restore the vector context. */
1350 restore_msa(current);
1351
1352 /* Restore the scalar FP control & status register */
1353 if (!was_fpu_owner)
1354 write_32bit_cp1_register(CP1_STATUS,
1355 current->thread.fpu.fcr31);
1356 }
1357
1358 out:
1359 preempt_enable();
1360
1361 return 0;
1362 }
1363
1364 asmlinkage void do_cpu(struct pt_regs *regs)
1365 {
1366 enum ctx_state prev_state;
1367 unsigned int __user *epc;
1368 unsigned long old_epc, old31;
1369 void __user *fault_addr;
1370 unsigned int opcode;
1371 unsigned long fcr31;
1372 unsigned int cpid;
1373 int status, err;
1374 int sig;
1375
1376 prev_state = exception_enter();
1377 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1378
1379 if (cpid != 2)
1380 die_if_kernel("do_cpu invoked from kernel context!", regs);
1381
1382 switch (cpid) {
1383 case 0:
1384 epc = (unsigned int __user *)exception_epc(regs);
1385 old_epc = regs->cp0_epc;
1386 old31 = regs->regs[31];
1387 opcode = 0;
1388 status = -1;
1389
1390 if (unlikely(compute_return_epc(regs) < 0))
1391 break;
1392
1393 if (!get_isa16_mode(regs->cp0_epc)) {
1394 if (unlikely(get_user(opcode, epc) < 0))
1395 status = SIGSEGV;
1396
1397 if (!cpu_has_llsc && status < 0)
1398 status = simulate_llsc(regs, opcode);
1399 }
1400
1401 if (status < 0)
1402 status = SIGILL;
1403
1404 if (unlikely(status > 0)) {
1405 regs->cp0_epc = old_epc; /* Undo skip-over. */
1406 regs->regs[31] = old31;
1407 force_sig(status, current);
1408 }
1409
1410 break;
1411
1412 case 3:
1413 /*
1414 * The COP3 opcode space and consequently the CP0.Status.CU3
1415 * bit and the CP0.Cause.CE=3 encoding have been removed as
1416 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
1417 * up the space has been reused for COP1X instructions, that
1418 * are enabled by the CP0.Status.CU1 bit and consequently
1419 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
1420 * exceptions. Some FPU-less processors that implement one
1421 * of these ISAs however use this code erroneously for COP1X
1422 * instructions. Therefore we redirect this trap to the FP
1423 * emulator too.
1424 */
1425 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
1426 force_sig(SIGILL, current);
1427 break;
1428 }
1429 /* Fall through. */
1430
1431 case 1:
1432 err = enable_restore_fp_context(0);
1433
1434 if (raw_cpu_has_fpu && !err)
1435 break;
1436
1437 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 0,
1438 &fault_addr);
1439
1440 /*
1441 * We can't allow the emulated instruction to leave
1442 * any enabled Cause bits set in $fcr31.
1443 */
1444 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
1445 current->thread.fpu.fcr31 &= ~fcr31;
1446
1447 /* Send a signal if required. */
1448 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
1449 mt_ase_fp_affinity();
1450
1451 break;
1452
1453 case 2:
1454 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1455 break;
1456 }
1457
1458 exception_exit(prev_state);
1459 }
1460
1461 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
1462 {
1463 enum ctx_state prev_state;
1464
1465 prev_state = exception_enter();
1466 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1467 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
1468 current->thread.trap_nr, SIGFPE) == NOTIFY_STOP)
1469 goto out;
1470
1471 /* Clear MSACSR.Cause before enabling interrupts */
1472 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
1473 local_irq_enable();
1474
1475 die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
1476 force_sig(SIGFPE, current);
1477 out:
1478 exception_exit(prev_state);
1479 }
1480
1481 asmlinkage void do_msa(struct pt_regs *regs)
1482 {
1483 enum ctx_state prev_state;
1484 int err;
1485
1486 prev_state = exception_enter();
1487
1488 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
1489 force_sig(SIGILL, current);
1490 goto out;
1491 }
1492
1493 die_if_kernel("do_msa invoked from kernel context!", regs);
1494
1495 err = enable_restore_fp_context(1);
1496 if (err)
1497 force_sig(SIGILL, current);
1498 out:
1499 exception_exit(prev_state);
1500 }
1501
1502 asmlinkage void do_mdmx(struct pt_regs *regs)
1503 {
1504 enum ctx_state prev_state;
1505
1506 prev_state = exception_enter();
1507 force_sig(SIGILL, current);
1508 exception_exit(prev_state);
1509 }
1510
1511 /*
1512 * Called with interrupts disabled.
1513 */
1514 asmlinkage void do_watch(struct pt_regs *regs)
1515 {
1516 siginfo_t info = { .si_signo = SIGTRAP, .si_code = TRAP_HWBKPT };
1517 enum ctx_state prev_state;
1518
1519 prev_state = exception_enter();
1520 /*
1521 * Clear WP (bit 22) bit of cause register so we don't loop
1522 * forever.
1523 */
1524 clear_c0_cause(CAUSEF_WP);
1525
1526 /*
1527 * If the current thread has the watch registers loaded, save
1528 * their values and send SIGTRAP. Otherwise another thread
1529 * left the registers set, clear them and continue.
1530 */
1531 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1532 mips_read_watch_registers();
1533 local_irq_enable();
1534 force_sig_info(SIGTRAP, &info, current);
1535 } else {
1536 mips_clear_watch_registers();
1537 local_irq_enable();
1538 }
1539 exception_exit(prev_state);
1540 }
1541
1542 asmlinkage void do_mcheck(struct pt_regs *regs)
1543 {
1544 int multi_match = regs->cp0_status & ST0_TS;
1545 enum ctx_state prev_state;
1546 mm_segment_t old_fs = get_fs();
1547
1548 prev_state = exception_enter();
1549 show_regs(regs);
1550
1551 if (multi_match) {
1552 dump_tlb_regs();
1553 pr_info("\n");
1554 dump_tlb_all();
1555 }
1556
1557 if (!user_mode(regs))
1558 set_fs(KERNEL_DS);
1559
1560 show_code((unsigned int __user *) regs->cp0_epc);
1561
1562 set_fs(old_fs);
1563
1564 /*
1565 * Some chips may have other causes of machine check (e.g. SB1
1566 * graduation timer)
1567 */
1568 panic("Caught Machine Check exception - %scaused by multiple "
1569 "matching entries in the TLB.",
1570 (multi_match) ? "" : "not ");
1571 }
1572
1573 asmlinkage void do_mt(struct pt_regs *regs)
1574 {
1575 int subcode;
1576
1577 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1578 >> VPECONTROL_EXCPT_SHIFT;
1579 switch (subcode) {
1580 case 0:
1581 printk(KERN_DEBUG "Thread Underflow\n");
1582 break;
1583 case 1:
1584 printk(KERN_DEBUG "Thread Overflow\n");
1585 break;
1586 case 2:
1587 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1588 break;
1589 case 3:
1590 printk(KERN_DEBUG "Gating Storage Exception\n");
1591 break;
1592 case 4:
1593 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1594 break;
1595 case 5:
1596 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1597 break;
1598 default:
1599 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1600 subcode);
1601 break;
1602 }
1603 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1604
1605 force_sig(SIGILL, current);
1606 }
1607
1608
1609 asmlinkage void do_dsp(struct pt_regs *regs)
1610 {
1611 if (cpu_has_dsp)
1612 panic("Unexpected DSP exception");
1613
1614 force_sig(SIGILL, current);
1615 }
1616
1617 asmlinkage void do_reserved(struct pt_regs *regs)
1618 {
1619 /*
1620 * Game over - no way to handle this if it ever occurs. Most probably
1621 * caused by a new unknown cpu type or after another deadly
1622 * hard/software error.
1623 */
1624 show_regs(regs);
1625 panic("Caught reserved exception %ld - should not happen.",
1626 (regs->cp0_cause & 0x7f) >> 2);
1627 }
1628
1629 static int __initdata l1parity = 1;
1630 static int __init nol1parity(char *s)
1631 {
1632 l1parity = 0;
1633 return 1;
1634 }
1635 __setup("nol1par", nol1parity);
1636 static int __initdata l2parity = 1;
1637 static int __init nol2parity(char *s)
1638 {
1639 l2parity = 0;
1640 return 1;
1641 }
1642 __setup("nol2par", nol2parity);
1643
1644 /*
1645 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1646 * it different ways.
1647 */
1648 static inline void parity_protection_init(void)
1649 {
1650 #define ERRCTL_PE 0x80000000
1651 #define ERRCTL_L2P 0x00800000
1652
1653 if (mips_cm_revision() >= CM_REV_CM3) {
1654 ulong gcr_ectl, cp0_ectl;
1655
1656 /*
1657 * With CM3 systems we need to ensure that the L1 & L2
1658 * parity enables are set to the same value, since this
1659 * is presumed by the hardware engineers.
1660 *
1661 * If the user disabled either of L1 or L2 ECC checking,
1662 * disable both.
1663 */
1664 l1parity &= l2parity;
1665 l2parity &= l1parity;
1666
1667 /* Probe L1 ECC support */
1668 cp0_ectl = read_c0_ecc();
1669 write_c0_ecc(cp0_ectl | ERRCTL_PE);
1670 back_to_back_c0_hazard();
1671 cp0_ectl = read_c0_ecc();
1672
1673 /* Probe L2 ECC support */
1674 gcr_ectl = read_gcr_err_control();
1675
1676 if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT_MSK) ||
1677 !(cp0_ectl & ERRCTL_PE)) {
1678 /*
1679 * One of L1 or L2 ECC checking isn't supported,
1680 * so we cannot enable either.
1681 */
1682 l1parity = l2parity = 0;
1683 }
1684
1685 /* Configure L1 ECC checking */
1686 if (l1parity)
1687 cp0_ectl |= ERRCTL_PE;
1688 else
1689 cp0_ectl &= ~ERRCTL_PE;
1690 write_c0_ecc(cp0_ectl);
1691 back_to_back_c0_hazard();
1692 WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity);
1693
1694 /* Configure L2 ECC checking */
1695 if (l2parity)
1696 gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN_MSK;
1697 else
1698 gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN_MSK;
1699 write_gcr_err_control(gcr_ectl);
1700 gcr_ectl = read_gcr_err_control();
1701 gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN_MSK;
1702 WARN_ON(!!gcr_ectl != l2parity);
1703
1704 pr_info("Cache parity protection %sabled\n",
1705 l1parity ? "en" : "dis");
1706 return;
1707 }
1708
1709 switch (current_cpu_type()) {
1710 case CPU_24K:
1711 case CPU_34K:
1712 case CPU_74K:
1713 case CPU_1004K:
1714 case CPU_1074K:
1715 case CPU_INTERAPTIV:
1716 case CPU_PROAPTIV:
1717 case CPU_P5600:
1718 case CPU_QEMU_GENERIC:
1719 case CPU_P6600:
1720 {
1721 unsigned long errctl;
1722 unsigned int l1parity_present, l2parity_present;
1723
1724 errctl = read_c0_ecc();
1725 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1726
1727 /* probe L1 parity support */
1728 write_c0_ecc(errctl | ERRCTL_PE);
1729 back_to_back_c0_hazard();
1730 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1731
1732 /* probe L2 parity support */
1733 write_c0_ecc(errctl|ERRCTL_L2P);
1734 back_to_back_c0_hazard();
1735 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1736
1737 if (l1parity_present && l2parity_present) {
1738 if (l1parity)
1739 errctl |= ERRCTL_PE;
1740 if (l1parity ^ l2parity)
1741 errctl |= ERRCTL_L2P;
1742 } else if (l1parity_present) {
1743 if (l1parity)
1744 errctl |= ERRCTL_PE;
1745 } else if (l2parity_present) {
1746 if (l2parity)
1747 errctl |= ERRCTL_L2P;
1748 } else {
1749 /* No parity available */
1750 }
1751
1752 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1753
1754 write_c0_ecc(errctl);
1755 back_to_back_c0_hazard();
1756 errctl = read_c0_ecc();
1757 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1758
1759 if (l1parity_present)
1760 printk(KERN_INFO "Cache parity protection %sabled\n",
1761 (errctl & ERRCTL_PE) ? "en" : "dis");
1762
1763 if (l2parity_present) {
1764 if (l1parity_present && l1parity)
1765 errctl ^= ERRCTL_L2P;
1766 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1767 (errctl & ERRCTL_L2P) ? "en" : "dis");
1768 }
1769 }
1770 break;
1771
1772 case CPU_5KC:
1773 case CPU_5KE:
1774 case CPU_LOONGSON1:
1775 write_c0_ecc(0x80000000);
1776 back_to_back_c0_hazard();
1777 /* Set the PE bit (bit 31) in the c0_errctl register. */
1778 printk(KERN_INFO "Cache parity protection %sabled\n",
1779 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1780 break;
1781 case CPU_20KC:
1782 case CPU_25KF:
1783 /* Clear the DE bit (bit 16) in the c0_status register. */
1784 printk(KERN_INFO "Enable cache parity protection for "
1785 "MIPS 20KC/25KF CPUs.\n");
1786 clear_c0_status(ST0_DE);
1787 break;
1788 default:
1789 break;
1790 }
1791 }
1792
1793 asmlinkage void cache_parity_error(void)
1794 {
1795 const int field = 2 * sizeof(unsigned long);
1796 unsigned int reg_val;
1797
1798 /* For the moment, report the problem and hang. */
1799 printk("Cache error exception:\n");
1800 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1801 reg_val = read_c0_cacheerr();
1802 printk("c0_cacheerr == %08x\n", reg_val);
1803
1804 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1805 reg_val & (1<<30) ? "secondary" : "primary",
1806 reg_val & (1<<31) ? "data" : "insn");
1807 if ((cpu_has_mips_r2_r6) &&
1808 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1809 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1810 reg_val & (1<<29) ? "ED " : "",
1811 reg_val & (1<<28) ? "ET " : "",
1812 reg_val & (1<<27) ? "ES " : "",
1813 reg_val & (1<<26) ? "EE " : "",
1814 reg_val & (1<<25) ? "EB " : "",
1815 reg_val & (1<<24) ? "EI " : "",
1816 reg_val & (1<<23) ? "E1 " : "",
1817 reg_val & (1<<22) ? "E0 " : "");
1818 } else {
1819 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1820 reg_val & (1<<29) ? "ED " : "",
1821 reg_val & (1<<28) ? "ET " : "",
1822 reg_val & (1<<26) ? "EE " : "",
1823 reg_val & (1<<25) ? "EB " : "",
1824 reg_val & (1<<24) ? "EI " : "",
1825 reg_val & (1<<23) ? "E1 " : "",
1826 reg_val & (1<<22) ? "E0 " : "");
1827 }
1828 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1829
1830 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1831 if (reg_val & (1<<22))
1832 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1833
1834 if (reg_val & (1<<23))
1835 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1836 #endif
1837
1838 panic("Can't handle the cache error!");
1839 }
1840
1841 asmlinkage void do_ftlb(void)
1842 {
1843 const int field = 2 * sizeof(unsigned long);
1844 unsigned int reg_val;
1845
1846 /* For the moment, report the problem and hang. */
1847 if ((cpu_has_mips_r2_r6) &&
1848 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) ||
1849 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) {
1850 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1851 read_c0_ecc());
1852 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1853 reg_val = read_c0_cacheerr();
1854 pr_err("c0_cacheerr == %08x\n", reg_val);
1855
1856 if ((reg_val & 0xc0000000) == 0xc0000000) {
1857 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1858 } else {
1859 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1860 reg_val & (1<<30) ? "secondary" : "primary",
1861 reg_val & (1<<31) ? "data" : "insn");
1862 }
1863 } else {
1864 pr_err("FTLB error exception\n");
1865 }
1866 /* Just print the cacheerr bits for now */
1867 cache_parity_error();
1868 }
1869
1870 /*
1871 * SDBBP EJTAG debug exception handler.
1872 * We skip the instruction and return to the next instruction.
1873 */
1874 void ejtag_exception_handler(struct pt_regs *regs)
1875 {
1876 const int field = 2 * sizeof(unsigned long);
1877 unsigned long depc, old_epc, old_ra;
1878 unsigned int debug;
1879
1880 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1881 depc = read_c0_depc();
1882 debug = read_c0_debug();
1883 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1884 if (debug & 0x80000000) {
1885 /*
1886 * In branch delay slot.
1887 * We cheat a little bit here and use EPC to calculate the
1888 * debug return address (DEPC). EPC is restored after the
1889 * calculation.
1890 */
1891 old_epc = regs->cp0_epc;
1892 old_ra = regs->regs[31];
1893 regs->cp0_epc = depc;
1894 compute_return_epc(regs);
1895 depc = regs->cp0_epc;
1896 regs->cp0_epc = old_epc;
1897 regs->regs[31] = old_ra;
1898 } else
1899 depc += 4;
1900 write_c0_depc(depc);
1901
1902 #if 0
1903 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1904 write_c0_debug(debug | 0x100);
1905 #endif
1906 }
1907
1908 /*
1909 * NMI exception handler.
1910 * No lock; only written during early bootup by CPU 0.
1911 */
1912 static RAW_NOTIFIER_HEAD(nmi_chain);
1913
1914 int register_nmi_notifier(struct notifier_block *nb)
1915 {
1916 return raw_notifier_chain_register(&nmi_chain, nb);
1917 }
1918
1919 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1920 {
1921 char str[100];
1922
1923 nmi_enter();
1924 raw_notifier_call_chain(&nmi_chain, 0, regs);
1925 bust_spinlocks(1);
1926 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1927 smp_processor_id(), regs->cp0_epc);
1928 regs->cp0_epc = read_c0_errorepc();
1929 die(str, regs);
1930 nmi_exit();
1931 }
1932
1933 #define VECTORSPACING 0x100 /* for EI/VI mode */
1934
1935 unsigned long ebase;
1936 EXPORT_SYMBOL_GPL(ebase);
1937 unsigned long exception_handlers[32];
1938 unsigned long vi_handlers[64];
1939
1940 void __init *set_except_vector(int n, void *addr)
1941 {
1942 unsigned long handler = (unsigned long) addr;
1943 unsigned long old_handler;
1944
1945 #ifdef CONFIG_CPU_MICROMIPS
1946 /*
1947 * Only the TLB handlers are cache aligned with an even
1948 * address. All other handlers are on an odd address and
1949 * require no modification. Otherwise, MIPS32 mode will
1950 * be entered when handling any TLB exceptions. That
1951 * would be bad...since we must stay in microMIPS mode.
1952 */
1953 if (!(handler & 0x1))
1954 handler |= 1;
1955 #endif
1956 old_handler = xchg(&exception_handlers[n], handler);
1957
1958 if (n == 0 && cpu_has_divec) {
1959 #ifdef CONFIG_CPU_MICROMIPS
1960 unsigned long jump_mask = ~((1 << 27) - 1);
1961 #else
1962 unsigned long jump_mask = ~((1 << 28) - 1);
1963 #endif
1964 u32 *buf = (u32 *)(ebase + 0x200);
1965 unsigned int k0 = 26;
1966 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1967 uasm_i_j(&buf, handler & ~jump_mask);
1968 uasm_i_nop(&buf);
1969 } else {
1970 UASM_i_LA(&buf, k0, handler);
1971 uasm_i_jr(&buf, k0);
1972 uasm_i_nop(&buf);
1973 }
1974 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1975 }
1976 return (void *)old_handler;
1977 }
1978
1979 static void do_default_vi(void)
1980 {
1981 show_regs(get_irq_regs());
1982 panic("Caught unexpected vectored interrupt.");
1983 }
1984
1985 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1986 {
1987 unsigned long handler;
1988 unsigned long old_handler = vi_handlers[n];
1989 int srssets = current_cpu_data.srsets;
1990 u16 *h;
1991 unsigned char *b;
1992
1993 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1994
1995 if (addr == NULL) {
1996 handler = (unsigned long) do_default_vi;
1997 srs = 0;
1998 } else
1999 handler = (unsigned long) addr;
2000 vi_handlers[n] = handler;
2001
2002 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
2003
2004 if (srs >= srssets)
2005 panic("Shadow register set %d not supported", srs);
2006
2007 if (cpu_has_veic) {
2008 if (board_bind_eic_interrupt)
2009 board_bind_eic_interrupt(n, srs);
2010 } else if (cpu_has_vint) {
2011 /* SRSMap is only defined if shadow sets are implemented */
2012 if (srssets > 1)
2013 change_c0_srsmap(0xf << n*4, srs << n*4);
2014 }
2015
2016 if (srs == 0) {
2017 /*
2018 * If no shadow set is selected then use the default handler
2019 * that does normal register saving and standard interrupt exit
2020 */
2021 extern char except_vec_vi, except_vec_vi_lui;
2022 extern char except_vec_vi_ori, except_vec_vi_end;
2023 extern char rollback_except_vec_vi;
2024 char *vec_start = using_rollback_handler() ?
2025 &rollback_except_vec_vi : &except_vec_vi;
2026 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
2027 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
2028 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
2029 #else
2030 const int lui_offset = &except_vec_vi_lui - vec_start;
2031 const int ori_offset = &except_vec_vi_ori - vec_start;
2032 #endif
2033 const int handler_len = &except_vec_vi_end - vec_start;
2034
2035 if (handler_len > VECTORSPACING) {
2036 /*
2037 * Sigh... panicing won't help as the console
2038 * is probably not configured :(
2039 */
2040 panic("VECTORSPACING too small");
2041 }
2042
2043 set_handler(((unsigned long)b - ebase), vec_start,
2044 #ifdef CONFIG_CPU_MICROMIPS
2045 (handler_len - 1));
2046 #else
2047 handler_len);
2048 #endif
2049 h = (u16 *)(b + lui_offset);
2050 *h = (handler >> 16) & 0xffff;
2051 h = (u16 *)(b + ori_offset);
2052 *h = (handler & 0xffff);
2053 local_flush_icache_range((unsigned long)b,
2054 (unsigned long)(b+handler_len));
2055 }
2056 else {
2057 /*
2058 * In other cases jump directly to the interrupt handler. It
2059 * is the handler's responsibility to save registers if required
2060 * (eg hi/lo) and return from the exception using "eret".
2061 */
2062 u32 insn;
2063
2064 h = (u16 *)b;
2065 /* j handler */
2066 #ifdef CONFIG_CPU_MICROMIPS
2067 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
2068 #else
2069 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
2070 #endif
2071 h[0] = (insn >> 16) & 0xffff;
2072 h[1] = insn & 0xffff;
2073 h[2] = 0;
2074 h[3] = 0;
2075 local_flush_icache_range((unsigned long)b,
2076 (unsigned long)(b+8));
2077 }
2078
2079 return (void *)old_handler;
2080 }
2081
2082 void *set_vi_handler(int n, vi_handler_t addr)
2083 {
2084 return set_vi_srs_handler(n, addr, 0);
2085 }
2086
2087 extern void tlb_init(void);
2088
2089 /*
2090 * Timer interrupt
2091 */
2092 int cp0_compare_irq;
2093 EXPORT_SYMBOL_GPL(cp0_compare_irq);
2094 int cp0_compare_irq_shift;
2095
2096 /*
2097 * Performance counter IRQ or -1 if shared with timer
2098 */
2099 int cp0_perfcount_irq;
2100 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
2101
2102 /*
2103 * Fast debug channel IRQ or -1 if not present
2104 */
2105 int cp0_fdc_irq;
2106 EXPORT_SYMBOL_GPL(cp0_fdc_irq);
2107
2108 static int noulri;
2109
2110 static int __init ulri_disable(char *s)
2111 {
2112 pr_info("Disabling ulri\n");
2113 noulri = 1;
2114
2115 return 1;
2116 }
2117 __setup("noulri", ulri_disable);
2118
2119 /* configure STATUS register */
2120 static void configure_status(void)
2121 {
2122 /*
2123 * Disable coprocessors and select 32-bit or 64-bit addressing
2124 * and the 16/32 or 32/32 FPR register model. Reset the BEV
2125 * flag that some firmware may have left set and the TS bit (for
2126 * IP27). Set XX for ISA IV code to work.
2127 */
2128 unsigned int status_set = ST0_CU0;
2129 #ifdef CONFIG_64BIT
2130 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
2131 #endif
2132 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
2133 status_set |= ST0_XX;
2134 if (cpu_has_dsp)
2135 status_set |= ST0_MX;
2136
2137 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
2138 status_set);
2139 }
2140
2141 unsigned int hwrena;
2142 EXPORT_SYMBOL_GPL(hwrena);
2143
2144 /* configure HWRENA register */
2145 static void configure_hwrena(void)
2146 {
2147 hwrena = cpu_hwrena_impl_bits;
2148
2149 if (cpu_has_mips_r2_r6)
2150 hwrena |= MIPS_HWRENA_CPUNUM |
2151 MIPS_HWRENA_SYNCISTEP |
2152 MIPS_HWRENA_CC |
2153 MIPS_HWRENA_CCRES;
2154
2155 if (!noulri && cpu_has_userlocal)
2156 hwrena |= MIPS_HWRENA_ULR;
2157
2158 if (hwrena)
2159 write_c0_hwrena(hwrena);
2160 }
2161
2162 static void configure_exception_vector(void)
2163 {
2164 if (cpu_has_veic || cpu_has_vint) {
2165 unsigned long sr = set_c0_status(ST0_BEV);
2166 /* If available, use WG to set top bits of EBASE */
2167 if (cpu_has_ebase_wg) {
2168 #ifdef CONFIG_64BIT
2169 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2170 #else
2171 write_c0_ebase(ebase | MIPS_EBASE_WG);
2172 #endif
2173 }
2174 write_c0_ebase(ebase);
2175 write_c0_status(sr);
2176 /* Setting vector spacing enables EI/VI mode */
2177 change_c0_intctl(0x3e0, VECTORSPACING);
2178 }
2179 if (cpu_has_divec) {
2180 if (cpu_has_mipsmt) {
2181 unsigned int vpflags = dvpe();
2182 set_c0_cause(CAUSEF_IV);
2183 evpe(vpflags);
2184 } else
2185 set_c0_cause(CAUSEF_IV);
2186 }
2187 }
2188
2189 void per_cpu_trap_init(bool is_boot_cpu)
2190 {
2191 unsigned int cpu = smp_processor_id();
2192
2193 configure_status();
2194 configure_hwrena();
2195
2196 configure_exception_vector();
2197
2198 /*
2199 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2200 *
2201 * o read IntCtl.IPTI to determine the timer interrupt
2202 * o read IntCtl.IPPCI to determine the performance counter interrupt
2203 * o read IntCtl.IPFDC to determine the fast debug channel interrupt
2204 */
2205 if (cpu_has_mips_r2_r6) {
2206 /*
2207 * We shouldn't trust a secondary core has a sane EBASE register
2208 * so use the one calculated by the boot CPU.
2209 */
2210 if (!is_boot_cpu) {
2211 /* If available, use WG to set top bits of EBASE */
2212 if (cpu_has_ebase_wg) {
2213 #ifdef CONFIG_64BIT
2214 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2215 #else
2216 write_c0_ebase(ebase | MIPS_EBASE_WG);
2217 #endif
2218 }
2219 write_c0_ebase(ebase);
2220 }
2221
2222 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2223 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2224 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
2225 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
2226 if (!cp0_fdc_irq)
2227 cp0_fdc_irq = -1;
2228
2229 } else {
2230 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
2231 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
2232 cp0_perfcount_irq = -1;
2233 cp0_fdc_irq = -1;
2234 }
2235
2236 if (!cpu_data[cpu].asid_cache)
2237 cpu_data[cpu].asid_cache = asid_first_version(cpu);
2238
2239 mmgrab(&init_mm);
2240 current->active_mm = &init_mm;
2241 BUG_ON(current->mm);
2242 enter_lazy_tlb(&init_mm, current);
2243
2244 /* Boot CPU's cache setup in setup_arch(). */
2245 if (!is_boot_cpu)
2246 cpu_cache_init();
2247 tlb_init();
2248 TLBMISS_HANDLER_SETUP();
2249 }
2250
2251 /* Install CPU exception handler */
2252 void set_handler(unsigned long offset, void *addr, unsigned long size)
2253 {
2254 #ifdef CONFIG_CPU_MICROMIPS
2255 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
2256 #else
2257 memcpy((void *)(ebase + offset), addr, size);
2258 #endif
2259 local_flush_icache_range(ebase + offset, ebase + offset + size);
2260 }
2261
2262 static const char panic_null_cerr[] =
2263 "Trying to set NULL cache error exception handler\n";
2264
2265 /*
2266 * Install uncached CPU exception handler.
2267 * This is suitable only for the cache error exception which is the only
2268 * exception handler that is being run uncached.
2269 */
2270 void set_uncached_handler(unsigned long offset, void *addr,
2271 unsigned long size)
2272 {
2273 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
2274
2275 if (!addr)
2276 panic(panic_null_cerr);
2277
2278 memcpy((void *)(uncached_ebase + offset), addr, size);
2279 }
2280
2281 static int __initdata rdhwr_noopt;
2282 static int __init set_rdhwr_noopt(char *str)
2283 {
2284 rdhwr_noopt = 1;
2285 return 1;
2286 }
2287
2288 __setup("rdhwr_noopt", set_rdhwr_noopt);
2289
2290 void __init trap_init(void)
2291 {
2292 extern char except_vec3_generic;
2293 extern char except_vec4;
2294 extern char except_vec3_r4000;
2295 unsigned long i;
2296
2297 check_wait();
2298
2299 if (cpu_has_veic || cpu_has_vint) {
2300 unsigned long size = 0x200 + VECTORSPACING*64;
2301 phys_addr_t ebase_pa;
2302
2303 ebase = (unsigned long)
2304 __alloc_bootmem(size, 1 << fls(size), 0);
2305
2306 /*
2307 * Try to ensure ebase resides in KSeg0 if possible.
2308 *
2309 * It shouldn't generally be in XKPhys on MIPS64 to avoid
2310 * hitting a poorly defined exception base for Cache Errors.
2311 * The allocation is likely to be in the low 512MB of physical,
2312 * in which case we should be able to convert to KSeg0.
2313 *
2314 * EVA is special though as it allows segments to be rearranged
2315 * and to become uncached during cache error handling.
2316 */
2317 ebase_pa = __pa(ebase);
2318 if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
2319 ebase = CKSEG0ADDR(ebase_pa);
2320 } else {
2321 ebase = CAC_BASE;
2322
2323 if (cpu_has_mips_r2_r6) {
2324 if (cpu_has_ebase_wg) {
2325 #ifdef CONFIG_64BIT
2326 ebase = (read_c0_ebase_64() & ~0xfff);
2327 #else
2328 ebase = (read_c0_ebase() & ~0xfff);
2329 #endif
2330 } else {
2331 ebase += (read_c0_ebase() & 0x3ffff000);
2332 }
2333 }
2334 }
2335
2336 if (cpu_has_mmips) {
2337 unsigned int config3 = read_c0_config3();
2338
2339 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
2340 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
2341 else
2342 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
2343 }
2344
2345 if (board_ebase_setup)
2346 board_ebase_setup();
2347 per_cpu_trap_init(true);
2348
2349 /*
2350 * Copy the generic exception handlers to their final destination.
2351 * This will be overridden later as suitable for a particular
2352 * configuration.
2353 */
2354 set_handler(0x180, &except_vec3_generic, 0x80);
2355
2356 /*
2357 * Setup default vectors
2358 */
2359 for (i = 0; i <= 31; i++)
2360 set_except_vector(i, handle_reserved);
2361
2362 /*
2363 * Copy the EJTAG debug exception vector handler code to it's final
2364 * destination.
2365 */
2366 if (cpu_has_ejtag && board_ejtag_handler_setup)
2367 board_ejtag_handler_setup();
2368
2369 /*
2370 * Only some CPUs have the watch exceptions.
2371 */
2372 if (cpu_has_watch)
2373 set_except_vector(EXCCODE_WATCH, handle_watch);
2374
2375 /*
2376 * Initialise interrupt handlers
2377 */
2378 if (cpu_has_veic || cpu_has_vint) {
2379 int nvec = cpu_has_veic ? 64 : 8;
2380 for (i = 0; i < nvec; i++)
2381 set_vi_handler(i, NULL);
2382 }
2383 else if (cpu_has_divec)
2384 set_handler(0x200, &except_vec4, 0x8);
2385
2386 /*
2387 * Some CPUs can enable/disable for cache parity detection, but does
2388 * it different ways.
2389 */
2390 parity_protection_init();
2391
2392 /*
2393 * The Data Bus Errors / Instruction Bus Errors are signaled
2394 * by external hardware. Therefore these two exceptions
2395 * may have board specific handlers.
2396 */
2397 if (board_be_init)
2398 board_be_init();
2399
2400 set_except_vector(EXCCODE_INT, using_rollback_handler() ?
2401 rollback_handle_int : handle_int);
2402 set_except_vector(EXCCODE_MOD, handle_tlbm);
2403 set_except_vector(EXCCODE_TLBL, handle_tlbl);
2404 set_except_vector(EXCCODE_TLBS, handle_tlbs);
2405
2406 set_except_vector(EXCCODE_ADEL, handle_adel);
2407 set_except_vector(EXCCODE_ADES, handle_ades);
2408
2409 set_except_vector(EXCCODE_IBE, handle_ibe);
2410 set_except_vector(EXCCODE_DBE, handle_dbe);
2411
2412 set_except_vector(EXCCODE_SYS, handle_sys);
2413 set_except_vector(EXCCODE_BP, handle_bp);
2414
2415 if (rdhwr_noopt)
2416 set_except_vector(EXCCODE_RI, handle_ri);
2417 else {
2418 if (cpu_has_vtag_icache)
2419 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
2420 else if (current_cpu_type() == CPU_LOONGSON3)
2421 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
2422 else
2423 set_except_vector(EXCCODE_RI, handle_ri_rdhwr);
2424 }
2425
2426 set_except_vector(EXCCODE_CPU, handle_cpu);
2427 set_except_vector(EXCCODE_OV, handle_ov);
2428 set_except_vector(EXCCODE_TR, handle_tr);
2429 set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe);
2430
2431 if (current_cpu_type() == CPU_R6000 ||
2432 current_cpu_type() == CPU_R6000A) {
2433 /*
2434 * The R6000 is the only R-series CPU that features a machine
2435 * check exception (similar to the R4000 cache error) and
2436 * unaligned ldc1/sdc1 exception. The handlers have not been
2437 * written yet. Well, anyway there is no R6000 machine on the
2438 * current list of targets for Linux/MIPS.
2439 * (Duh, crap, there is someone with a triple R6k machine)
2440 */
2441 //set_except_vector(14, handle_mc);
2442 //set_except_vector(15, handle_ndc);
2443 }
2444
2445
2446 if (board_nmi_handler_setup)
2447 board_nmi_handler_setup();
2448
2449 if (cpu_has_fpu && !cpu_has_nofpuex)
2450 set_except_vector(EXCCODE_FPE, handle_fpe);
2451
2452 set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
2453
2454 if (cpu_has_rixiex) {
2455 set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);
2456 set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);
2457 }
2458
2459 set_except_vector(EXCCODE_MSADIS, handle_msa);
2460 set_except_vector(EXCCODE_MDMX, handle_mdmx);
2461
2462 if (cpu_has_mcheck)
2463 set_except_vector(EXCCODE_MCHECK, handle_mcheck);
2464
2465 if (cpu_has_mipsmt)
2466 set_except_vector(EXCCODE_THREAD, handle_mt);
2467
2468 set_except_vector(EXCCODE_DSPDIS, handle_dsp);
2469
2470 if (board_cache_error_setup)
2471 board_cache_error_setup();
2472
2473 if (cpu_has_vce)
2474 /* Special exception: R4[04]00 uses also the divec space. */
2475 set_handler(0x180, &except_vec3_r4000, 0x100);
2476 else if (cpu_has_4kex)
2477 set_handler(0x180, &except_vec3_generic, 0x80);
2478 else
2479 set_handler(0x080, &except_vec3_generic, 0x80);
2480
2481 local_flush_icache_range(ebase, ebase + 0x400);
2482
2483 sort_extable(__start___dbe_table, __stop___dbe_table);
2484
2485 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
2486 }
2487
2488 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
2489 void *v)
2490 {
2491 switch (cmd) {
2492 case CPU_PM_ENTER_FAILED:
2493 case CPU_PM_EXIT:
2494 configure_status();
2495 configure_hwrena();
2496 configure_exception_vector();
2497
2498 /* Restore register with CPU number for TLB handlers */
2499 TLBMISS_HANDLER_RESTORE();
2500
2501 break;
2502 }
2503
2504 return NOTIFY_OK;
2505 }
2506
2507 static struct notifier_block trap_pm_notifier_block = {
2508 .notifier_call = trap_pm_notifier,
2509 };
2510
2511 static int __init trap_pm_init(void)
2512 {
2513 return cpu_pm_register_notifier(&trap_pm_notifier_block);
2514 }
2515 arch_initcall(trap_pm_init);
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