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FRV: Use generic show_interrupts()
[cris-mirror.git] / drivers / net / wireless / ath / ath9k / hw.c
blob338b07502f1adc5621c60815a8f5ce8c0e0345e6
1 /*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
20
21 #include "hw.h"
22 #include "hw-ops.h"
23 #include "rc.h"
24 #include "ar9003_mac.h"
25
26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
27
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
32
33 static int __init ath9k_init(void)
34 {
35 return 0;
36 }
37 module_init(ath9k_init);
38
39 static void __exit ath9k_exit(void)
40 {
41 return;
42 }
43 module_exit(ath9k_exit);
44
45 /* Private hardware callbacks */
46
47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48 {
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50 }
51
52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53 {
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55 }
56
57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
59 {
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
61 }
62
63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
64 {
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
66 return;
67
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
69 }
70
71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
72 {
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
78 }
79
80 /********************/
81 /* Helper Functions */
82 /********************/
83
84 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
85 {
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate;
89
90 if (!ah->curchan) /* should really check for CCK instead */
91 clockrate = ATH9K_CLOCK_RATE_CCK;
92 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
93 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
94 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
95 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
96 else
97 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
98
99 if (conf_is_ht40(conf))
100 clockrate *= 2;
101
102 common->clockrate = clockrate;
103 }
104
105 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
106 {
107 struct ath_common *common = ath9k_hw_common(ah);
108
109 return usecs * common->clockrate;
110 }
111
112 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
113 {
114 int i;
115
116 BUG_ON(timeout < AH_TIME_QUANTUM);
117
118 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
119 if ((REG_READ(ah, reg) & mask) == val)
120 return true;
121
122 udelay(AH_TIME_QUANTUM);
123 }
124
125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
126 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
127 timeout, reg, REG_READ(ah, reg), mask, val);
128
129 return false;
130 }
131 EXPORT_SYMBOL(ath9k_hw_wait);
132
133 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
134 {
135 u32 retval;
136 int i;
137
138 for (i = 0, retval = 0; i < n; i++) {
139 retval = (retval << 1) | (val & 1);
140 val >>= 1;
141 }
142 return retval;
143 }
144
145 bool ath9k_get_channel_edges(struct ath_hw *ah,
146 u16 flags, u16 *low,
147 u16 *high)
148 {
149 struct ath9k_hw_capabilities *pCap = &ah->caps;
150
151 if (flags & CHANNEL_5GHZ) {
152 *low = pCap->low_5ghz_chan;
153 *high = pCap->high_5ghz_chan;
154 return true;
155 }
156 if ((flags & CHANNEL_2GHZ)) {
157 *low = pCap->low_2ghz_chan;
158 *high = pCap->high_2ghz_chan;
159 return true;
160 }
161 return false;
162 }
163
164 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
165 u8 phy, int kbps,
166 u32 frameLen, u16 rateix,
167 bool shortPreamble)
168 {
169 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
170
171 if (kbps == 0)
172 return 0;
173
174 switch (phy) {
175 case WLAN_RC_PHY_CCK:
176 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
177 if (shortPreamble)
178 phyTime >>= 1;
179 numBits = frameLen << 3;
180 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
181 break;
182 case WLAN_RC_PHY_OFDM:
183 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
184 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
185 numBits = OFDM_PLCP_BITS + (frameLen << 3);
186 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
187 txTime = OFDM_SIFS_TIME_QUARTER
188 + OFDM_PREAMBLE_TIME_QUARTER
189 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
190 } else if (ah->curchan &&
191 IS_CHAN_HALF_RATE(ah->curchan)) {
192 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
193 numBits = OFDM_PLCP_BITS + (frameLen << 3);
194 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
195 txTime = OFDM_SIFS_TIME_HALF +
196 OFDM_PREAMBLE_TIME_HALF
197 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
198 } else {
199 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
200 numBits = OFDM_PLCP_BITS + (frameLen << 3);
201 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
202 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
203 + (numSymbols * OFDM_SYMBOL_TIME);
204 }
205 break;
206 default:
207 ath_err(ath9k_hw_common(ah),
208 "Unknown phy %u (rate ix %u)\n", phy, rateix);
209 txTime = 0;
210 break;
211 }
212
213 return txTime;
214 }
215 EXPORT_SYMBOL(ath9k_hw_computetxtime);
216
217 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
218 struct ath9k_channel *chan,
219 struct chan_centers *centers)
220 {
221 int8_t extoff;
222
223 if (!IS_CHAN_HT40(chan)) {
224 centers->ctl_center = centers->ext_center =
225 centers->synth_center = chan->channel;
226 return;
227 }
228
229 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
230 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
231 centers->synth_center =
232 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
233 extoff = 1;
234 } else {
235 centers->synth_center =
236 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
237 extoff = -1;
238 }
239
240 centers->ctl_center =
241 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
242 /* 25 MHz spacing is supported by hw but not on upper layers */
243 centers->ext_center =
244 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
245 }
246
247 /******************/
248 /* Chip Revisions */
249 /******************/
250
251 static void ath9k_hw_read_revisions(struct ath_hw *ah)
252 {
253 u32 val;
254
255 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
256
257 if (val == 0xFF) {
258 val = REG_READ(ah, AR_SREV);
259 ah->hw_version.macVersion =
260 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
261 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
262 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
263 } else {
264 if (!AR_SREV_9100(ah))
265 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
266
267 ah->hw_version.macRev = val & AR_SREV_REVISION;
268
269 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
270 ah->is_pciexpress = true;
271 }
272 }
273
274 /************************************/
275 /* HW Attach, Detach, Init Routines */
276 /************************************/
277
278 static void ath9k_hw_disablepcie(struct ath_hw *ah)
279 {
280 if (!AR_SREV_5416(ah))
281 return;
282
283 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
292
293 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
294 }
295
296 /* This should work for all families including legacy */
297 static bool ath9k_hw_chip_test(struct ath_hw *ah)
298 {
299 struct ath_common *common = ath9k_hw_common(ah);
300 u32 regAddr[2] = { AR_STA_ID0 };
301 u32 regHold[2];
302 static const u32 patternData[4] = {
303 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
304 };
305 int i, j, loop_max;
306
307 if (!AR_SREV_9300_20_OR_LATER(ah)) {
308 loop_max = 2;
309 regAddr[1] = AR_PHY_BASE + (8 << 2);
310 } else
311 loop_max = 1;
312
313 for (i = 0; i < loop_max; i++) {
314 u32 addr = regAddr[i];
315 u32 wrData, rdData;
316
317 regHold[i] = REG_READ(ah, addr);
318 for (j = 0; j < 0x100; j++) {
319 wrData = (j << 16) | j;
320 REG_WRITE(ah, addr, wrData);
321 rdData = REG_READ(ah, addr);
322 if (rdData != wrData) {
323 ath_err(common,
324 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
325 addr, wrData, rdData);
326 return false;
327 }
328 }
329 for (j = 0; j < 4; j++) {
330 wrData = patternData[j];
331 REG_WRITE(ah, addr, wrData);
332 rdData = REG_READ(ah, addr);
333 if (wrData != rdData) {
334 ath_err(common,
335 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
336 addr, wrData, rdData);
337 return false;
338 }
339 }
340 REG_WRITE(ah, regAddr[i], regHold[i]);
341 }
342 udelay(100);
343
344 return true;
345 }
346
347 static void ath9k_hw_init_config(struct ath_hw *ah)
348 {
349 int i;
350
351 ah->config.dma_beacon_response_time = 2;
352 ah->config.sw_beacon_response_time = 10;
353 ah->config.additional_swba_backoff = 0;
354 ah->config.ack_6mb = 0x0;
355 ah->config.cwm_ignore_extcca = 0;
356 ah->config.pcie_powersave_enable = 0;
357 ah->config.pcie_clock_req = 0;
358 ah->config.pcie_waen = 0;
359 ah->config.analog_shiftreg = 1;
360 ah->config.enable_ani = true;
361
362 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
363 ah->config.spurchans[i][0] = AR_NO_SPUR;
364 ah->config.spurchans[i][1] = AR_NO_SPUR;
365 }
366
367 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
368 ah->config.ht_enable = 1;
369 else
370 ah->config.ht_enable = 0;
371
372 /* PAPRD needs some more work to be enabled */
373 ah->config.paprd_disable = 1;
374
375 ah->config.rx_intr_mitigation = true;
376 ah->config.pcieSerDesWrite = true;
377
378 /*
379 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
380 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
381 * This means we use it for all AR5416 devices, and the few
382 * minor PCI AR9280 devices out there.
383 *
384 * Serialization is required because these devices do not handle
385 * well the case of two concurrent reads/writes due to the latency
386 * involved. During one read/write another read/write can be issued
387 * on another CPU while the previous read/write may still be working
388 * on our hardware, if we hit this case the hardware poops in a loop.
389 * We prevent this by serializing reads and writes.
390 *
391 * This issue is not present on PCI-Express devices or pre-AR5416
392 * devices (legacy, 802.11abg).
393 */
394 if (num_possible_cpus() > 1)
395 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
396 }
397
398 static void ath9k_hw_init_defaults(struct ath_hw *ah)
399 {
400 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
401
402 regulatory->country_code = CTRY_DEFAULT;
403 regulatory->power_limit = MAX_RATE_POWER;
404 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
405
406 ah->hw_version.magic = AR5416_MAGIC;
407 ah->hw_version.subvendorid = 0;
408
409 ah->atim_window = 0;
410 ah->sta_id1_defaults =
411 AR_STA_ID1_CRPT_MIC_ENABLE |
412 AR_STA_ID1_MCAST_KSRCH;
413 ah->enable_32kHz_clock = DONT_USE_32KHZ;
414 ah->slottime = 20;
415 ah->globaltxtimeout = (u32) -1;
416 ah->power_mode = ATH9K_PM_UNDEFINED;
417 }
418
419 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
420 {
421 struct ath_common *common = ath9k_hw_common(ah);
422 u32 sum;
423 int i;
424 u16 eeval;
425 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
426
427 sum = 0;
428 for (i = 0; i < 3; i++) {
429 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
430 sum += eeval;
431 common->macaddr[2 * i] = eeval >> 8;
432 common->macaddr[2 * i + 1] = eeval & 0xff;
433 }
434 if (sum == 0 || sum == 0xffff * 3)
435 return -EADDRNOTAVAIL;
436
437 return 0;
438 }
439
440 static int ath9k_hw_post_init(struct ath_hw *ah)
441 {
442 struct ath_common *common = ath9k_hw_common(ah);
443 int ecode;
444
445 if (common->bus_ops->ath_bus_type != ATH_USB) {
446 if (!ath9k_hw_chip_test(ah))
447 return -ENODEV;
448 }
449
450 if (!AR_SREV_9300_20_OR_LATER(ah)) {
451 ecode = ar9002_hw_rf_claim(ah);
452 if (ecode != 0)
453 return ecode;
454 }
455
456 ecode = ath9k_hw_eeprom_init(ah);
457 if (ecode != 0)
458 return ecode;
459
460 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
461 "Eeprom VER: %d, REV: %d\n",
462 ah->eep_ops->get_eeprom_ver(ah),
463 ah->eep_ops->get_eeprom_rev(ah));
464
465 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
466 if (ecode) {
467 ath_err(ath9k_hw_common(ah),
468 "Failed allocating banks for external radio\n");
469 ath9k_hw_rf_free_ext_banks(ah);
470 return ecode;
471 }
472
473 if (!AR_SREV_9100(ah)) {
474 ath9k_hw_ani_setup(ah);
475 ath9k_hw_ani_init(ah);
476 }
477
478 return 0;
479 }
480
481 static void ath9k_hw_attach_ops(struct ath_hw *ah)
482 {
483 if (AR_SREV_9300_20_OR_LATER(ah))
484 ar9003_hw_attach_ops(ah);
485 else
486 ar9002_hw_attach_ops(ah);
487 }
488
489 /* Called for all hardware families */
490 static int __ath9k_hw_init(struct ath_hw *ah)
491 {
492 struct ath_common *common = ath9k_hw_common(ah);
493 int r = 0;
494
495 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
496 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
497
498 ath9k_hw_read_revisions(ah);
499
500 /*
501 * Read back AR_WA into a permanent copy and set bits 14 and 17.
502 * We need to do this to avoid RMW of this register. We cannot
503 * read the reg when chip is asleep.
504 */
505 ah->WARegVal = REG_READ(ah, AR_WA);
506 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
507 AR_WA_ASPM_TIMER_BASED_DISABLE);
508
509 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
510 ath_err(common, "Couldn't reset chip\n");
511 return -EIO;
512 }
513
514 ath9k_hw_init_defaults(ah);
515 ath9k_hw_init_config(ah);
516
517 ath9k_hw_attach_ops(ah);
518
519 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
520 ath_err(common, "Couldn't wakeup chip\n");
521 return -EIO;
522 }
523
524 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
525 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
526 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
527 !ah->is_pciexpress)) {
528 ah->config.serialize_regmode =
529 SER_REG_MODE_ON;
530 } else {
531 ah->config.serialize_regmode =
532 SER_REG_MODE_OFF;
533 }
534 }
535
536 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
537 ah->config.serialize_regmode);
538
539 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
540 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
541 else
542 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
543
544 switch (ah->hw_version.macVersion) {
545 case AR_SREV_VERSION_5416_PCI:
546 case AR_SREV_VERSION_5416_PCIE:
547 case AR_SREV_VERSION_9160:
548 case AR_SREV_VERSION_9100:
549 case AR_SREV_VERSION_9280:
550 case AR_SREV_VERSION_9285:
551 case AR_SREV_VERSION_9287:
552 case AR_SREV_VERSION_9271:
553 case AR_SREV_VERSION_9300:
554 case AR_SREV_VERSION_9485:
555 break;
556 default:
557 ath_err(common,
558 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
559 ah->hw_version.macVersion, ah->hw_version.macRev);
560 return -EOPNOTSUPP;
561 }
562
563 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
564 ah->is_pciexpress = false;
565
566 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
567 ath9k_hw_init_cal_settings(ah);
568
569 ah->ani_function = ATH9K_ANI_ALL;
570 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
571 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
572 if (!AR_SREV_9300_20_OR_LATER(ah))
573 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
574
575 ath9k_hw_init_mode_regs(ah);
576
577
578 if (ah->is_pciexpress)
579 ath9k_hw_configpcipowersave(ah, 0, 0);
580 else
581 ath9k_hw_disablepcie(ah);
582
583 if (!AR_SREV_9300_20_OR_LATER(ah))
584 ar9002_hw_cck_chan14_spread(ah);
585
586 r = ath9k_hw_post_init(ah);
587 if (r)
588 return r;
589
590 ath9k_hw_init_mode_gain_regs(ah);
591 r = ath9k_hw_fill_cap_info(ah);
592 if (r)
593 return r;
594
595 r = ath9k_hw_init_macaddr(ah);
596 if (r) {
597 ath_err(common, "Failed to initialize MAC address\n");
598 return r;
599 }
600
601 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
602 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
603 else
604 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
605
606 ah->bb_watchdog_timeout_ms = 25;
607
608 common->state = ATH_HW_INITIALIZED;
609
610 return 0;
611 }
612
613 int ath9k_hw_init(struct ath_hw *ah)
614 {
615 int ret;
616 struct ath_common *common = ath9k_hw_common(ah);
617
618 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
619 switch (ah->hw_version.devid) {
620 case AR5416_DEVID_PCI:
621 case AR5416_DEVID_PCIE:
622 case AR5416_AR9100_DEVID:
623 case AR9160_DEVID_PCI:
624 case AR9280_DEVID_PCI:
625 case AR9280_DEVID_PCIE:
626 case AR9285_DEVID_PCIE:
627 case AR9287_DEVID_PCI:
628 case AR9287_DEVID_PCIE:
629 case AR2427_DEVID_PCIE:
630 case AR9300_DEVID_PCIE:
631 case AR9300_DEVID_AR9485_PCIE:
632 break;
633 default:
634 if (common->bus_ops->ath_bus_type == ATH_USB)
635 break;
636 ath_err(common, "Hardware device ID 0x%04x not supported\n",
637 ah->hw_version.devid);
638 return -EOPNOTSUPP;
639 }
640
641 ret = __ath9k_hw_init(ah);
642 if (ret) {
643 ath_err(common,
644 "Unable to initialize hardware; initialization status: %d\n",
645 ret);
646 return ret;
647 }
648
649 return 0;
650 }
651 EXPORT_SYMBOL(ath9k_hw_init);
652
653 static void ath9k_hw_init_qos(struct ath_hw *ah)
654 {
655 ENABLE_REGWRITE_BUFFER(ah);
656
657 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
658 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
659
660 REG_WRITE(ah, AR_QOS_NO_ACK,
661 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
662 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
663 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
664
665 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
666 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
667 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
668 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
669 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
670
671 REGWRITE_BUFFER_FLUSH(ah);
672 }
673
674 unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
675 {
676 REG_WRITE(ah, PLL3, (REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK)));
677 udelay(100);
678 REG_WRITE(ah, PLL3, (REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK));
679
680 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
681 udelay(100);
682
683 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
684 }
685 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
686
687 #define DPLL2_KD_VAL 0x3D
688 #define DPLL2_KI_VAL 0x06
689 #define DPLL3_PHASE_SHIFT_VAL 0x1
690
691 static void ath9k_hw_init_pll(struct ath_hw *ah,
692 struct ath9k_channel *chan)
693 {
694 u32 pll;
695
696 if (AR_SREV_9485(ah)) {
697 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
698 REG_WRITE(ah, AR_CH0_DDR_DPLL2, 0x19e82f01);
699
700 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
701 AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
702
703 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
704 udelay(1000);
705
706 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
707
708 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
709 AR_CH0_DPLL2_KD, DPLL2_KD_VAL);
710 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
711 AR_CH0_DPLL2_KI, DPLL2_KI_VAL);
712
713 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
714 AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
715 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x142c);
716 udelay(1000);
717 }
718
719 pll = ath9k_hw_compute_pll_control(ah, chan);
720
721 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
722
723 /* Switch the core clock for ar9271 to 117Mhz */
724 if (AR_SREV_9271(ah)) {
725 udelay(500);
726 REG_WRITE(ah, 0x50040, 0x304);
727 }
728
729 udelay(RTC_PLL_SETTLE_DELAY);
730
731 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
732 }
733
734 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
735 enum nl80211_iftype opmode)
736 {
737 u32 imr_reg = AR_IMR_TXERR |
738 AR_IMR_TXURN |
739 AR_IMR_RXERR |
740 AR_IMR_RXORN |
741 AR_IMR_BCNMISC;
742
743 if (AR_SREV_9300_20_OR_LATER(ah)) {
744 imr_reg |= AR_IMR_RXOK_HP;
745 if (ah->config.rx_intr_mitigation)
746 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
747 else
748 imr_reg |= AR_IMR_RXOK_LP;
749
750 } else {
751 if (ah->config.rx_intr_mitigation)
752 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
753 else
754 imr_reg |= AR_IMR_RXOK;
755 }
756
757 if (ah->config.tx_intr_mitigation)
758 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
759 else
760 imr_reg |= AR_IMR_TXOK;
761
762 if (opmode == NL80211_IFTYPE_AP)
763 imr_reg |= AR_IMR_MIB;
764
765 ENABLE_REGWRITE_BUFFER(ah);
766
767 REG_WRITE(ah, AR_IMR, imr_reg);
768 ah->imrs2_reg |= AR_IMR_S2_GTT;
769 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
770
771 if (!AR_SREV_9100(ah)) {
772 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
773 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
774 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
775 }
776
777 REGWRITE_BUFFER_FLUSH(ah);
778
779 if (AR_SREV_9300_20_OR_LATER(ah)) {
780 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
781 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
782 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
783 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
784 }
785 }
786
787 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
788 {
789 u32 val = ath9k_hw_mac_to_clks(ah, us);
790 val = min(val, (u32) 0xFFFF);
791 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
792 }
793
794 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
795 {
796 u32 val = ath9k_hw_mac_to_clks(ah, us);
797 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
798 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
799 }
800
801 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
802 {
803 u32 val = ath9k_hw_mac_to_clks(ah, us);
804 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
805 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
806 }
807
808 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
809 {
810 if (tu > 0xFFFF) {
811 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
812 "bad global tx timeout %u\n", tu);
813 ah->globaltxtimeout = (u32) -1;
814 return false;
815 } else {
816 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
817 ah->globaltxtimeout = tu;
818 return true;
819 }
820 }
821
822 void ath9k_hw_init_global_settings(struct ath_hw *ah)
823 {
824 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
825 int acktimeout;
826 int slottime;
827 int sifstime;
828
829 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
830 ah->misc_mode);
831
832 if (ah->misc_mode != 0)
833 REG_WRITE(ah, AR_PCU_MISC,
834 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
835
836 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
837 sifstime = 16;
838 else
839 sifstime = 10;
840
841 /* As defined by IEEE 802.11-2007 17.3.8.6 */
842 slottime = ah->slottime + 3 * ah->coverage_class;
843 acktimeout = slottime + sifstime;
844
845 /*
846 * Workaround for early ACK timeouts, add an offset to match the
847 * initval's 64us ack timeout value.
848 * This was initially only meant to work around an issue with delayed
849 * BA frames in some implementations, but it has been found to fix ACK
850 * timeout issues in other cases as well.
851 */
852 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
853 acktimeout += 64 - sifstime - ah->slottime;
854
855 ath9k_hw_setslottime(ah, ah->slottime);
856 ath9k_hw_set_ack_timeout(ah, acktimeout);
857 ath9k_hw_set_cts_timeout(ah, acktimeout);
858 if (ah->globaltxtimeout != (u32) -1)
859 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
860 }
861 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
862
863 void ath9k_hw_deinit(struct ath_hw *ah)
864 {
865 struct ath_common *common = ath9k_hw_common(ah);
866
867 if (common->state < ATH_HW_INITIALIZED)
868 goto free_hw;
869
870 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
871
872 free_hw:
873 ath9k_hw_rf_free_ext_banks(ah);
874 }
875 EXPORT_SYMBOL(ath9k_hw_deinit);
876
877 /*******/
878 /* INI */
879 /*******/
880
881 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
882 {
883 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
884
885 if (IS_CHAN_B(chan))
886 ctl |= CTL_11B;
887 else if (IS_CHAN_G(chan))
888 ctl |= CTL_11G;
889 else
890 ctl |= CTL_11A;
891
892 return ctl;
893 }
894
895 /****************************************/
896 /* Reset and Channel Switching Routines */
897 /****************************************/
898
899 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
900 {
901 struct ath_common *common = ath9k_hw_common(ah);
902 u32 regval;
903
904 ENABLE_REGWRITE_BUFFER(ah);
905
906 /*
907 * set AHB_MODE not to do cacheline prefetches
908 */
909 if (!AR_SREV_9300_20_OR_LATER(ah)) {
910 regval = REG_READ(ah, AR_AHB_MODE);
911 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
912 }
913
914 /*
915 * let mac dma reads be in 128 byte chunks
916 */
917 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
918 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
919
920 REGWRITE_BUFFER_FLUSH(ah);
921
922 /*
923 * Restore TX Trigger Level to its pre-reset value.
924 * The initial value depends on whether aggregation is enabled, and is
925 * adjusted whenever underruns are detected.
926 */
927 if (!AR_SREV_9300_20_OR_LATER(ah))
928 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
929
930 ENABLE_REGWRITE_BUFFER(ah);
931
932 /*
933 * let mac dma writes be in 128 byte chunks
934 */
935 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
936 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
937
938 /*
939 * Setup receive FIFO threshold to hold off TX activities
940 */
941 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
942
943 if (AR_SREV_9300_20_OR_LATER(ah)) {
944 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
945 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
946
947 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
948 ah->caps.rx_status_len);
949 }
950
951 /*
952 * reduce the number of usable entries in PCU TXBUF to avoid
953 * wrap around issues.
954 */
955 if (AR_SREV_9285(ah)) {
956 /* For AR9285 the number of Fifos are reduced to half.
957 * So set the usable tx buf size also to half to
958 * avoid data/delimiter underruns
959 */
960 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
961 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
962 } else if (!AR_SREV_9271(ah)) {
963 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
964 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
965 }
966
967 REGWRITE_BUFFER_FLUSH(ah);
968
969 if (AR_SREV_9300_20_OR_LATER(ah))
970 ath9k_hw_reset_txstatus_ring(ah);
971 }
972
973 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
974 {
975 u32 val;
976
977 val = REG_READ(ah, AR_STA_ID1);
978 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
979 switch (opmode) {
980 case NL80211_IFTYPE_AP:
981 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
982 | AR_STA_ID1_KSRCH_MODE);
983 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
984 break;
985 case NL80211_IFTYPE_ADHOC:
986 case NL80211_IFTYPE_MESH_POINT:
987 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
988 | AR_STA_ID1_KSRCH_MODE);
989 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
990 break;
991 case NL80211_IFTYPE_STATION:
992 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
993 break;
994 default:
995 if (ah->is_monitoring)
996 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
997 break;
998 }
999 }
1000
1001 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1002 u32 *coef_mantissa, u32 *coef_exponent)
1003 {
1004 u32 coef_exp, coef_man;
1005
1006 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1007 if ((coef_scaled >> coef_exp) & 0x1)
1008 break;
1009
1010 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1011
1012 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1013
1014 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1015 *coef_exponent = coef_exp - 16;
1016 }
1017
1018 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1019 {
1020 u32 rst_flags;
1021 u32 tmpReg;
1022
1023 if (AR_SREV_9100(ah)) {
1024 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1025 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1026 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1027 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1028 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1029 }
1030
1031 ENABLE_REGWRITE_BUFFER(ah);
1032
1033 if (AR_SREV_9300_20_OR_LATER(ah)) {
1034 REG_WRITE(ah, AR_WA, ah->WARegVal);
1035 udelay(10);
1036 }
1037
1038 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1039 AR_RTC_FORCE_WAKE_ON_INT);
1040
1041 if (AR_SREV_9100(ah)) {
1042 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1043 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1044 } else {
1045 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1046 if (tmpReg &
1047 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1048 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1049 u32 val;
1050 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1051
1052 val = AR_RC_HOSTIF;
1053 if (!AR_SREV_9300_20_OR_LATER(ah))
1054 val |= AR_RC_AHB;
1055 REG_WRITE(ah, AR_RC, val);
1056
1057 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1058 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1059
1060 rst_flags = AR_RTC_RC_MAC_WARM;
1061 if (type == ATH9K_RESET_COLD)
1062 rst_flags |= AR_RTC_RC_MAC_COLD;
1063 }
1064
1065 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1066
1067 REGWRITE_BUFFER_FLUSH(ah);
1068
1069 udelay(50);
1070
1071 REG_WRITE(ah, AR_RTC_RC, 0);
1072 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1073 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1074 "RTC stuck in MAC reset\n");
1075 return false;
1076 }
1077
1078 if (!AR_SREV_9100(ah))
1079 REG_WRITE(ah, AR_RC, 0);
1080
1081 if (AR_SREV_9100(ah))
1082 udelay(50);
1083
1084 return true;
1085 }
1086
1087 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1088 {
1089 ENABLE_REGWRITE_BUFFER(ah);
1090
1091 if (AR_SREV_9300_20_OR_LATER(ah)) {
1092 REG_WRITE(ah, AR_WA, ah->WARegVal);
1093 udelay(10);
1094 }
1095
1096 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1097 AR_RTC_FORCE_WAKE_ON_INT);
1098
1099 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1100 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1101
1102 REG_WRITE(ah, AR_RTC_RESET, 0);
1103
1104 REGWRITE_BUFFER_FLUSH(ah);
1105
1106 if (!AR_SREV_9300_20_OR_LATER(ah))
1107 udelay(2);
1108
1109 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1110 REG_WRITE(ah, AR_RC, 0);
1111
1112 REG_WRITE(ah, AR_RTC_RESET, 1);
1113
1114 if (!ath9k_hw_wait(ah,
1115 AR_RTC_STATUS,
1116 AR_RTC_STATUS_M,
1117 AR_RTC_STATUS_ON,
1118 AH_WAIT_TIMEOUT)) {
1119 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1120 "RTC not waking up\n");
1121 return false;
1122 }
1123
1124 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1125 }
1126
1127 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1128 {
1129 if (AR_SREV_9300_20_OR_LATER(ah)) {
1130 REG_WRITE(ah, AR_WA, ah->WARegVal);
1131 udelay(10);
1132 }
1133
1134 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1135 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1136
1137 switch (type) {
1138 case ATH9K_RESET_POWER_ON:
1139 return ath9k_hw_set_reset_power_on(ah);
1140 case ATH9K_RESET_WARM:
1141 case ATH9K_RESET_COLD:
1142 return ath9k_hw_set_reset(ah, type);
1143 default:
1144 return false;
1145 }
1146 }
1147
1148 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1149 struct ath9k_channel *chan)
1150 {
1151 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1152 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1153 return false;
1154 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1155 return false;
1156
1157 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1158 return false;
1159
1160 ah->chip_fullsleep = false;
1161 ath9k_hw_init_pll(ah, chan);
1162 ath9k_hw_set_rfmode(ah, chan);
1163
1164 return true;
1165 }
1166
1167 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1168 struct ath9k_channel *chan)
1169 {
1170 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1171 struct ath_common *common = ath9k_hw_common(ah);
1172 struct ieee80211_channel *channel = chan->chan;
1173 u32 qnum;
1174 int r;
1175
1176 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1177 if (ath9k_hw_numtxpending(ah, qnum)) {
1178 ath_dbg(common, ATH_DBG_QUEUE,
1179 "Transmit frames pending on queue %d\n", qnum);
1180 return false;
1181 }
1182 }
1183
1184 if (!ath9k_hw_rfbus_req(ah)) {
1185 ath_err(common, "Could not kill baseband RX\n");
1186 return false;
1187 }
1188
1189 ath9k_hw_set_channel_regs(ah, chan);
1190
1191 r = ath9k_hw_rf_set_freq(ah, chan);
1192 if (r) {
1193 ath_err(common, "Failed to set channel\n");
1194 return false;
1195 }
1196 ath9k_hw_set_clockrate(ah);
1197
1198 ah->eep_ops->set_txpower(ah, chan,
1199 ath9k_regd_get_ctl(regulatory, chan),
1200 channel->max_antenna_gain * 2,
1201 channel->max_power * 2,
1202 min((u32) MAX_RATE_POWER,
1203 (u32) regulatory->power_limit), false);
1204
1205 ath9k_hw_rfbus_done(ah);
1206
1207 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1208 ath9k_hw_set_delta_slope(ah, chan);
1209
1210 ath9k_hw_spur_mitigate_freq(ah, chan);
1211
1212 return true;
1213 }
1214
1215 bool ath9k_hw_check_alive(struct ath_hw *ah)
1216 {
1217 int count = 50;
1218 u32 reg;
1219
1220 if (AR_SREV_9285_12_OR_LATER(ah))
1221 return true;
1222
1223 do {
1224 reg = REG_READ(ah, AR_OBS_BUS_1);
1225
1226 if ((reg & 0x7E7FFFEF) == 0x00702400)
1227 continue;
1228
1229 switch (reg & 0x7E000B00) {
1230 case 0x1E000000:
1231 case 0x52000B00:
1232 case 0x18000B00:
1233 continue;
1234 default:
1235 return true;
1236 }
1237 } while (count-- > 0);
1238
1239 return false;
1240 }
1241 EXPORT_SYMBOL(ath9k_hw_check_alive);
1242
1243 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1244 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1245 {
1246 struct ath_common *common = ath9k_hw_common(ah);
1247 u32 saveLedState;
1248 struct ath9k_channel *curchan = ah->curchan;
1249 u32 saveDefAntenna;
1250 u32 macStaId1;
1251 u64 tsf = 0;
1252 int i, r;
1253
1254 ah->txchainmask = common->tx_chainmask;
1255 ah->rxchainmask = common->rx_chainmask;
1256
1257 if ((common->bus_ops->ath_bus_type != ATH_USB) && !ah->chip_fullsleep) {
1258 ath9k_hw_abortpcurecv(ah);
1259 if (!ath9k_hw_stopdmarecv(ah)) {
1260 ath_dbg(common, ATH_DBG_XMIT,
1261 "Failed to stop receive dma\n");
1262 bChannelChange = false;
1263 }
1264 }
1265
1266 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1267 return -EIO;
1268
1269 if (curchan && !ah->chip_fullsleep)
1270 ath9k_hw_getnf(ah, curchan);
1271
1272 ah->caldata = caldata;
1273 if (caldata &&
1274 (chan->channel != caldata->channel ||
1275 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1276 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1277 /* Operating channel changed, reset channel calibration data */
1278 memset(caldata, 0, sizeof(*caldata));
1279 ath9k_init_nfcal_hist_buffer(ah, chan);
1280 }
1281
1282 if (bChannelChange &&
1283 (ah->chip_fullsleep != true) &&
1284 (ah->curchan != NULL) &&
1285 (chan->channel != ah->curchan->channel) &&
1286 ((chan->channelFlags & CHANNEL_ALL) ==
1287 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1288 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1289
1290 if (ath9k_hw_channel_change(ah, chan)) {
1291 ath9k_hw_loadnf(ah, ah->curchan);
1292 ath9k_hw_start_nfcal(ah, true);
1293 if (AR_SREV_9271(ah))
1294 ar9002_hw_load_ani_reg(ah, chan);
1295 return 0;
1296 }
1297 }
1298
1299 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1300 if (saveDefAntenna == 0)
1301 saveDefAntenna = 1;
1302
1303 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1304
1305 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1306 if (AR_SREV_9100(ah) ||
1307 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1308 tsf = ath9k_hw_gettsf64(ah);
1309
1310 saveLedState = REG_READ(ah, AR_CFG_LED) &
1311 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1312 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1313
1314 ath9k_hw_mark_phy_inactive(ah);
1315
1316 ah->paprd_table_write_done = false;
1317
1318 /* Only required on the first reset */
1319 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1320 REG_WRITE(ah,
1321 AR9271_RESET_POWER_DOWN_CONTROL,
1322 AR9271_RADIO_RF_RST);
1323 udelay(50);
1324 }
1325
1326 if (!ath9k_hw_chip_reset(ah, chan)) {
1327 ath_err(common, "Chip reset failed\n");
1328 return -EINVAL;
1329 }
1330
1331 /* Only required on the first reset */
1332 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1333 ah->htc_reset_init = false;
1334 REG_WRITE(ah,
1335 AR9271_RESET_POWER_DOWN_CONTROL,
1336 AR9271_GATE_MAC_CTL);
1337 udelay(50);
1338 }
1339
1340 /* Restore TSF */
1341 if (tsf)
1342 ath9k_hw_settsf64(ah, tsf);
1343
1344 if (AR_SREV_9280_20_OR_LATER(ah))
1345 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1346
1347 if (!AR_SREV_9300_20_OR_LATER(ah))
1348 ar9002_hw_enable_async_fifo(ah);
1349
1350 r = ath9k_hw_process_ini(ah, chan);
1351 if (r)
1352 return r;
1353
1354 /*
1355 * Some AR91xx SoC devices frequently fail to accept TSF writes
1356 * right after the chip reset. When that happens, write a new
1357 * value after the initvals have been applied, with an offset
1358 * based on measured time difference
1359 */
1360 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1361 tsf += 1500;
1362 ath9k_hw_settsf64(ah, tsf);
1363 }
1364
1365 /* Setup MFP options for CCMP */
1366 if (AR_SREV_9280_20_OR_LATER(ah)) {
1367 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1368 * frames when constructing CCMP AAD. */
1369 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1370 0xc7ff);
1371 ah->sw_mgmt_crypto = false;
1372 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1373 /* Disable hardware crypto for management frames */
1374 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1375 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1376 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1377 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1378 ah->sw_mgmt_crypto = true;
1379 } else
1380 ah->sw_mgmt_crypto = true;
1381
1382 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1383 ath9k_hw_set_delta_slope(ah, chan);
1384
1385 ath9k_hw_spur_mitigate_freq(ah, chan);
1386 ah->eep_ops->set_board_values(ah, chan);
1387
1388 ENABLE_REGWRITE_BUFFER(ah);
1389
1390 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1391 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1392 | macStaId1
1393 | AR_STA_ID1_RTS_USE_DEF
1394 | (ah->config.
1395 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1396 | ah->sta_id1_defaults);
1397 ath_hw_setbssidmask(common);
1398 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1399 ath9k_hw_write_associd(ah);
1400 REG_WRITE(ah, AR_ISR, ~0);
1401 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1402
1403 REGWRITE_BUFFER_FLUSH(ah);
1404
1405 ath9k_hw_set_operating_mode(ah, ah->opmode);
1406
1407 r = ath9k_hw_rf_set_freq(ah, chan);
1408 if (r)
1409 return r;
1410
1411 ath9k_hw_set_clockrate(ah);
1412
1413 ENABLE_REGWRITE_BUFFER(ah);
1414
1415 for (i = 0; i < AR_NUM_DCU; i++)
1416 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1417
1418 REGWRITE_BUFFER_FLUSH(ah);
1419
1420 ah->intr_txqs = 0;
1421 for (i = 0; i < ah->caps.total_queues; i++)
1422 ath9k_hw_resettxqueue(ah, i);
1423
1424 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1425 ath9k_hw_ani_cache_ini_regs(ah);
1426 ath9k_hw_init_qos(ah);
1427
1428 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1429 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1430
1431 ath9k_hw_init_global_settings(ah);
1432
1433 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1434 ar9002_hw_update_async_fifo(ah);
1435 ar9002_hw_enable_wep_aggregation(ah);
1436 }
1437
1438 REG_WRITE(ah, AR_STA_ID1,
1439 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1440
1441 ath9k_hw_set_dma(ah);
1442
1443 REG_WRITE(ah, AR_OBS, 8);
1444
1445 if (ah->config.rx_intr_mitigation) {
1446 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1447 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1448 }
1449
1450 if (ah->config.tx_intr_mitigation) {
1451 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1452 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1453 }
1454
1455 ath9k_hw_init_bb(ah, chan);
1456
1457 if (!ath9k_hw_init_cal(ah, chan))
1458 return -EIO;
1459
1460 ENABLE_REGWRITE_BUFFER(ah);
1461
1462 ath9k_hw_restore_chainmask(ah);
1463 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1464
1465 REGWRITE_BUFFER_FLUSH(ah);
1466
1467 /*
1468 * For big endian systems turn on swapping for descriptors
1469 */
1470 if (AR_SREV_9100(ah)) {
1471 u32 mask;
1472 mask = REG_READ(ah, AR_CFG);
1473 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1474 ath_dbg(common, ATH_DBG_RESET,
1475 "CFG Byte Swap Set 0x%x\n", mask);
1476 } else {
1477 mask =
1478 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1479 REG_WRITE(ah, AR_CFG, mask);
1480 ath_dbg(common, ATH_DBG_RESET,
1481 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1482 }
1483 } else {
1484 if (common->bus_ops->ath_bus_type == ATH_USB) {
1485 /* Configure AR9271 target WLAN */
1486 if (AR_SREV_9271(ah))
1487 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1488 else
1489 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1490 }
1491 #ifdef __BIG_ENDIAN
1492 else
1493 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1494 #endif
1495 }
1496
1497 if (ah->btcoex_hw.enabled)
1498 ath9k_hw_btcoex_enable(ah);
1499
1500 if (AR_SREV_9300_20_OR_LATER(ah))
1501 ar9003_hw_bb_watchdog_config(ah);
1502
1503 return 0;
1504 }
1505 EXPORT_SYMBOL(ath9k_hw_reset);
1506
1507 /******************************/
1508 /* Power Management (Chipset) */
1509 /******************************/
1510
1511 /*
1512 * Notify Power Mgt is disabled in self-generated frames.
1513 * If requested, force chip to sleep.
1514 */
1515 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1516 {
1517 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1518 if (setChip) {
1519 /*
1520 * Clear the RTC force wake bit to allow the
1521 * mac to go to sleep.
1522 */
1523 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1524 AR_RTC_FORCE_WAKE_EN);
1525 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1526 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1527
1528 /* Shutdown chip. Active low */
1529 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1530 REG_CLR_BIT(ah, (AR_RTC_RESET),
1531 AR_RTC_RESET_EN);
1532 }
1533
1534 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1535 if (AR_SREV_9300_20_OR_LATER(ah))
1536 REG_WRITE(ah, AR_WA,
1537 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1538 }
1539
1540 /*
1541 * Notify Power Management is enabled in self-generating
1542 * frames. If request, set power mode of chip to
1543 * auto/normal. Duration in units of 128us (1/8 TU).
1544 */
1545 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1546 {
1547 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1548 if (setChip) {
1549 struct ath9k_hw_capabilities *pCap = &ah->caps;
1550
1551 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1552 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1553 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1554 AR_RTC_FORCE_WAKE_ON_INT);
1555 } else {
1556 /*
1557 * Clear the RTC force wake bit to allow the
1558 * mac to go to sleep.
1559 */
1560 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1561 AR_RTC_FORCE_WAKE_EN);
1562 }
1563 }
1564
1565 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1566 if (AR_SREV_9300_20_OR_LATER(ah))
1567 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1568 }
1569
1570 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1571 {
1572 u32 val;
1573 int i;
1574
1575 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1576 if (AR_SREV_9300_20_OR_LATER(ah)) {
1577 REG_WRITE(ah, AR_WA, ah->WARegVal);
1578 udelay(10);
1579 }
1580
1581 if (setChip) {
1582 if ((REG_READ(ah, AR_RTC_STATUS) &
1583 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1584 if (ath9k_hw_set_reset_reg(ah,
1585 ATH9K_RESET_POWER_ON) != true) {
1586 return false;
1587 }
1588 if (!AR_SREV_9300_20_OR_LATER(ah))
1589 ath9k_hw_init_pll(ah, NULL);
1590 }
1591 if (AR_SREV_9100(ah))
1592 REG_SET_BIT(ah, AR_RTC_RESET,
1593 AR_RTC_RESET_EN);
1594
1595 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1596 AR_RTC_FORCE_WAKE_EN);
1597 udelay(50);
1598
1599 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1600 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1601 if (val == AR_RTC_STATUS_ON)
1602 break;
1603 udelay(50);
1604 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1605 AR_RTC_FORCE_WAKE_EN);
1606 }
1607 if (i == 0) {
1608 ath_err(ath9k_hw_common(ah),
1609 "Failed to wakeup in %uus\n",
1610 POWER_UP_TIME / 20);
1611 return false;
1612 }
1613 }
1614
1615 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1616
1617 return true;
1618 }
1619
1620 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1621 {
1622 struct ath_common *common = ath9k_hw_common(ah);
1623 int status = true, setChip = true;
1624 static const char *modes[] = {
1625 "AWAKE",
1626 "FULL-SLEEP",
1627 "NETWORK SLEEP",
1628 "UNDEFINED"
1629 };
1630
1631 if (ah->power_mode == mode)
1632 return status;
1633
1634 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1635 modes[ah->power_mode], modes[mode]);
1636
1637 switch (mode) {
1638 case ATH9K_PM_AWAKE:
1639 status = ath9k_hw_set_power_awake(ah, setChip);
1640 break;
1641 case ATH9K_PM_FULL_SLEEP:
1642 ath9k_set_power_sleep(ah, setChip);
1643 ah->chip_fullsleep = true;
1644 break;
1645 case ATH9K_PM_NETWORK_SLEEP:
1646 ath9k_set_power_network_sleep(ah, setChip);
1647 break;
1648 default:
1649 ath_err(common, "Unknown power mode %u\n", mode);
1650 return false;
1651 }
1652 ah->power_mode = mode;
1653
1654 /*
1655 * XXX: If this warning never comes up after a while then
1656 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1657 * ath9k_hw_setpower() return type void.
1658 */
1659
1660 if (!(ah->ah_flags & AH_UNPLUGGED))
1661 ATH_DBG_WARN_ON_ONCE(!status);
1662
1663 return status;
1664 }
1665 EXPORT_SYMBOL(ath9k_hw_setpower);
1666
1667 /*******************/
1668 /* Beacon Handling */
1669 /*******************/
1670
1671 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1672 {
1673 int flags = 0;
1674
1675 ENABLE_REGWRITE_BUFFER(ah);
1676
1677 switch (ah->opmode) {
1678 case NL80211_IFTYPE_ADHOC:
1679 case NL80211_IFTYPE_MESH_POINT:
1680 REG_SET_BIT(ah, AR_TXCFG,
1681 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1682 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1683 TU_TO_USEC(next_beacon +
1684 (ah->atim_window ? ah->
1685 atim_window : 1)));
1686 flags |= AR_NDP_TIMER_EN;
1687 case NL80211_IFTYPE_AP:
1688 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1689 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1690 TU_TO_USEC(next_beacon -
1691 ah->config.
1692 dma_beacon_response_time));
1693 REG_WRITE(ah, AR_NEXT_SWBA,
1694 TU_TO_USEC(next_beacon -
1695 ah->config.
1696 sw_beacon_response_time));
1697 flags |=
1698 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1699 break;
1700 default:
1701 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1702 "%s: unsupported opmode: %d\n",
1703 __func__, ah->opmode);
1704 return;
1705 break;
1706 }
1707
1708 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1709 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1710 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1711 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1712
1713 REGWRITE_BUFFER_FLUSH(ah);
1714
1715 beacon_period &= ~ATH9K_BEACON_ENA;
1716 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1717 ath9k_hw_reset_tsf(ah);
1718 }
1719
1720 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1721 }
1722 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1723
1724 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1725 const struct ath9k_beacon_state *bs)
1726 {
1727 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1728 struct ath9k_hw_capabilities *pCap = &ah->caps;
1729 struct ath_common *common = ath9k_hw_common(ah);
1730
1731 ENABLE_REGWRITE_BUFFER(ah);
1732
1733 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1734
1735 REG_WRITE(ah, AR_BEACON_PERIOD,
1736 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1737 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1738 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1739
1740 REGWRITE_BUFFER_FLUSH(ah);
1741
1742 REG_RMW_FIELD(ah, AR_RSSI_THR,
1743 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1744
1745 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1746
1747 if (bs->bs_sleepduration > beaconintval)
1748 beaconintval = bs->bs_sleepduration;
1749
1750 dtimperiod = bs->bs_dtimperiod;
1751 if (bs->bs_sleepduration > dtimperiod)
1752 dtimperiod = bs->bs_sleepduration;
1753
1754 if (beaconintval == dtimperiod)
1755 nextTbtt = bs->bs_nextdtim;
1756 else
1757 nextTbtt = bs->bs_nexttbtt;
1758
1759 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1760 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1761 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1762 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1763
1764 ENABLE_REGWRITE_BUFFER(ah);
1765
1766 REG_WRITE(ah, AR_NEXT_DTIM,
1767 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1768 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1769
1770 REG_WRITE(ah, AR_SLEEP1,
1771 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1772 | AR_SLEEP1_ASSUME_DTIM);
1773
1774 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1775 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1776 else
1777 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1778
1779 REG_WRITE(ah, AR_SLEEP2,
1780 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1781
1782 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1783 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1784
1785 REGWRITE_BUFFER_FLUSH(ah);
1786
1787 REG_SET_BIT(ah, AR_TIMER_MODE,
1788 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1789 AR_DTIM_TIMER_EN);
1790
1791 /* TSF Out of Range Threshold */
1792 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1793 }
1794 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1795
1796 /*******************/
1797 /* HW Capabilities */
1798 /*******************/
1799
1800 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1801 {
1802 struct ath9k_hw_capabilities *pCap = &ah->caps;
1803 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1804 struct ath_common *common = ath9k_hw_common(ah);
1805 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1806
1807 u16 capField = 0, eeval;
1808 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
1809
1810 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1811 regulatory->current_rd = eeval;
1812
1813 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1814 if (AR_SREV_9285_12_OR_LATER(ah))
1815 eeval |= AR9285_RDEXT_DEFAULT;
1816 regulatory->current_rd_ext = eeval;
1817
1818 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
1819
1820 if (ah->opmode != NL80211_IFTYPE_AP &&
1821 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1822 if (regulatory->current_rd == 0x64 ||
1823 regulatory->current_rd == 0x65)
1824 regulatory->current_rd += 5;
1825 else if (regulatory->current_rd == 0x41)
1826 regulatory->current_rd = 0x43;
1827 ath_dbg(common, ATH_DBG_REGULATORY,
1828 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1829 }
1830
1831 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1832 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1833 ath_err(common,
1834 "no band has been marked as supported in EEPROM\n");
1835 return -EINVAL;
1836 }
1837
1838 if (eeval & AR5416_OPFLAGS_11A)
1839 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
1840
1841 if (eeval & AR5416_OPFLAGS_11G)
1842 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
1843
1844 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1845 /*
1846 * For AR9271 we will temporarilly uses the rx chainmax as read from
1847 * the EEPROM.
1848 */
1849 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1850 !(eeval & AR5416_OPFLAGS_11A) &&
1851 !(AR_SREV_9271(ah)))
1852 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1853 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1854 else
1855 /* Use rx_chainmask from EEPROM. */
1856 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1857
1858 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1859
1860 /* enable key search for every frame in an aggregate */
1861 if (AR_SREV_9300_20_OR_LATER(ah))
1862 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
1863
1864 pCap->low_2ghz_chan = 2312;
1865 pCap->high_2ghz_chan = 2732;
1866
1867 pCap->low_5ghz_chan = 4920;
1868 pCap->high_5ghz_chan = 6100;
1869
1870 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
1871
1872 if (ah->config.ht_enable)
1873 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1874 else
1875 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1876
1877 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
1878 pCap->total_queues =
1879 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
1880 else
1881 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
1882
1883 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
1884 pCap->keycache_size =
1885 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
1886 else
1887 pCap->keycache_size = AR_KEYTABLE_SIZE;
1888
1889 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
1890 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
1891 else
1892 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
1893
1894 if (AR_SREV_9271(ah))
1895 pCap->num_gpio_pins = AR9271_NUM_GPIO;
1896 else if (AR_DEVID_7010(ah))
1897 pCap->num_gpio_pins = AR7010_NUM_GPIO;
1898 else if (AR_SREV_9285_12_OR_LATER(ah))
1899 pCap->num_gpio_pins = AR9285_NUM_GPIO;
1900 else if (AR_SREV_9280_20_OR_LATER(ah))
1901 pCap->num_gpio_pins = AR928X_NUM_GPIO;
1902 else
1903 pCap->num_gpio_pins = AR_NUM_GPIO;
1904
1905 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
1906 pCap->hw_caps |= ATH9K_HW_CAP_CST;
1907 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1908 } else {
1909 pCap->rts_aggr_limit = (8 * 1024);
1910 }
1911
1912 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
1913
1914 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1915 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
1916 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
1917 ah->rfkill_gpio =
1918 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
1919 ah->rfkill_polarity =
1920 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
1921
1922 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
1923 }
1924 #endif
1925 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
1926 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
1927 else
1928 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
1929
1930 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
1931 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
1932 else
1933 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
1934
1935 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
1936 pCap->reg_cap =
1937 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
1938 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
1939 AR_EEPROM_EEREGCAP_EN_KK_U2 |
1940 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
1941 } else {
1942 pCap->reg_cap =
1943 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
1944 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
1945 }
1946
1947 /* Advertise midband for AR5416 with FCC midband set in eeprom */
1948 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
1949 AR_SREV_5416(ah))
1950 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
1951
1952 if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) {
1953 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
1954 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
1955
1956 if (AR_SREV_9285(ah)) {
1957 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
1958 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
1959 } else {
1960 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
1961 }
1962 } else {
1963 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
1964 }
1965
1966 if (AR_SREV_9300_20_OR_LATER(ah)) {
1967 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
1968 if (!AR_SREV_9485(ah))
1969 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
1970
1971 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
1972 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
1973 pCap->rx_status_len = sizeof(struct ar9003_rxs);
1974 pCap->tx_desc_len = sizeof(struct ar9003_txc);
1975 pCap->txs_len = sizeof(struct ar9003_txs);
1976 if (!ah->config.paprd_disable &&
1977 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
1978 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
1979 } else {
1980 pCap->tx_desc_len = sizeof(struct ath_desc);
1981 if (AR_SREV_9280_20(ah) &&
1982 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
1983 AR5416_EEP_MINOR_VER_16) ||
1984 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
1985 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
1986 }
1987
1988 if (AR_SREV_9300_20_OR_LATER(ah))
1989 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
1990
1991 if (AR_SREV_9300_20_OR_LATER(ah))
1992 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
1993
1994 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
1995 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
1996
1997 if (AR_SREV_9285(ah))
1998 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
1999 ant_div_ctl1 =
2000 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2001 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2002 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2003 }
2004 if (AR_SREV_9300_20_OR_LATER(ah)) {
2005 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2006 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2007 }
2008
2009
2010
2011 if (AR_SREV_9485_10(ah)) {
2012 pCap->pcie_lcr_extsync_en = true;
2013 pCap->pcie_lcr_offset = 0x80;
2014 }
2015
2016 tx_chainmask = pCap->tx_chainmask;
2017 rx_chainmask = pCap->rx_chainmask;
2018 while (tx_chainmask || rx_chainmask) {
2019 if (tx_chainmask & BIT(0))
2020 pCap->max_txchains++;
2021 if (rx_chainmask & BIT(0))
2022 pCap->max_rxchains++;
2023
2024 tx_chainmask >>= 1;
2025 rx_chainmask >>= 1;
2026 }
2027
2028 return 0;
2029 }
2030
2031 /****************************/
2032 /* GPIO / RFKILL / Antennae */
2033 /****************************/
2034
2035 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2036 u32 gpio, u32 type)
2037 {
2038 int addr;
2039 u32 gpio_shift, tmp;
2040
2041 if (gpio > 11)
2042 addr = AR_GPIO_OUTPUT_MUX3;
2043 else if (gpio > 5)
2044 addr = AR_GPIO_OUTPUT_MUX2;
2045 else
2046 addr = AR_GPIO_OUTPUT_MUX1;
2047
2048 gpio_shift = (gpio % 6) * 5;
2049
2050 if (AR_SREV_9280_20_OR_LATER(ah)
2051 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2052 REG_RMW(ah, addr, (type << gpio_shift),
2053 (0x1f << gpio_shift));
2054 } else {
2055 tmp = REG_READ(ah, addr);
2056 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2057 tmp &= ~(0x1f << gpio_shift);
2058 tmp |= (type << gpio_shift);
2059 REG_WRITE(ah, addr, tmp);
2060 }
2061 }
2062
2063 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2064 {
2065 u32 gpio_shift;
2066
2067 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2068
2069 if (AR_DEVID_7010(ah)) {
2070 gpio_shift = gpio;
2071 REG_RMW(ah, AR7010_GPIO_OE,
2072 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2073 (AR7010_GPIO_OE_MASK << gpio_shift));
2074 return;
2075 }
2076
2077 gpio_shift = gpio << 1;
2078 REG_RMW(ah,
2079 AR_GPIO_OE_OUT,
2080 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2081 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2082 }
2083 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2084
2085 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2086 {
2087 #define MS_REG_READ(x, y) \
2088 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2089
2090 if (gpio >= ah->caps.num_gpio_pins)
2091 return 0xffffffff;
2092
2093 if (AR_DEVID_7010(ah)) {
2094 u32 val;
2095 val = REG_READ(ah, AR7010_GPIO_IN);
2096 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2097 } else if (AR_SREV_9300_20_OR_LATER(ah))
2098 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2099 AR_GPIO_BIT(gpio)) != 0;
2100 else if (AR_SREV_9271(ah))
2101 return MS_REG_READ(AR9271, gpio) != 0;
2102 else if (AR_SREV_9287_11_OR_LATER(ah))
2103 return MS_REG_READ(AR9287, gpio) != 0;
2104 else if (AR_SREV_9285_12_OR_LATER(ah))
2105 return MS_REG_READ(AR9285, gpio) != 0;
2106 else if (AR_SREV_9280_20_OR_LATER(ah))
2107 return MS_REG_READ(AR928X, gpio) != 0;
2108 else
2109 return MS_REG_READ(AR, gpio) != 0;
2110 }
2111 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2112
2113 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2114 u32 ah_signal_type)
2115 {
2116 u32 gpio_shift;
2117
2118 if (AR_DEVID_7010(ah)) {
2119 gpio_shift = gpio;
2120 REG_RMW(ah, AR7010_GPIO_OE,
2121 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2122 (AR7010_GPIO_OE_MASK << gpio_shift));
2123 return;
2124 }
2125
2126 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2127 gpio_shift = 2 * gpio;
2128 REG_RMW(ah,
2129 AR_GPIO_OE_OUT,
2130 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2131 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2132 }
2133 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2134
2135 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2136 {
2137 if (AR_DEVID_7010(ah)) {
2138 val = val ? 0 : 1;
2139 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2140 AR_GPIO_BIT(gpio));
2141 return;
2142 }
2143
2144 if (AR_SREV_9271(ah))
2145 val = ~val;
2146
2147 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2148 AR_GPIO_BIT(gpio));
2149 }
2150 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2151
2152 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2153 {
2154 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2155 }
2156 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2157
2158 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2159 {
2160 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2161 }
2162 EXPORT_SYMBOL(ath9k_hw_setantenna);
2163
2164 /*********************/
2165 /* General Operation */
2166 /*********************/
2167
2168 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2169 {
2170 u32 bits = REG_READ(ah, AR_RX_FILTER);
2171 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2172
2173 if (phybits & AR_PHY_ERR_RADAR)
2174 bits |= ATH9K_RX_FILTER_PHYRADAR;
2175 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2176 bits |= ATH9K_RX_FILTER_PHYERR;
2177
2178 return bits;
2179 }
2180 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2181
2182 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2183 {
2184 u32 phybits;
2185
2186 ENABLE_REGWRITE_BUFFER(ah);
2187
2188 REG_WRITE(ah, AR_RX_FILTER, bits);
2189
2190 phybits = 0;
2191 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2192 phybits |= AR_PHY_ERR_RADAR;
2193 if (bits & ATH9K_RX_FILTER_PHYERR)
2194 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2195 REG_WRITE(ah, AR_PHY_ERR, phybits);
2196
2197 if (phybits)
2198 REG_WRITE(ah, AR_RXCFG,
2199 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2200 else
2201 REG_WRITE(ah, AR_RXCFG,
2202 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2203
2204 REGWRITE_BUFFER_FLUSH(ah);
2205 }
2206 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2207
2208 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2209 {
2210 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2211 return false;
2212
2213 ath9k_hw_init_pll(ah, NULL);
2214 return true;
2215 }
2216 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2217
2218 bool ath9k_hw_disable(struct ath_hw *ah)
2219 {
2220 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2221 return false;
2222
2223 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2224 return false;
2225
2226 ath9k_hw_init_pll(ah, NULL);
2227 return true;
2228 }
2229 EXPORT_SYMBOL(ath9k_hw_disable);
2230
2231 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2232 {
2233 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2234 struct ath9k_channel *chan = ah->curchan;
2235 struct ieee80211_channel *channel = chan->chan;
2236
2237 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2238
2239 ah->eep_ops->set_txpower(ah, chan,
2240 ath9k_regd_get_ctl(regulatory, chan),
2241 channel->max_antenna_gain * 2,
2242 channel->max_power * 2,
2243 min((u32) MAX_RATE_POWER,
2244 (u32) regulatory->power_limit), test);
2245 }
2246 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2247
2248 void ath9k_hw_setopmode(struct ath_hw *ah)
2249 {
2250 ath9k_hw_set_operating_mode(ah, ah->opmode);
2251 }
2252 EXPORT_SYMBOL(ath9k_hw_setopmode);
2253
2254 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2255 {
2256 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2257 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2258 }
2259 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2260
2261 void ath9k_hw_write_associd(struct ath_hw *ah)
2262 {
2263 struct ath_common *common = ath9k_hw_common(ah);
2264
2265 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2266 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2267 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2268 }
2269 EXPORT_SYMBOL(ath9k_hw_write_associd);
2270
2271 #define ATH9K_MAX_TSF_READ 10
2272
2273 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2274 {
2275 u32 tsf_lower, tsf_upper1, tsf_upper2;
2276 int i;
2277
2278 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2279 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2280 tsf_lower = REG_READ(ah, AR_TSF_L32);
2281 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2282 if (tsf_upper2 == tsf_upper1)
2283 break;
2284 tsf_upper1 = tsf_upper2;
2285 }
2286
2287 WARN_ON( i == ATH9K_MAX_TSF_READ );
2288
2289 return (((u64)tsf_upper1 << 32) | tsf_lower);
2290 }
2291 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2292
2293 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2294 {
2295 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2296 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2297 }
2298 EXPORT_SYMBOL(ath9k_hw_settsf64);
2299
2300 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2301 {
2302 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2303 AH_TSF_WRITE_TIMEOUT))
2304 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2305 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2306
2307 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2308 }
2309 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2310
2311 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2312 {
2313 if (setting)
2314 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2315 else
2316 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2317 }
2318 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2319
2320 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2321 {
2322 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2323 u32 macmode;
2324
2325 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2326 macmode = AR_2040_JOINED_RX_CLEAR;
2327 else
2328 macmode = 0;
2329
2330 REG_WRITE(ah, AR_2040_MODE, macmode);
2331 }
2332
2333 /* HW Generic timers configuration */
2334
2335 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2336 {
2337 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2338 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2339 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2340 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2341 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2342 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2343 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2344 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2345 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2346 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2347 AR_NDP2_TIMER_MODE, 0x0002},
2348 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2349 AR_NDP2_TIMER_MODE, 0x0004},
2350 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2351 AR_NDP2_TIMER_MODE, 0x0008},
2352 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2353 AR_NDP2_TIMER_MODE, 0x0010},
2354 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2355 AR_NDP2_TIMER_MODE, 0x0020},
2356 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2357 AR_NDP2_TIMER_MODE, 0x0040},
2358 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2359 AR_NDP2_TIMER_MODE, 0x0080}
2360 };
2361
2362 /* HW generic timer primitives */
2363
2364 /* compute and clear index of rightmost 1 */
2365 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2366 {
2367 u32 b;
2368
2369 b = *mask;
2370 b &= (0-b);
2371 *mask &= ~b;
2372 b *= debruijn32;
2373 b >>= 27;
2374
2375 return timer_table->gen_timer_index[b];
2376 }
2377
2378 static u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2379 {
2380 return REG_READ(ah, AR_TSF_L32);
2381 }
2382
2383 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2384 void (*trigger)(void *),
2385 void (*overflow)(void *),
2386 void *arg,
2387 u8 timer_index)
2388 {
2389 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2390 struct ath_gen_timer *timer;
2391
2392 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2393
2394 if (timer == NULL) {
2395 ath_err(ath9k_hw_common(ah),
2396 "Failed to allocate memory for hw timer[%d]\n",
2397 timer_index);
2398 return NULL;
2399 }
2400
2401 /* allocate a hardware generic timer slot */
2402 timer_table->timers[timer_index] = timer;
2403 timer->index = timer_index;
2404 timer->trigger = trigger;
2405 timer->overflow = overflow;
2406 timer->arg = arg;
2407
2408 return timer;
2409 }
2410 EXPORT_SYMBOL(ath_gen_timer_alloc);
2411
2412 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2413 struct ath_gen_timer *timer,
2414 u32 timer_next,
2415 u32 timer_period)
2416 {
2417 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2418 u32 tsf;
2419
2420 BUG_ON(!timer_period);
2421
2422 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2423
2424 tsf = ath9k_hw_gettsf32(ah);
2425
2426 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2427 "current tsf %x period %x timer_next %x\n",
2428 tsf, timer_period, timer_next);
2429
2430 /*
2431 * Pull timer_next forward if the current TSF already passed it
2432 * because of software latency
2433 */
2434 if (timer_next < tsf)
2435 timer_next = tsf + timer_period;
2436
2437 /*
2438 * Program generic timer registers
2439 */
2440 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2441 timer_next);
2442 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2443 timer_period);
2444 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2445 gen_tmr_configuration[timer->index].mode_mask);
2446
2447 /* Enable both trigger and thresh interrupt masks */
2448 REG_SET_BIT(ah, AR_IMR_S5,
2449 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2450 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2451 }
2452 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2453
2454 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2455 {
2456 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2457
2458 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2459 (timer->index >= ATH_MAX_GEN_TIMER)) {
2460 return;
2461 }
2462
2463 /* Clear generic timer enable bits. */
2464 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2465 gen_tmr_configuration[timer->index].mode_mask);
2466
2467 /* Disable both trigger and thresh interrupt masks */
2468 REG_CLR_BIT(ah, AR_IMR_S5,
2469 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2470 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2471
2472 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2473 }
2474 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2475
2476 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2477 {
2478 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2479
2480 /* free the hardware generic timer slot */
2481 timer_table->timers[timer->index] = NULL;
2482 kfree(timer);
2483 }
2484 EXPORT_SYMBOL(ath_gen_timer_free);
2485
2486 /*
2487 * Generic Timer Interrupts handling
2488 */
2489 void ath_gen_timer_isr(struct ath_hw *ah)
2490 {
2491 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2492 struct ath_gen_timer *timer;
2493 struct ath_common *common = ath9k_hw_common(ah);
2494 u32 trigger_mask, thresh_mask, index;
2495
2496 /* get hardware generic timer interrupt status */
2497 trigger_mask = ah->intr_gen_timer_trigger;
2498 thresh_mask = ah->intr_gen_timer_thresh;
2499 trigger_mask &= timer_table->timer_mask.val;
2500 thresh_mask &= timer_table->timer_mask.val;
2501
2502 trigger_mask &= ~thresh_mask;
2503
2504 while (thresh_mask) {
2505 index = rightmost_index(timer_table, &thresh_mask);
2506 timer = timer_table->timers[index];
2507 BUG_ON(!timer);
2508 ath_dbg(common, ATH_DBG_HWTIMER,
2509 "TSF overflow for Gen timer %d\n", index);
2510 timer->overflow(timer->arg);
2511 }
2512
2513 while (trigger_mask) {
2514 index = rightmost_index(timer_table, &trigger_mask);
2515 timer = timer_table->timers[index];
2516 BUG_ON(!timer);
2517 ath_dbg(common, ATH_DBG_HWTIMER,
2518 "Gen timer[%d] trigger\n", index);
2519 timer->trigger(timer->arg);
2520 }
2521 }
2522 EXPORT_SYMBOL(ath_gen_timer_isr);
2523
2524 /********/
2525 /* HTC */
2526 /********/
2527
2528 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2529 {
2530 ah->htc_reset_init = true;
2531 }
2532 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2533
2534 static struct {
2535 u32 version;
2536 const char * name;
2537 } ath_mac_bb_names[] = {
2538 /* Devices with external radios */
2539 { AR_SREV_VERSION_5416_PCI, "5416" },
2540 { AR_SREV_VERSION_5416_PCIE, "5418" },
2541 { AR_SREV_VERSION_9100, "9100" },
2542 { AR_SREV_VERSION_9160, "9160" },
2543 /* Single-chip solutions */
2544 { AR_SREV_VERSION_9280, "9280" },
2545 { AR_SREV_VERSION_9285, "9285" },
2546 { AR_SREV_VERSION_9287, "9287" },
2547 { AR_SREV_VERSION_9271, "9271" },
2548 { AR_SREV_VERSION_9300, "9300" },
2549 };
2550
2551 /* For devices with external radios */
2552 static struct {
2553 u16 version;
2554 const char * name;
2555 } ath_rf_names[] = {
2556 { 0, "5133" },
2557 { AR_RAD5133_SREV_MAJOR, "5133" },
2558 { AR_RAD5122_SREV_MAJOR, "5122" },
2559 { AR_RAD2133_SREV_MAJOR, "2133" },
2560 { AR_RAD2122_SREV_MAJOR, "2122" }
2561 };
2562
2563 /*
2564 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2565 */
2566 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2567 {
2568 int i;
2569
2570 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2571 if (ath_mac_bb_names[i].version == mac_bb_version) {
2572 return ath_mac_bb_names[i].name;
2573 }
2574 }
2575
2576 return "????";
2577 }
2578
2579 /*
2580 * Return the RF name. "????" is returned if the RF is unknown.
2581 * Used for devices with external radios.
2582 */
2583 static const char *ath9k_hw_rf_name(u16 rf_version)
2584 {
2585 int i;
2586
2587 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2588 if (ath_rf_names[i].version == rf_version) {
2589 return ath_rf_names[i].name;
2590 }
2591 }
2592
2593 return "????";
2594 }
2595
2596 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2597 {
2598 int used;
2599
2600 /* chipsets >= AR9280 are single-chip */
2601 if (AR_SREV_9280_20_OR_LATER(ah)) {
2602 used = snprintf(hw_name, len,
2603 "Atheros AR%s Rev:%x",
2604 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2605 ah->hw_version.macRev);
2606 }
2607 else {
2608 used = snprintf(hw_name, len,
2609 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2610 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2611 ah->hw_version.macRev,
2612 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2613 AR_RADIO_SREV_MAJOR)),
2614 ah->hw_version.phyRev);
2615 }
2616
2617 hw_name[used] = '\0';
2618 }
2619 EXPORT_SYMBOL(ath9k_hw_name);
CRIS linux kernel tree