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pty: Repair TIOCGPTPEER
[cris-mirror.git] / drivers / ata / ahci.c
blob5a5fd0b404eb8467b1b83bf04d9d6768cc9536c9
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/driver-api/libata.rst
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <linux/msi.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include <linux/ahci-remap.h>
50 #include <linux/io-64-nonatomic-lo-hi.h>
51 #include "ahci.h"
52
53 #define DRV_NAME "ahci"
54 #define DRV_VERSION "3.0"
55
56 enum {
57 AHCI_PCI_BAR_STA2X11 = 0,
58 AHCI_PCI_BAR_CAVIUM = 0,
59 AHCI_PCI_BAR_ENMOTUS = 2,
60 AHCI_PCI_BAR_STANDARD = 5,
61 };
62
63 enum board_ids {
64 /* board IDs by feature in alphabetical order */
65 board_ahci,
66 board_ahci_ign_iferr,
67 board_ahci_nomsi,
68 board_ahci_noncq,
69 board_ahci_nosntf,
70 board_ahci_yes_fbs,
71
72 /* board IDs for specific chipsets in alphabetical order */
73 board_ahci_avn,
74 board_ahci_mcp65,
75 board_ahci_mcp77,
76 board_ahci_mcp89,
77 board_ahci_mv,
78 board_ahci_sb600,
79 board_ahci_sb700, /* for SB700 and SB800 */
80 board_ahci_vt8251,
81
82 /* aliases */
83 board_ahci_mcp_linux = board_ahci_mcp65,
84 board_ahci_mcp67 = board_ahci_mcp65,
85 board_ahci_mcp73 = board_ahci_mcp65,
86 board_ahci_mcp79 = board_ahci_mcp77,
87 };
88
89 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
90 static void ahci_remove_one(struct pci_dev *dev);
91 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
92 unsigned long deadline);
93 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
94 unsigned long deadline);
95 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
96 static bool is_mcp89_apple(struct pci_dev *pdev);
97 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
98 unsigned long deadline);
99 #ifdef CONFIG_PM
100 static int ahci_pci_device_runtime_suspend(struct device *dev);
101 static int ahci_pci_device_runtime_resume(struct device *dev);
102 #ifdef CONFIG_PM_SLEEP
103 static int ahci_pci_device_suspend(struct device *dev);
104 static int ahci_pci_device_resume(struct device *dev);
105 #endif
106 #endif /* CONFIG_PM */
107
108 static struct scsi_host_template ahci_sht = {
109 AHCI_SHT("ahci"),
110 };
111
112 static struct ata_port_operations ahci_vt8251_ops = {
113 .inherits = &ahci_ops,
114 .hardreset = ahci_vt8251_hardreset,
115 };
116
117 static struct ata_port_operations ahci_p5wdh_ops = {
118 .inherits = &ahci_ops,
119 .hardreset = ahci_p5wdh_hardreset,
120 };
121
122 static struct ata_port_operations ahci_avn_ops = {
123 .inherits = &ahci_ops,
124 .hardreset = ahci_avn_hardreset,
125 };
126
127 static const struct ata_port_info ahci_port_info[] = {
128 /* by features */
129 [board_ahci] = {
130 .flags = AHCI_FLAG_COMMON,
131 .pio_mask = ATA_PIO4,
132 .udma_mask = ATA_UDMA6,
133 .port_ops = &ahci_ops,
134 },
135 [board_ahci_ign_iferr] = {
136 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
137 .flags = AHCI_FLAG_COMMON,
138 .pio_mask = ATA_PIO4,
139 .udma_mask = ATA_UDMA6,
140 .port_ops = &ahci_ops,
141 },
142 [board_ahci_nomsi] = {
143 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
144 .flags = AHCI_FLAG_COMMON,
145 .pio_mask = ATA_PIO4,
146 .udma_mask = ATA_UDMA6,
147 .port_ops = &ahci_ops,
148 },
149 [board_ahci_noncq] = {
150 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
151 .flags = AHCI_FLAG_COMMON,
152 .pio_mask = ATA_PIO4,
153 .udma_mask = ATA_UDMA6,
154 .port_ops = &ahci_ops,
155 },
156 [board_ahci_nosntf] = {
157 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
158 .flags = AHCI_FLAG_COMMON,
159 .pio_mask = ATA_PIO4,
160 .udma_mask = ATA_UDMA6,
161 .port_ops = &ahci_ops,
162 },
163 [board_ahci_yes_fbs] = {
164 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
165 .flags = AHCI_FLAG_COMMON,
166 .pio_mask = ATA_PIO4,
167 .udma_mask = ATA_UDMA6,
168 .port_ops = &ahci_ops,
169 },
170 /* by chipsets */
171 [board_ahci_avn] = {
172 .flags = AHCI_FLAG_COMMON,
173 .pio_mask = ATA_PIO4,
174 .udma_mask = ATA_UDMA6,
175 .port_ops = &ahci_avn_ops,
176 },
177 [board_ahci_mcp65] = {
178 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
179 AHCI_HFLAG_YES_NCQ),
180 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_ops,
184 },
185 [board_ahci_mcp77] = {
186 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_ops,
191 },
192 [board_ahci_mcp89] = {
193 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
194 .flags = AHCI_FLAG_COMMON,
195 .pio_mask = ATA_PIO4,
196 .udma_mask = ATA_UDMA6,
197 .port_ops = &ahci_ops,
198 },
199 [board_ahci_mv] = {
200 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
201 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
202 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
203 .pio_mask = ATA_PIO4,
204 .udma_mask = ATA_UDMA6,
205 .port_ops = &ahci_ops,
206 },
207 [board_ahci_sb600] = {
208 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
209 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
210 AHCI_HFLAG_32BIT_ONLY),
211 .flags = AHCI_FLAG_COMMON,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_pmp_retry_srst_ops,
215 },
216 [board_ahci_sb700] = { /* for SB700 and SB800 */
217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
218 .flags = AHCI_FLAG_COMMON,
219 .pio_mask = ATA_PIO4,
220 .udma_mask = ATA_UDMA6,
221 .port_ops = &ahci_pmp_retry_srst_ops,
222 },
223 [board_ahci_vt8251] = {
224 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
225 .flags = AHCI_FLAG_COMMON,
226 .pio_mask = ATA_PIO4,
227 .udma_mask = ATA_UDMA6,
228 .port_ops = &ahci_vt8251_ops,
229 },
230 };
231
232 static const struct pci_device_id ahci_pci_tbl[] = {
233 /* Intel */
234 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
235 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
236 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
237 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
238 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
239 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
240 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
241 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
242 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
243 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
244 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
245 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
246 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
247 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
248 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
249 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
250 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
251 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
252 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
254 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
255 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
256 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
257 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
258 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
259 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
260 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
261 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
262 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
263 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
264 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
265 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
266 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
267 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
268 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
269 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
270 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
271 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
272 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
273 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
274 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
275 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
276 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
277 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
278 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
279 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
288 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
289 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
290 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
295 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
296 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
297 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
298 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
299 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
300 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
301 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
302 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
303 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
304 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
305 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
306 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
307 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
308 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
309 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
310 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
311 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
312 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
313 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
314 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
315 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
316 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
317 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
318 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
319 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
320 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
321 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
322 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
323 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
324 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
325 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
326 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
327 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
328 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
329 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
330 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
331 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
332 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
333 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
334 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
335 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
336 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
337 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
338 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
339 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
340 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
341 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
342 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
343 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
344 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
345 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
346 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
347 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
348 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
349 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
350 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
351 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
352 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
353 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
354 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
355 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
356 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
357 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
358 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
359 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
360 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
361 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
362 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
363 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
364 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
365 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
366 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
367 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
368 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
369 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
370 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
371 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
372 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
373 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
374 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
375 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
376 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
377 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
378 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
379 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
380 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
381 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
382 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
383 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
384 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
385 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
386 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
387 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
388
389 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
390 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
391 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
392 /* JMicron 362B and 362C have an AHCI function with IDE class code */
393 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
394 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
395 /* May need to update quirk_jmicron_async_suspend() for additions */
396
397 /* ATI */
398 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
399 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
400 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
401 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
402 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
403 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
404 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
405
406 /* AMD */
407 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
408 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
409 /* AMD is using RAID class only for ahci controllers */
410 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
411 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
412
413 /* VIA */
414 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
415 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
416
417 /* NVIDIA */
418 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
419 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
420 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
421 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
422 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
423 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
424 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
425 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
426 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
427 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
428 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
429 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
430 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
431 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
432 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
433 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
439 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
440 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
441 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
442 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
443 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
444 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
445 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
446 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
447 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
448 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
449 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
450 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
451 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
452 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
453 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
454 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
455 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
456 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
458 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
459 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
460 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
467 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
468 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
469 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
470 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
471 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
479 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
480 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
481 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
482 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
483 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
484 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
485 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
486 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
487 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
488 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
489 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
490 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
491 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
492 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
493 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
494 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
495 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
496 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
497 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
498 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
499 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
500 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
501 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
502
503 /* SiS */
504 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
505 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
506 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
507
508 /* ST Microelectronics */
509 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
510
511 /* Marvell */
512 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
513 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
514 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
515 .class = PCI_CLASS_STORAGE_SATA_AHCI,
516 .class_mask = 0xffffff,
517 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
518 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
519 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
520 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
521 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
522 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
523 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
524 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
525 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
526 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
527 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
528 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
529 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
530 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
531 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
532 .driver_data = board_ahci_yes_fbs },
533 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
534 .driver_data = board_ahci_yes_fbs },
535 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
536 .driver_data = board_ahci_yes_fbs },
537 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
538 .driver_data = board_ahci_yes_fbs },
539 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
540 .driver_data = board_ahci_yes_fbs },
541
542 /* Promise */
543 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
544 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
545
546 /* Asmedia */
547 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
548 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
549 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
550 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
551 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
552 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
553
554 /*
555 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
556 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
557 */
558 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
559 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
560
561 /* Enmotus */
562 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
563
564 /* Generic, PCI class code for AHCI */
565 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
566 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
567
568 { } /* terminate list */
569 };
570
571 static const struct dev_pm_ops ahci_pci_pm_ops = {
572 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
573 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
574 ahci_pci_device_runtime_resume, NULL)
575 };
576
577 static struct pci_driver ahci_pci_driver = {
578 .name = DRV_NAME,
579 .id_table = ahci_pci_tbl,
580 .probe = ahci_init_one,
581 .remove = ahci_remove_one,
582 .driver = {
583 .pm = &ahci_pci_pm_ops,
584 },
585 };
586
587 #if IS_ENABLED(CONFIG_PATA_MARVELL)
588 static int marvell_enable;
589 #else
590 static int marvell_enable = 1;
591 #endif
592 module_param(marvell_enable, int, 0644);
593 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
594
595
596 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
597 struct ahci_host_priv *hpriv)
598 {
599 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
600 dev_info(&pdev->dev, "JMB361 has only one port\n");
601 hpriv->force_port_map = 1;
602 }
603
604 /*
605 * Temporary Marvell 6145 hack: PATA port presence
606 * is asserted through the standard AHCI port
607 * presence register, as bit 4 (counting from 0)
608 */
609 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
610 if (pdev->device == 0x6121)
611 hpriv->mask_port_map = 0x3;
612 else
613 hpriv->mask_port_map = 0xf;
614 dev_info(&pdev->dev,
615 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
616 }
617
618 ahci_save_initial_config(&pdev->dev, hpriv);
619 }
620
621 static int ahci_pci_reset_controller(struct ata_host *host)
622 {
623 struct pci_dev *pdev = to_pci_dev(host->dev);
624
625 ahci_reset_controller(host);
626
627 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
628 struct ahci_host_priv *hpriv = host->private_data;
629 u16 tmp16;
630
631 /* configure PCS */
632 pci_read_config_word(pdev, 0x92, &tmp16);
633 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
634 tmp16 |= hpriv->port_map;
635 pci_write_config_word(pdev, 0x92, tmp16);
636 }
637 }
638
639 return 0;
640 }
641
642 static void ahci_pci_init_controller(struct ata_host *host)
643 {
644 struct ahci_host_priv *hpriv = host->private_data;
645 struct pci_dev *pdev = to_pci_dev(host->dev);
646 void __iomem *port_mmio;
647 u32 tmp;
648 int mv;
649
650 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
651 if (pdev->device == 0x6121)
652 mv = 2;
653 else
654 mv = 4;
655 port_mmio = __ahci_port_base(host, mv);
656
657 writel(0, port_mmio + PORT_IRQ_MASK);
658
659 /* clear port IRQ */
660 tmp = readl(port_mmio + PORT_IRQ_STAT);
661 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
662 if (tmp)
663 writel(tmp, port_mmio + PORT_IRQ_STAT);
664 }
665
666 ahci_init_controller(host);
667 }
668
669 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
670 unsigned long deadline)
671 {
672 struct ata_port *ap = link->ap;
673 struct ahci_host_priv *hpriv = ap->host->private_data;
674 bool online;
675 int rc;
676
677 DPRINTK("ENTER\n");
678
679 ahci_stop_engine(ap);
680
681 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
682 deadline, &online, NULL);
683
684 hpriv->start_engine(ap);
685
686 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
687
688 /* vt8251 doesn't clear BSY on signature FIS reception,
689 * request follow-up softreset.
690 */
691 return online ? -EAGAIN : rc;
692 }
693
694 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
695 unsigned long deadline)
696 {
697 struct ata_port *ap = link->ap;
698 struct ahci_port_priv *pp = ap->private_data;
699 struct ahci_host_priv *hpriv = ap->host->private_data;
700 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
701 struct ata_taskfile tf;
702 bool online;
703 int rc;
704
705 ahci_stop_engine(ap);
706
707 /* clear D2H reception area to properly wait for D2H FIS */
708 ata_tf_init(link->device, &tf);
709 tf.command = ATA_BUSY;
710 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
711
712 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
713 deadline, &online, NULL);
714
715 hpriv->start_engine(ap);
716
717 /* The pseudo configuration device on SIMG4726 attached to
718 * ASUS P5W-DH Deluxe doesn't send signature FIS after
719 * hardreset if no device is attached to the first downstream
720 * port && the pseudo device locks up on SRST w/ PMP==0. To
721 * work around this, wait for !BSY only briefly. If BSY isn't
722 * cleared, perform CLO and proceed to IDENTIFY (achieved by
723 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
724 *
725 * Wait for two seconds. Devices attached to downstream port
726 * which can't process the following IDENTIFY after this will
727 * have to be reset again. For most cases, this should
728 * suffice while making probing snappish enough.
729 */
730 if (online) {
731 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
732 ahci_check_ready);
733 if (rc)
734 ahci_kick_engine(ap);
735 }
736 return rc;
737 }
738
739 /*
740 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
741 *
742 * It has been observed with some SSDs that the timing of events in the
743 * link synchronization phase can leave the port in a state that can not
744 * be recovered by a SATA-hard-reset alone. The failing signature is
745 * SStatus.DET stuck at 1 ("Device presence detected but Phy
746 * communication not established"). It was found that unloading and
747 * reloading the driver when this problem occurs allows the drive
748 * connection to be recovered (DET advanced to 0x3). The critical
749 * component of reloading the driver is that the port state machines are
750 * reset by bouncing "port enable" in the AHCI PCS configuration
751 * register. So, reproduce that effect by bouncing a port whenever we
752 * see DET==1 after a reset.
753 */
754 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
755 unsigned long deadline)
756 {
757 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
758 struct ata_port *ap = link->ap;
759 struct ahci_port_priv *pp = ap->private_data;
760 struct ahci_host_priv *hpriv = ap->host->private_data;
761 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
762 unsigned long tmo = deadline - jiffies;
763 struct ata_taskfile tf;
764 bool online;
765 int rc, i;
766
767 DPRINTK("ENTER\n");
768
769 ahci_stop_engine(ap);
770
771 for (i = 0; i < 2; i++) {
772 u16 val;
773 u32 sstatus;
774 int port = ap->port_no;
775 struct ata_host *host = ap->host;
776 struct pci_dev *pdev = to_pci_dev(host->dev);
777
778 /* clear D2H reception area to properly wait for D2H FIS */
779 ata_tf_init(link->device, &tf);
780 tf.command = ATA_BUSY;
781 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
782
783 rc = sata_link_hardreset(link, timing, deadline, &online,
784 ahci_check_ready);
785
786 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
787 (sstatus & 0xf) != 1)
788 break;
789
790 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
791 port);
792
793 pci_read_config_word(pdev, 0x92, &val);
794 val &= ~(1 << port);
795 pci_write_config_word(pdev, 0x92, val);
796 ata_msleep(ap, 1000);
797 val |= 1 << port;
798 pci_write_config_word(pdev, 0x92, val);
799 deadline += tmo;
800 }
801
802 hpriv->start_engine(ap);
803
804 if (online)
805 *class = ahci_dev_classify(ap);
806
807 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
808 return rc;
809 }
810
811
812 #ifdef CONFIG_PM
813 static void ahci_pci_disable_interrupts(struct ata_host *host)
814 {
815 struct ahci_host_priv *hpriv = host->private_data;
816 void __iomem *mmio = hpriv->mmio;
817 u32 ctl;
818
819 /* AHCI spec rev1.1 section 8.3.3:
820 * Software must disable interrupts prior to requesting a
821 * transition of the HBA to D3 state.
822 */
823 ctl = readl(mmio + HOST_CTL);
824 ctl &= ~HOST_IRQ_EN;
825 writel(ctl, mmio + HOST_CTL);
826 readl(mmio + HOST_CTL); /* flush */
827 }
828
829 static int ahci_pci_device_runtime_suspend(struct device *dev)
830 {
831 struct pci_dev *pdev = to_pci_dev(dev);
832 struct ata_host *host = pci_get_drvdata(pdev);
833
834 ahci_pci_disable_interrupts(host);
835 return 0;
836 }
837
838 static int ahci_pci_device_runtime_resume(struct device *dev)
839 {
840 struct pci_dev *pdev = to_pci_dev(dev);
841 struct ata_host *host = pci_get_drvdata(pdev);
842 int rc;
843
844 rc = ahci_pci_reset_controller(host);
845 if (rc)
846 return rc;
847 ahci_pci_init_controller(host);
848 return 0;
849 }
850
851 #ifdef CONFIG_PM_SLEEP
852 static int ahci_pci_device_suspend(struct device *dev)
853 {
854 struct pci_dev *pdev = to_pci_dev(dev);
855 struct ata_host *host = pci_get_drvdata(pdev);
856 struct ahci_host_priv *hpriv = host->private_data;
857
858 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
859 dev_err(&pdev->dev,
860 "BIOS update required for suspend/resume\n");
861 return -EIO;
862 }
863
864 ahci_pci_disable_interrupts(host);
865 return ata_host_suspend(host, PMSG_SUSPEND);
866 }
867
868 static int ahci_pci_device_resume(struct device *dev)
869 {
870 struct pci_dev *pdev = to_pci_dev(dev);
871 struct ata_host *host = pci_get_drvdata(pdev);
872 int rc;
873
874 /* Apple BIOS helpfully mangles the registers on resume */
875 if (is_mcp89_apple(pdev))
876 ahci_mcp89_apple_enable(pdev);
877
878 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
879 rc = ahci_pci_reset_controller(host);
880 if (rc)
881 return rc;
882
883 ahci_pci_init_controller(host);
884 }
885
886 ata_host_resume(host);
887
888 return 0;
889 }
890 #endif
891
892 #endif /* CONFIG_PM */
893
894 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
895 {
896 int rc;
897
898 /*
899 * If the device fixup already set the dma_mask to some non-standard
900 * value, don't extend it here. This happens on STA2X11, for example.
901 */
902 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
903 return 0;
904
905 if (using_dac &&
906 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
907 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
908 if (rc) {
909 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
910 if (rc) {
911 dev_err(&pdev->dev,
912 "64-bit DMA enable failed\n");
913 return rc;
914 }
915 }
916 } else {
917 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
918 if (rc) {
919 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
920 return rc;
921 }
922 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
923 if (rc) {
924 dev_err(&pdev->dev,
925 "32-bit consistent DMA enable failed\n");
926 return rc;
927 }
928 }
929 return 0;
930 }
931
932 static void ahci_pci_print_info(struct ata_host *host)
933 {
934 struct pci_dev *pdev = to_pci_dev(host->dev);
935 u16 cc;
936 const char *scc_s;
937
938 pci_read_config_word(pdev, 0x0a, &cc);
939 if (cc == PCI_CLASS_STORAGE_IDE)
940 scc_s = "IDE";
941 else if (cc == PCI_CLASS_STORAGE_SATA)
942 scc_s = "SATA";
943 else if (cc == PCI_CLASS_STORAGE_RAID)
944 scc_s = "RAID";
945 else
946 scc_s = "unknown";
947
948 ahci_print_info(host, scc_s);
949 }
950
951 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
952 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
953 * support PMP and the 4726 either directly exports the device
954 * attached to the first downstream port or acts as a hardware storage
955 * controller and emulate a single ATA device (can be RAID 0/1 or some
956 * other configuration).
957 *
958 * When there's no device attached to the first downstream port of the
959 * 4726, "Config Disk" appears, which is a pseudo ATA device to
960 * configure the 4726. However, ATA emulation of the device is very
961 * lame. It doesn't send signature D2H Reg FIS after the initial
962 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
963 *
964 * The following function works around the problem by always using
965 * hardreset on the port and not depending on receiving signature FIS
966 * afterward. If signature FIS isn't received soon, ATA class is
967 * assumed without follow-up softreset.
968 */
969 static void ahci_p5wdh_workaround(struct ata_host *host)
970 {
971 static const struct dmi_system_id sysids[] = {
972 {
973 .ident = "P5W DH Deluxe",
974 .matches = {
975 DMI_MATCH(DMI_SYS_VENDOR,
976 "ASUSTEK COMPUTER INC"),
977 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
978 },
979 },
980 { }
981 };
982 struct pci_dev *pdev = to_pci_dev(host->dev);
983
984 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
985 dmi_check_system(sysids)) {
986 struct ata_port *ap = host->ports[1];
987
988 dev_info(&pdev->dev,
989 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
990
991 ap->ops = &ahci_p5wdh_ops;
992 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
993 }
994 }
995
996 /*
997 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
998 * booting in BIOS compatibility mode. We restore the registers but not ID.
999 */
1000 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1001 {
1002 u32 val;
1003
1004 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1005
1006 pci_read_config_dword(pdev, 0xf8, &val);
1007 val |= 1 << 0x1b;
1008 /* the following changes the device ID, but appears not to affect function */
1009 /* val = (val & ~0xf0000000) | 0x80000000; */
1010 pci_write_config_dword(pdev, 0xf8, val);
1011
1012 pci_read_config_dword(pdev, 0x54c, &val);
1013 val |= 1 << 0xc;
1014 pci_write_config_dword(pdev, 0x54c, val);
1015
1016 pci_read_config_dword(pdev, 0x4a4, &val);
1017 val &= 0xff;
1018 val |= 0x01060100;
1019 pci_write_config_dword(pdev, 0x4a4, val);
1020
1021 pci_read_config_dword(pdev, 0x54c, &val);
1022 val &= ~(1 << 0xc);
1023 pci_write_config_dword(pdev, 0x54c, val);
1024
1025 pci_read_config_dword(pdev, 0xf8, &val);
1026 val &= ~(1 << 0x1b);
1027 pci_write_config_dword(pdev, 0xf8, val);
1028 }
1029
1030 static bool is_mcp89_apple(struct pci_dev *pdev)
1031 {
1032 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1033 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1034 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1035 pdev->subsystem_device == 0xcb89;
1036 }
1037
1038 /* only some SB600 ahci controllers can do 64bit DMA */
1039 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1040 {
1041 static const struct dmi_system_id sysids[] = {
1042 /*
1043 * The oldest version known to be broken is 0901 and
1044 * working is 1501 which was released on 2007-10-26.
1045 * Enable 64bit DMA on 1501 and anything newer.
1046 *
1047 * Please read bko#9412 for more info.
1048 */
1049 {
1050 .ident = "ASUS M2A-VM",
1051 .matches = {
1052 DMI_MATCH(DMI_BOARD_VENDOR,
1053 "ASUSTeK Computer INC."),
1054 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1055 },
1056 .driver_data = "20071026", /* yyyymmdd */
1057 },
1058 /*
1059 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1060 * support 64bit DMA.
1061 *
1062 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1063 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1064 * This spelling mistake was fixed in BIOS version 1.5, so
1065 * 1.5 and later have the Manufacturer as
1066 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1067 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1068 *
1069 * BIOS versions earlier than 1.9 had a Board Product Name
1070 * DMI field of "MS-7376". This was changed to be
1071 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1072 * match on DMI_BOARD_NAME of "MS-7376".
1073 */
1074 {
1075 .ident = "MSI K9A2 Platinum",
1076 .matches = {
1077 DMI_MATCH(DMI_BOARD_VENDOR,
1078 "MICRO-STAR INTER"),
1079 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1080 },
1081 },
1082 /*
1083 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1084 * 64bit DMA.
1085 *
1086 * This board also had the typo mentioned above in the
1087 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1088 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1089 */
1090 {
1091 .ident = "MSI K9AGM2",
1092 .matches = {
1093 DMI_MATCH(DMI_BOARD_VENDOR,
1094 "MICRO-STAR INTER"),
1095 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1096 },
1097 },
1098 /*
1099 * All BIOS versions for the Asus M3A support 64bit DMA.
1100 * (all release versions from 0301 to 1206 were tested)
1101 */
1102 {
1103 .ident = "ASUS M3A",
1104 .matches = {
1105 DMI_MATCH(DMI_BOARD_VENDOR,
1106 "ASUSTeK Computer INC."),
1107 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1108 },
1109 },
1110 { }
1111 };
1112 const struct dmi_system_id *match;
1113 int year, month, date;
1114 char buf[9];
1115
1116 match = dmi_first_match(sysids);
1117 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1118 !match)
1119 return false;
1120
1121 if (!match->driver_data)
1122 goto enable_64bit;
1123
1124 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1125 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1126
1127 if (strcmp(buf, match->driver_data) >= 0)
1128 goto enable_64bit;
1129 else {
1130 dev_warn(&pdev->dev,
1131 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1132 match->ident);
1133 return false;
1134 }
1135
1136 enable_64bit:
1137 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1138 return true;
1139 }
1140
1141 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1142 {
1143 static const struct dmi_system_id broken_systems[] = {
1144 {
1145 .ident = "HP Compaq nx6310",
1146 .matches = {
1147 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1148 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1149 },
1150 /* PCI slot number of the controller */
1151 .driver_data = (void *)0x1FUL,
1152 },
1153 {
1154 .ident = "HP Compaq 6720s",
1155 .matches = {
1156 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1157 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1158 },
1159 /* PCI slot number of the controller */
1160 .driver_data = (void *)0x1FUL,
1161 },
1162
1163 { } /* terminate list */
1164 };
1165 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1166
1167 if (dmi) {
1168 unsigned long slot = (unsigned long)dmi->driver_data;
1169 /* apply the quirk only to on-board controllers */
1170 return slot == PCI_SLOT(pdev->devfn);
1171 }
1172
1173 return false;
1174 }
1175
1176 static bool ahci_broken_suspend(struct pci_dev *pdev)
1177 {
1178 static const struct dmi_system_id sysids[] = {
1179 /*
1180 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1181 * to the harddisk doesn't become online after
1182 * resuming from STR. Warn and fail suspend.
1183 *
1184 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1185 *
1186 * Use dates instead of versions to match as HP is
1187 * apparently recycling both product and version
1188 * strings.
1189 *
1190 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1191 */
1192 {
1193 .ident = "dv4",
1194 .matches = {
1195 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1196 DMI_MATCH(DMI_PRODUCT_NAME,
1197 "HP Pavilion dv4 Notebook PC"),
1198 },
1199 .driver_data = "20090105", /* F.30 */
1200 },
1201 {
1202 .ident = "dv5",
1203 .matches = {
1204 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1205 DMI_MATCH(DMI_PRODUCT_NAME,
1206 "HP Pavilion dv5 Notebook PC"),
1207 },
1208 .driver_data = "20090506", /* F.16 */
1209 },
1210 {
1211 .ident = "dv6",
1212 .matches = {
1213 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1214 DMI_MATCH(DMI_PRODUCT_NAME,
1215 "HP Pavilion dv6 Notebook PC"),
1216 },
1217 .driver_data = "20090423", /* F.21 */
1218 },
1219 {
1220 .ident = "HDX18",
1221 .matches = {
1222 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1223 DMI_MATCH(DMI_PRODUCT_NAME,
1224 "HP HDX18 Notebook PC"),
1225 },
1226 .driver_data = "20090430", /* F.23 */
1227 },
1228 /*
1229 * Acer eMachines G725 has the same problem. BIOS
1230 * V1.03 is known to be broken. V3.04 is known to
1231 * work. Between, there are V1.06, V2.06 and V3.03
1232 * that we don't have much idea about. For now,
1233 * blacklist anything older than V3.04.
1234 *
1235 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1236 */
1237 {
1238 .ident = "G725",
1239 .matches = {
1240 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1241 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1242 },
1243 .driver_data = "20091216", /* V3.04 */
1244 },
1245 { } /* terminate list */
1246 };
1247 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1248 int year, month, date;
1249 char buf[9];
1250
1251 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1252 return false;
1253
1254 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1255 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1256
1257 return strcmp(buf, dmi->driver_data) < 0;
1258 }
1259
1260 static bool ahci_broken_online(struct pci_dev *pdev)
1261 {
1262 #define ENCODE_BUSDEVFN(bus, slot, func) \
1263 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1264 static const struct dmi_system_id sysids[] = {
1265 /*
1266 * There are several gigabyte boards which use
1267 * SIMG5723s configured as hardware RAID. Certain
1268 * 5723 firmware revisions shipped there keep the link
1269 * online but fail to answer properly to SRST or
1270 * IDENTIFY when no device is attached downstream
1271 * causing libata to retry quite a few times leading
1272 * to excessive detection delay.
1273 *
1274 * As these firmwares respond to the second reset try
1275 * with invalid device signature, considering unknown
1276 * sig as offline works around the problem acceptably.
1277 */
1278 {
1279 .ident = "EP45-DQ6",
1280 .matches = {
1281 DMI_MATCH(DMI_BOARD_VENDOR,
1282 "Gigabyte Technology Co., Ltd."),
1283 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1284 },
1285 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1286 },
1287 {
1288 .ident = "EP45-DS5",
1289 .matches = {
1290 DMI_MATCH(DMI_BOARD_VENDOR,
1291 "Gigabyte Technology Co., Ltd."),
1292 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1293 },
1294 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1295 },
1296 { } /* terminate list */
1297 };
1298 #undef ENCODE_BUSDEVFN
1299 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1300 unsigned int val;
1301
1302 if (!dmi)
1303 return false;
1304
1305 val = (unsigned long)dmi->driver_data;
1306
1307 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1308 }
1309
1310 static bool ahci_broken_devslp(struct pci_dev *pdev)
1311 {
1312 /* device with broken DEVSLP but still showing SDS capability */
1313 static const struct pci_device_id ids[] = {
1314 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1315 {}
1316 };
1317
1318 return pci_match_id(ids, pdev);
1319 }
1320
1321 #ifdef CONFIG_ATA_ACPI
1322 static void ahci_gtf_filter_workaround(struct ata_host *host)
1323 {
1324 static const struct dmi_system_id sysids[] = {
1325 /*
1326 * Aspire 3810T issues a bunch of SATA enable commands
1327 * via _GTF including an invalid one and one which is
1328 * rejected by the device. Among the successful ones
1329 * is FPDMA non-zero offset enable which when enabled
1330 * only on the drive side leads to NCQ command
1331 * failures. Filter it out.
1332 */
1333 {
1334 .ident = "Aspire 3810T",
1335 .matches = {
1336 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1337 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1338 },
1339 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1340 },
1341 { }
1342 };
1343 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1344 unsigned int filter;
1345 int i;
1346
1347 if (!dmi)
1348 return;
1349
1350 filter = (unsigned long)dmi->driver_data;
1351 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1352 filter, dmi->ident);
1353
1354 for (i = 0; i < host->n_ports; i++) {
1355 struct ata_port *ap = host->ports[i];
1356 struct ata_link *link;
1357 struct ata_device *dev;
1358
1359 ata_for_each_link(link, ap, EDGE)
1360 ata_for_each_dev(dev, link, ALL)
1361 dev->gtf_filter |= filter;
1362 }
1363 }
1364 #else
1365 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1366 {}
1367 #endif
1368
1369 /*
1370 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1371 * as DUMMY, or detected but eventually get a "link down" and never get up
1372 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1373 * port_map may hold a value of 0x00.
1374 *
1375 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1376 * and can significantly reduce the occurrence of the problem.
1377 *
1378 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1379 */
1380 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1381 struct pci_dev *pdev)
1382 {
1383 static const struct dmi_system_id sysids[] = {
1384 {
1385 .ident = "Acer Switch Alpha 12",
1386 .matches = {
1387 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1388 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1389 },
1390 },
1391 { }
1392 };
1393
1394 if (dmi_check_system(sysids)) {
1395 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1396 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1397 hpriv->port_map = 0x7;
1398 hpriv->cap = 0xC734FF02;
1399 }
1400 }
1401 }
1402
1403 #ifdef CONFIG_ARM64
1404 /*
1405 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1406 * Workaround is to make sure all pending IRQs are served before leaving
1407 * handler.
1408 */
1409 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1410 {
1411 struct ata_host *host = dev_instance;
1412 struct ahci_host_priv *hpriv;
1413 unsigned int rc = 0;
1414 void __iomem *mmio;
1415 u32 irq_stat, irq_masked;
1416 unsigned int handled = 1;
1417
1418 VPRINTK("ENTER\n");
1419 hpriv = host->private_data;
1420 mmio = hpriv->mmio;
1421 irq_stat = readl(mmio + HOST_IRQ_STAT);
1422 if (!irq_stat)
1423 return IRQ_NONE;
1424
1425 do {
1426 irq_masked = irq_stat & hpriv->port_map;
1427 spin_lock(&host->lock);
1428 rc = ahci_handle_port_intr(host, irq_masked);
1429 if (!rc)
1430 handled = 0;
1431 writel(irq_stat, mmio + HOST_IRQ_STAT);
1432 irq_stat = readl(mmio + HOST_IRQ_STAT);
1433 spin_unlock(&host->lock);
1434 } while (irq_stat);
1435 VPRINTK("EXIT\n");
1436
1437 return IRQ_RETVAL(handled);
1438 }
1439 #endif
1440
1441 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1442 struct ahci_host_priv *hpriv)
1443 {
1444 int i, count = 0;
1445 u32 cap;
1446
1447 /*
1448 * Check if this device might have remapped nvme devices.
1449 */
1450 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1451 pci_resource_len(pdev, bar) < SZ_512K ||
1452 bar != AHCI_PCI_BAR_STANDARD ||
1453 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1454 return;
1455
1456 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1457 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1458 if ((cap & (1 << i)) == 0)
1459 continue;
1460 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1461 != PCI_CLASS_STORAGE_EXPRESS)
1462 continue;
1463
1464 /* We've found a remapped device */
1465 count++;
1466 }
1467
1468 if (!count)
1469 return;
1470
1471 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
1472 dev_warn(&pdev->dev, "Switch your BIOS from RAID to AHCI mode to use them.\n");
1473 }
1474
1475 static int ahci_get_irq_vector(struct ata_host *host, int port)
1476 {
1477 return pci_irq_vector(to_pci_dev(host->dev), port);
1478 }
1479
1480 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1481 struct ahci_host_priv *hpriv)
1482 {
1483 int nvec;
1484
1485 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1486 return -ENODEV;
1487
1488 /*
1489 * If number of MSIs is less than number of ports then Sharing Last
1490 * Message mode could be enforced. In this case assume that advantage
1491 * of multipe MSIs is negated and use single MSI mode instead.
1492 */
1493 if (n_ports > 1) {
1494 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1495 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1496 if (nvec > 0) {
1497 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1498 hpriv->get_irq_vector = ahci_get_irq_vector;
1499 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1500 return nvec;
1501 }
1502
1503 /*
1504 * Fallback to single MSI mode if the controller
1505 * enforced MRSM mode.
1506 */
1507 printk(KERN_INFO
1508 "ahci: MRSM is on, fallback to single MSI\n");
1509 pci_free_irq_vectors(pdev);
1510 }
1511 }
1512
1513 /*
1514 * If the host is not capable of supporting per-port vectors, fall
1515 * back to single MSI before finally attempting single MSI-X.
1516 */
1517 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1518 if (nvec == 1)
1519 return nvec;
1520 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1521 }
1522
1523 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1524 {
1525 unsigned int board_id = ent->driver_data;
1526 struct ata_port_info pi = ahci_port_info[board_id];
1527 const struct ata_port_info *ppi[] = { &pi, NULL };
1528 struct device *dev = &pdev->dev;
1529 struct ahci_host_priv *hpriv;
1530 struct ata_host *host;
1531 int n_ports, i, rc;
1532 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1533
1534 VPRINTK("ENTER\n");
1535
1536 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1537
1538 ata_print_version_once(&pdev->dev, DRV_VERSION);
1539
1540 /* The AHCI driver can only drive the SATA ports, the PATA driver
1541 can drive them all so if both drivers are selected make sure
1542 AHCI stays out of the way */
1543 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1544 return -ENODEV;
1545
1546 /* Apple BIOS on MCP89 prevents us using AHCI */
1547 if (is_mcp89_apple(pdev))
1548 ahci_mcp89_apple_enable(pdev);
1549
1550 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1551 * At the moment, we can only use the AHCI mode. Let the users know
1552 * that for SAS drives they're out of luck.
1553 */
1554 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1555 dev_info(&pdev->dev,
1556 "PDC42819 can only drive SATA devices with this driver\n");
1557
1558 /* Some devices use non-standard BARs */
1559 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1560 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1561 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1562 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1563 else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1564 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1565
1566 /* acquire resources */
1567 rc = pcim_enable_device(pdev);
1568 if (rc)
1569 return rc;
1570
1571 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1572 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1573 u8 map;
1574
1575 /* ICH6s share the same PCI ID for both piix and ahci
1576 * modes. Enabling ahci mode while MAP indicates
1577 * combined mode is a bad idea. Yield to ata_piix.
1578 */
1579 pci_read_config_byte(pdev, ICH_MAP, &map);
1580 if (map & 0x3) {
1581 dev_info(&pdev->dev,
1582 "controller is in combined mode, can't enable AHCI mode\n");
1583 return -ENODEV;
1584 }
1585 }
1586
1587 /* AHCI controllers often implement SFF compatible interface.
1588 * Grab all PCI BARs just in case.
1589 */
1590 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1591 if (rc == -EBUSY)
1592 pcim_pin_device(pdev);
1593 if (rc)
1594 return rc;
1595
1596 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1597 if (!hpriv)
1598 return -ENOMEM;
1599 hpriv->flags |= (unsigned long)pi.private_data;
1600
1601 /* MCP65 revision A1 and A2 can't do MSI */
1602 if (board_id == board_ahci_mcp65 &&
1603 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1604 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1605
1606 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1607 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1608 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1609
1610 /* only some SB600s can do 64bit DMA */
1611 if (ahci_sb600_enable_64bit(pdev))
1612 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1613
1614 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1615
1616 /* detect remapped nvme devices */
1617 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1618
1619 /* must set flag prior to save config in order to take effect */
1620 if (ahci_broken_devslp(pdev))
1621 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1622
1623 #ifdef CONFIG_ARM64
1624 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1625 hpriv->irq_handler = ahci_thunderx_irq_handler;
1626 #endif
1627
1628 /* save initial config */
1629 ahci_pci_save_initial_config(pdev, hpriv);
1630
1631 /* prepare host */
1632 if (hpriv->cap & HOST_CAP_NCQ) {
1633 pi.flags |= ATA_FLAG_NCQ;
1634 /*
1635 * Auto-activate optimization is supposed to be
1636 * supported on all AHCI controllers indicating NCQ
1637 * capability, but it seems to be broken on some
1638 * chipsets including NVIDIAs.
1639 */
1640 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1641 pi.flags |= ATA_FLAG_FPDMA_AA;
1642
1643 /*
1644 * All AHCI controllers should be forward-compatible
1645 * with the new auxiliary field. This code should be
1646 * conditionalized if any buggy AHCI controllers are
1647 * encountered.
1648 */
1649 pi.flags |= ATA_FLAG_FPDMA_AUX;
1650 }
1651
1652 if (hpriv->cap & HOST_CAP_PMP)
1653 pi.flags |= ATA_FLAG_PMP;
1654
1655 ahci_set_em_messages(hpriv, &pi);
1656
1657 if (ahci_broken_system_poweroff(pdev)) {
1658 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1659 dev_info(&pdev->dev,
1660 "quirky BIOS, skipping spindown on poweroff\n");
1661 }
1662
1663 if (ahci_broken_suspend(pdev)) {
1664 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1665 dev_warn(&pdev->dev,
1666 "BIOS update required for suspend/resume\n");
1667 }
1668
1669 if (ahci_broken_online(pdev)) {
1670 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1671 dev_info(&pdev->dev,
1672 "online status unreliable, applying workaround\n");
1673 }
1674
1675
1676 /* Acer SA5-271 workaround modifies private_data */
1677 acer_sa5_271_workaround(hpriv, pdev);
1678
1679 /* CAP.NP sometimes indicate the index of the last enabled
1680 * port, at other times, that of the last possible port, so
1681 * determining the maximum port number requires looking at
1682 * both CAP.NP and port_map.
1683 */
1684 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1685
1686 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1687 if (!host)
1688 return -ENOMEM;
1689 host->private_data = hpriv;
1690
1691 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1692 /* legacy intx interrupts */
1693 pci_intx(pdev, 1);
1694 }
1695 hpriv->irq = pci_irq_vector(pdev, 0);
1696
1697 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1698 host->flags |= ATA_HOST_PARALLEL_SCAN;
1699 else
1700 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1701
1702 if (pi.flags & ATA_FLAG_EM)
1703 ahci_reset_em(host);
1704
1705 for (i = 0; i < host->n_ports; i++) {
1706 struct ata_port *ap = host->ports[i];
1707
1708 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1709 ata_port_pbar_desc(ap, ahci_pci_bar,
1710 0x100 + ap->port_no * 0x80, "port");
1711
1712 /* set enclosure management message type */
1713 if (ap->flags & ATA_FLAG_EM)
1714 ap->em_message_type = hpriv->em_msg_type;
1715
1716
1717 /* disabled/not-implemented port */
1718 if (!(hpriv->port_map & (1 << i)))
1719 ap->ops = &ata_dummy_port_ops;
1720 }
1721
1722 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1723 ahci_p5wdh_workaround(host);
1724
1725 /* apply gtf filter quirk */
1726 ahci_gtf_filter_workaround(host);
1727
1728 /* initialize adapter */
1729 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1730 if (rc)
1731 return rc;
1732
1733 rc = ahci_pci_reset_controller(host);
1734 if (rc)
1735 return rc;
1736
1737 ahci_pci_init_controller(host);
1738 ahci_pci_print_info(host);
1739
1740 pci_set_master(pdev);
1741
1742 rc = ahci_host_activate(host, &ahci_sht);
1743 if (rc)
1744 return rc;
1745
1746 pm_runtime_put_noidle(&pdev->dev);
1747 return 0;
1748 }
1749
1750 static void ahci_remove_one(struct pci_dev *pdev)
1751 {
1752 pm_runtime_get_noresume(&pdev->dev);
1753 ata_pci_remove_one(pdev);
1754 }
1755
1756 module_pci_driver(ahci_pci_driver);
1757
1758 MODULE_AUTHOR("Jeff Garzik");
1759 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1760 MODULE_LICENSE("GPL");
1761 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1762 MODULE_VERSION(DRV_VERSION);
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