?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[cris-mirror.git] / arch / mips / kernel / traps.c
blob3de85be2486a44d5fbaedb64a556b3e9bf879210
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
13 * Copyright (C) 2014, Imagination Technologies Ltd.
14 */
15 #include <linux/bitops.h>
16 #include <linux/bug.h>
17 #include <linux/compiler.h>
18 #include <linux/context_tracking.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/kexec.h>
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/mm.h>
25 #include <linux/sched.h>
26 #include <linux/smp.h>
27 #include <linux/spinlock.h>
28 #include <linux/kallsyms.h>
29 #include <linux/bootmem.h>
30 #include <linux/interrupt.h>
31 #include <linux/ptrace.h>
32 #include <linux/kgdb.h>
33 #include <linux/kdebug.h>
34 #include <linux/kprobes.h>
35 #include <linux/notifier.h>
36 #include <linux/kdb.h>
37 #include <linux/irq.h>
38 #include <linux/perf_event.h>
39
40 #include <asm/addrspace.h>
41 #include <asm/bootinfo.h>
42 #include <asm/branch.h>
43 #include <asm/break.h>
44 #include <asm/cop2.h>
45 #include <asm/cpu.h>
46 #include <asm/cpu-type.h>
47 #include <asm/dsp.h>
48 #include <asm/fpu.h>
49 #include <asm/fpu_emulator.h>
50 #include <asm/idle.h>
51 #include <asm/mips-r2-to-r6-emul.h>
52 #include <asm/mipsregs.h>
53 #include <asm/mipsmtregs.h>
54 #include <asm/module.h>
55 #include <asm/msa.h>
56 #include <asm/pgtable.h>
57 #include <asm/ptrace.h>
58 #include <asm/sections.h>
59 #include <asm/siginfo.h>
60 #include <asm/tlbdebug.h>
61 #include <asm/traps.h>
62 #include <asm/uaccess.h>
63 #include <asm/watch.h>
64 #include <asm/mmu_context.h>
65 #include <asm/types.h>
66 #include <asm/stacktrace.h>
67 #include <asm/uasm.h>
68
69 extern void check_wait(void);
70 extern asmlinkage void rollback_handle_int(void);
71 extern asmlinkage void handle_int(void);
72 extern u32 handle_tlbl[];
73 extern u32 handle_tlbs[];
74 extern u32 handle_tlbm[];
75 extern asmlinkage void handle_adel(void);
76 extern asmlinkage void handle_ades(void);
77 extern asmlinkage void handle_ibe(void);
78 extern asmlinkage void handle_dbe(void);
79 extern asmlinkage void handle_sys(void);
80 extern asmlinkage void handle_bp(void);
81 extern asmlinkage void handle_ri(void);
82 extern asmlinkage void handle_ri_rdhwr_vivt(void);
83 extern asmlinkage void handle_ri_rdhwr(void);
84 extern asmlinkage void handle_cpu(void);
85 extern asmlinkage void handle_ov(void);
86 extern asmlinkage void handle_tr(void);
87 extern asmlinkage void handle_msa_fpe(void);
88 extern asmlinkage void handle_fpe(void);
89 extern asmlinkage void handle_ftlb(void);
90 extern asmlinkage void handle_msa(void);
91 extern asmlinkage void handle_mdmx(void);
92 extern asmlinkage void handle_watch(void);
93 extern asmlinkage void handle_mt(void);
94 extern asmlinkage void handle_dsp(void);
95 extern asmlinkage void handle_mcheck(void);
96 extern asmlinkage void handle_reserved(void);
97 extern void tlb_do_page_fault_0(void);
98
99 void (*board_be_init)(void);
100 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
101 void (*board_nmi_handler_setup)(void);
102 void (*board_ejtag_handler_setup)(void);
103 void (*board_bind_eic_interrupt)(int irq, int regset);
104 void (*board_ebase_setup)(void);
105 void(*board_cache_error_setup)(void);
106
107 static void show_raw_backtrace(unsigned long reg29)
108 {
109 unsigned long *sp = (unsigned long *)(reg29 & ~3);
110 unsigned long addr;
111
112 printk("Call Trace:");
113 #ifdef CONFIG_KALLSYMS
114 printk("\n");
115 #endif
116 while (!kstack_end(sp)) {
117 unsigned long __user *p =
118 (unsigned long __user *)(unsigned long)sp++;
119 if (__get_user(addr, p)) {
120 printk(" (Bad stack address)");
121 break;
122 }
123 if (__kernel_text_address(addr))
124 print_ip_sym(addr);
125 }
126 printk("\n");
127 }
128
129 #ifdef CONFIG_KALLSYMS
130 int raw_show_trace;
131 static int __init set_raw_show_trace(char *str)
132 {
133 raw_show_trace = 1;
134 return 1;
135 }
136 __setup("raw_show_trace", set_raw_show_trace);
137 #endif
138
139 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
140 {
141 unsigned long sp = regs->regs[29];
142 unsigned long ra = regs->regs[31];
143 unsigned long pc = regs->cp0_epc;
144
145 if (!task)
146 task = current;
147
148 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) {
149 show_raw_backtrace(sp);
150 return;
151 }
152 printk("Call Trace:\n");
153 do {
154 print_ip_sym(pc);
155 pc = unwind_stack(task, &sp, pc, &ra);
156 } while (pc);
157 printk("\n");
158 }
159
160 /*
161 * This routine abuses get_user()/put_user() to reference pointers
162 * with at least a bit of error checking ...
163 */
164 static void show_stacktrace(struct task_struct *task,
165 const struct pt_regs *regs)
166 {
167 const int field = 2 * sizeof(unsigned long);
168 long stackdata;
169 int i;
170 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
171
172 printk("Stack :");
173 i = 0;
174 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
175 if (i && ((i % (64 / field)) == 0))
176 printk("\n ");
177 if (i > 39) {
178 printk(" ...");
179 break;
180 }
181
182 if (__get_user(stackdata, sp++)) {
183 printk(" (Bad stack address)");
184 break;
185 }
186
187 printk(" %0*lx", field, stackdata);
188 i++;
189 }
190 printk("\n");
191 show_backtrace(task, regs);
192 }
193
194 void show_stack(struct task_struct *task, unsigned long *sp)
195 {
196 struct pt_regs regs;
197 mm_segment_t old_fs = get_fs();
198 if (sp) {
199 regs.regs[29] = (unsigned long)sp;
200 regs.regs[31] = 0;
201 regs.cp0_epc = 0;
202 } else {
203 if (task && task != current) {
204 regs.regs[29] = task->thread.reg29;
205 regs.regs[31] = 0;
206 regs.cp0_epc = task->thread.reg31;
207 #ifdef CONFIG_KGDB_KDB
208 } else if (atomic_read(&kgdb_active) != -1 &&
209 kdb_current_regs) {
210 memcpy(&regs, kdb_current_regs, sizeof(regs));
211 #endif /* CONFIG_KGDB_KDB */
212 } else {
213 prepare_frametrace(&regs);
214 }
215 }
216 /*
217 * show_stack() deals exclusively with kernel mode, so be sure to access
218 * the stack in the kernel (not user) address space.
219 */
220 set_fs(KERNEL_DS);
221 show_stacktrace(task, &regs);
222 set_fs(old_fs);
223 }
224
225 static void show_code(unsigned int __user *pc)
226 {
227 long i;
228 unsigned short __user *pc16 = NULL;
229
230 printk("\nCode:");
231
232 if ((unsigned long)pc & 1)
233 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
234 for(i = -3 ; i < 6 ; i++) {
235 unsigned int insn;
236 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
237 printk(" (Bad address in epc)\n");
238 break;
239 }
240 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
241 }
242 }
243
244 static void __show_regs(const struct pt_regs *regs)
245 {
246 const int field = 2 * sizeof(unsigned long);
247 unsigned int cause = regs->cp0_cause;
248 unsigned int exccode;
249 int i;
250
251 show_regs_print_info(KERN_DEFAULT);
252
253 /*
254 * Saved main processor registers
255 */
256 for (i = 0; i < 32; ) {
257 if ((i % 4) == 0)
258 printk("$%2d :", i);
259 if (i == 0)
260 printk(" %0*lx", field, 0UL);
261 else if (i == 26 || i == 27)
262 printk(" %*s", field, "");
263 else
264 printk(" %0*lx", field, regs->regs[i]);
265
266 i++;
267 if ((i % 4) == 0)
268 printk("\n");
269 }
270
271 #ifdef CONFIG_CPU_HAS_SMARTMIPS
272 printk("Acx : %0*lx\n", field, regs->acx);
273 #endif
274 printk("Hi : %0*lx\n", field, regs->hi);
275 printk("Lo : %0*lx\n", field, regs->lo);
276
277 /*
278 * Saved cp0 registers
279 */
280 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
281 (void *) regs->cp0_epc);
282 printk("ra : %0*lx %pS\n", field, regs->regs[31],
283 (void *) regs->regs[31]);
284
285 printk("Status: %08x ", (uint32_t) regs->cp0_status);
286
287 if (cpu_has_3kex) {
288 if (regs->cp0_status & ST0_KUO)
289 printk("KUo ");
290 if (regs->cp0_status & ST0_IEO)
291 printk("IEo ");
292 if (regs->cp0_status & ST0_KUP)
293 printk("KUp ");
294 if (regs->cp0_status & ST0_IEP)
295 printk("IEp ");
296 if (regs->cp0_status & ST0_KUC)
297 printk("KUc ");
298 if (regs->cp0_status & ST0_IEC)
299 printk("IEc ");
300 } else if (cpu_has_4kex) {
301 if (regs->cp0_status & ST0_KX)
302 printk("KX ");
303 if (regs->cp0_status & ST0_SX)
304 printk("SX ");
305 if (regs->cp0_status & ST0_UX)
306 printk("UX ");
307 switch (regs->cp0_status & ST0_KSU) {
308 case KSU_USER:
309 printk("USER ");
310 break;
311 case KSU_SUPERVISOR:
312 printk("SUPERVISOR ");
313 break;
314 case KSU_KERNEL:
315 printk("KERNEL ");
316 break;
317 default:
318 printk("BAD_MODE ");
319 break;
320 }
321 if (regs->cp0_status & ST0_ERL)
322 printk("ERL ");
323 if (regs->cp0_status & ST0_EXL)
324 printk("EXL ");
325 if (regs->cp0_status & ST0_IE)
326 printk("IE ");
327 }
328 printk("\n");
329
330 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
331 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode);
332
333 if (1 <= exccode && exccode <= 5)
334 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
335
336 printk("PrId : %08x (%s)\n", read_c0_prid(),
337 cpu_name_string());
338 }
339
340 /*
341 * FIXME: really the generic show_regs should take a const pointer argument.
342 */
343 void show_regs(struct pt_regs *regs)
344 {
345 __show_regs((struct pt_regs *)regs);
346 }
347
348 void show_registers(struct pt_regs *regs)
349 {
350 const int field = 2 * sizeof(unsigned long);
351 mm_segment_t old_fs = get_fs();
352
353 __show_regs(regs);
354 print_modules();
355 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
356 current->comm, current->pid, current_thread_info(), current,
357 field, current_thread_info()->tp_value);
358 if (cpu_has_userlocal) {
359 unsigned long tls;
360
361 tls = read_c0_userlocal();
362 if (tls != current_thread_info()->tp_value)
363 printk("*HwTLS: %0*lx\n", field, tls);
364 }
365
366 if (!user_mode(regs))
367 /* Necessary for getting the correct stack content */
368 set_fs(KERNEL_DS);
369 show_stacktrace(current, regs);
370 show_code((unsigned int __user *) regs->cp0_epc);
371 printk("\n");
372 set_fs(old_fs);
373 }
374
375 static DEFINE_RAW_SPINLOCK(die_lock);
376
377 void __noreturn die(const char *str, struct pt_regs *regs)
378 {
379 static int die_counter;
380 int sig = SIGSEGV;
381
382 oops_enter();
383
384 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
385 SIGSEGV) == NOTIFY_STOP)
386 sig = 0;
387
388 console_verbose();
389 raw_spin_lock_irq(&die_lock);
390 bust_spinlocks(1);
391
392 printk("%s[#%d]:\n", str, ++die_counter);
393 show_registers(regs);
394 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
395 raw_spin_unlock_irq(&die_lock);
396
397 oops_exit();
398
399 if (in_interrupt())
400 panic("Fatal exception in interrupt");
401
402 if (panic_on_oops)
403 panic("Fatal exception");
404
405 if (regs && kexec_should_crash(current))
406 crash_kexec(regs);
407
408 do_exit(sig);
409 }
410
411 extern struct exception_table_entry __start___dbe_table[];
412 extern struct exception_table_entry __stop___dbe_table[];
413
414 __asm__(
415 " .section __dbe_table, \"a\"\n"
416 " .previous \n");
417
418 /* Given an address, look for it in the exception tables. */
419 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
420 {
421 const struct exception_table_entry *e;
422
423 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
424 if (!e)
425 e = search_module_dbetables(addr);
426 return e;
427 }
428
429 asmlinkage void do_be(struct pt_regs *regs)
430 {
431 const int field = 2 * sizeof(unsigned long);
432 const struct exception_table_entry *fixup = NULL;
433 int data = regs->cp0_cause & 4;
434 int action = MIPS_BE_FATAL;
435 enum ctx_state prev_state;
436
437 prev_state = exception_enter();
438 /* XXX For now. Fixme, this searches the wrong table ... */
439 if (data && !user_mode(regs))
440 fixup = search_dbe_tables(exception_epc(regs));
441
442 if (fixup)
443 action = MIPS_BE_FIXUP;
444
445 if (board_be_handler)
446 action = board_be_handler(regs, fixup != NULL);
447
448 switch (action) {
449 case MIPS_BE_DISCARD:
450 goto out;
451 case MIPS_BE_FIXUP:
452 if (fixup) {
453 regs->cp0_epc = fixup->nextinsn;
454 goto out;
455 }
456 break;
457 default:
458 break;
459 }
460
461 /*
462 * Assume it would be too dangerous to continue ...
463 */
464 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
465 data ? "Data" : "Instruction",
466 field, regs->cp0_epc, field, regs->regs[31]);
467 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr,
468 SIGBUS) == NOTIFY_STOP)
469 goto out;
470
471 die_if_kernel("Oops", regs);
472 force_sig(SIGBUS, current);
473
474 out:
475 exception_exit(prev_state);
476 }
477
478 /*
479 * ll/sc, rdhwr, sync emulation
480 */
481
482 #define OPCODE 0xfc000000
483 #define BASE 0x03e00000
484 #define RT 0x001f0000
485 #define OFFSET 0x0000ffff
486 #define LL 0xc0000000
487 #define SC 0xe0000000
488 #define SPEC0 0x00000000
489 #define SPEC3 0x7c000000
490 #define RD 0x0000f800
491 #define FUNC 0x0000003f
492 #define SYNC 0x0000000f
493 #define RDHWR 0x0000003b
494
495 /* microMIPS definitions */
496 #define MM_POOL32A_FUNC 0xfc00ffff
497 #define MM_RDHWR 0x00006b3c
498 #define MM_RS 0x001f0000
499 #define MM_RT 0x03e00000
500
501 /*
502 * The ll_bit is cleared by r*_switch.S
503 */
504
505 unsigned int ll_bit;
506 struct task_struct *ll_task;
507
508 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
509 {
510 unsigned long value, __user *vaddr;
511 long offset;
512
513 /*
514 * analyse the ll instruction that just caused a ri exception
515 * and put the referenced address to addr.
516 */
517
518 /* sign extend offset */
519 offset = opcode & OFFSET;
520 offset <<= 16;
521 offset >>= 16;
522
523 vaddr = (unsigned long __user *)
524 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
525
526 if ((unsigned long)vaddr & 3)
527 return SIGBUS;
528 if (get_user(value, vaddr))
529 return SIGSEGV;
530
531 preempt_disable();
532
533 if (ll_task == NULL || ll_task == current) {
534 ll_bit = 1;
535 } else {
536 ll_bit = 0;
537 }
538 ll_task = current;
539
540 preempt_enable();
541
542 regs->regs[(opcode & RT) >> 16] = value;
543
544 return 0;
545 }
546
547 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
548 {
549 unsigned long __user *vaddr;
550 unsigned long reg;
551 long offset;
552
553 /*
554 * analyse the sc instruction that just caused a ri exception
555 * and put the referenced address to addr.
556 */
557
558 /* sign extend offset */
559 offset = opcode & OFFSET;
560 offset <<= 16;
561 offset >>= 16;
562
563 vaddr = (unsigned long __user *)
564 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
565 reg = (opcode & RT) >> 16;
566
567 if ((unsigned long)vaddr & 3)
568 return SIGBUS;
569
570 preempt_disable();
571
572 if (ll_bit == 0 || ll_task != current) {
573 regs->regs[reg] = 0;
574 preempt_enable();
575 return 0;
576 }
577
578 preempt_enable();
579
580 if (put_user(regs->regs[reg], vaddr))
581 return SIGSEGV;
582
583 regs->regs[reg] = 1;
584
585 return 0;
586 }
587
588 /*
589 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
590 * opcodes are supposed to result in coprocessor unusable exceptions if
591 * executed on ll/sc-less processors. That's the theory. In practice a
592 * few processors such as NEC's VR4100 throw reserved instruction exceptions
593 * instead, so we're doing the emulation thing in both exception handlers.
594 */
595 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
596 {
597 if ((opcode & OPCODE) == LL) {
598 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
599 1, regs, 0);
600 return simulate_ll(regs, opcode);
601 }
602 if ((opcode & OPCODE) == SC) {
603 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
604 1, regs, 0);
605 return simulate_sc(regs, opcode);
606 }
607
608 return -1; /* Must be something else ... */
609 }
610
611 /*
612 * Simulate trapping 'rdhwr' instructions to provide user accessible
613 * registers not implemented in hardware.
614 */
615 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
616 {
617 struct thread_info *ti = task_thread_info(current);
618
619 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
620 1, regs, 0);
621 switch (rd) {
622 case MIPS_HWR_CPUNUM: /* CPU number */
623 regs->regs[rt] = smp_processor_id();
624 return 0;
625 case MIPS_HWR_SYNCISTEP: /* SYNCI length */
626 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
627 current_cpu_data.icache.linesz);
628 return 0;
629 case MIPS_HWR_CC: /* Read count register */
630 regs->regs[rt] = read_c0_count();
631 return 0;
632 case MIPS_HWR_CCRES: /* Count register resolution */
633 switch (current_cpu_type()) {
634 case CPU_20KC:
635 case CPU_25KF:
636 regs->regs[rt] = 1;
637 break;
638 default:
639 regs->regs[rt] = 2;
640 }
641 return 0;
642 case MIPS_HWR_ULR: /* Read UserLocal register */
643 regs->regs[rt] = ti->tp_value;
644 return 0;
645 default:
646 return -1;
647 }
648 }
649
650 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
651 {
652 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
653 int rd = (opcode & RD) >> 11;
654 int rt = (opcode & RT) >> 16;
655
656 simulate_rdhwr(regs, rd, rt);
657 return 0;
658 }
659
660 /* Not ours. */
661 return -1;
662 }
663
664 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode)
665 {
666 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
667 int rd = (opcode & MM_RS) >> 16;
668 int rt = (opcode & MM_RT) >> 21;
669 simulate_rdhwr(regs, rd, rt);
670 return 0;
671 }
672
673 /* Not ours. */
674 return -1;
675 }
676
677 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
678 {
679 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
680 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
681 1, regs, 0);
682 return 0;
683 }
684
685 return -1; /* Must be something else ... */
686 }
687
688 asmlinkage void do_ov(struct pt_regs *regs)
689 {
690 enum ctx_state prev_state;
691 siginfo_t info = {
692 .si_signo = SIGFPE,
693 .si_code = FPE_INTOVF,
694 .si_addr = (void __user *)regs->cp0_epc,
695 };
696
697 prev_state = exception_enter();
698 die_if_kernel("Integer overflow", regs);
699
700 force_sig_info(SIGFPE, &info, current);
701 exception_exit(prev_state);
702 }
703
704 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
705 {
706 struct siginfo si = { 0 };
707 struct vm_area_struct *vma;
708
709 switch (sig) {
710 case 0:
711 return 0;
712
713 case SIGFPE:
714 si.si_addr = fault_addr;
715 si.si_signo = sig;
716 /*
717 * Inexact can happen together with Overflow or Underflow.
718 * Respect the mask to deliver the correct exception.
719 */
720 fcr31 &= (fcr31 & FPU_CSR_ALL_E) <<
721 (ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E));
722 if (fcr31 & FPU_CSR_INV_X)
723 si.si_code = FPE_FLTINV;
724 else if (fcr31 & FPU_CSR_DIV_X)
725 si.si_code = FPE_FLTDIV;
726 else if (fcr31 & FPU_CSR_OVF_X)
727 si.si_code = FPE_FLTOVF;
728 else if (fcr31 & FPU_CSR_UDF_X)
729 si.si_code = FPE_FLTUND;
730 else if (fcr31 & FPU_CSR_INE_X)
731 si.si_code = FPE_FLTRES;
732 else
733 si.si_code = __SI_FAULT;
734 force_sig_info(sig, &si, current);
735 return 1;
736
737 case SIGBUS:
738 si.si_addr = fault_addr;
739 si.si_signo = sig;
740 si.si_code = BUS_ADRERR;
741 force_sig_info(sig, &si, current);
742 return 1;
743
744 case SIGSEGV:
745 si.si_addr = fault_addr;
746 si.si_signo = sig;
747 down_read(&current->mm->mmap_sem);
748 vma = find_vma(current->mm, (unsigned long)fault_addr);
749 if (vma && (vma->vm_start <= (unsigned long)fault_addr))
750 si.si_code = SEGV_ACCERR;
751 else
752 si.si_code = SEGV_MAPERR;
753 up_read(&current->mm->mmap_sem);
754 force_sig_info(sig, &si, current);
755 return 1;
756
757 default:
758 force_sig(sig, current);
759 return 1;
760 }
761 }
762
763 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
764 unsigned long old_epc, unsigned long old_ra)
765 {
766 union mips_instruction inst = { .word = opcode };
767 void __user *fault_addr;
768 unsigned long fcr31;
769 int sig;
770
771 /* If it's obviously not an FP instruction, skip it */
772 switch (inst.i_format.opcode) {
773 case cop1_op:
774 case cop1x_op:
775 case lwc1_op:
776 case ldc1_op:
777 case swc1_op:
778 case sdc1_op:
779 break;
780
781 default:
782 return -1;
783 }
784
785 /*
786 * do_ri skipped over the instruction via compute_return_epc, undo
787 * that for the FPU emulator.
788 */
789 regs->cp0_epc = old_epc;
790 regs->regs[31] = old_ra;
791
792 /* Save the FP context to struct thread_struct */
793 lose_fpu(1);
794
795 /* Run the emulator */
796 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
797 &fault_addr);
798 fcr31 = current->thread.fpu.fcr31;
799
800 /*
801 * We can't allow the emulated instruction to leave any of
802 * the cause bits set in $fcr31.
803 */
804 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
805
806 /* Restore the hardware register state */
807 own_fpu(1);
808
809 /* Send a signal if required. */
810 process_fpemu_return(sig, fault_addr, fcr31);
811
812 return 0;
813 }
814
815 /*
816 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
817 */
818 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
819 {
820 enum ctx_state prev_state;
821 void __user *fault_addr;
822 int sig;
823
824 prev_state = exception_enter();
825 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
826 SIGFPE) == NOTIFY_STOP)
827 goto out;
828
829 /* Clear FCSR.Cause before enabling interrupts */
830 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~FPU_CSR_ALL_X);
831 local_irq_enable();
832
833 die_if_kernel("FP exception in kernel code", regs);
834
835 if (fcr31 & FPU_CSR_UNI_X) {
836 /*
837 * Unimplemented operation exception. If we've got the full
838 * software emulator on-board, let's use it...
839 *
840 * Force FPU to dump state into task/thread context. We're
841 * moving a lot of data here for what is probably a single
842 * instruction, but the alternative is to pre-decode the FP
843 * register operands before invoking the emulator, which seems
844 * a bit extreme for what should be an infrequent event.
845 */
846 /* Ensure 'resume' not overwrite saved fp context again. */
847 lose_fpu(1);
848
849 /* Run the emulator */
850 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
851 &fault_addr);
852 fcr31 = current->thread.fpu.fcr31;
853
854 /*
855 * We can't allow the emulated instruction to leave any of
856 * the cause bits set in $fcr31.
857 */
858 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
859
860 /* Restore the hardware register state */
861 own_fpu(1); /* Using the FPU again. */
862 } else {
863 sig = SIGFPE;
864 fault_addr = (void __user *) regs->cp0_epc;
865 }
866
867 /* Send a signal if required. */
868 process_fpemu_return(sig, fault_addr, fcr31);
869
870 out:
871 exception_exit(prev_state);
872 }
873
874 void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
875 const char *str)
876 {
877 siginfo_t info = { 0 };
878 char b[40];
879
880 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
881 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr,
882 SIGTRAP) == NOTIFY_STOP)
883 return;
884 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
885
886 if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr,
887 SIGTRAP) == NOTIFY_STOP)
888 return;
889
890 /*
891 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
892 * insns, even for trap and break codes that indicate arithmetic
893 * failures. Weird ...
894 * But should we continue the brokenness??? --macro
895 */
896 switch (code) {
897 case BRK_OVERFLOW:
898 case BRK_DIVZERO:
899 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
900 die_if_kernel(b, regs);
901 if (code == BRK_DIVZERO)
902 info.si_code = FPE_INTDIV;
903 else
904 info.si_code = FPE_INTOVF;
905 info.si_signo = SIGFPE;
906 info.si_addr = (void __user *) regs->cp0_epc;
907 force_sig_info(SIGFPE, &info, current);
908 break;
909 case BRK_BUG:
910 die_if_kernel("Kernel bug detected", regs);
911 force_sig(SIGTRAP, current);
912 break;
913 case BRK_MEMU:
914 /*
915 * This breakpoint code is used by the FPU emulator to retake
916 * control of the CPU after executing the instruction from the
917 * delay slot of an emulated branch.
918 *
919 * Terminate if exception was recognized as a delay slot return
920 * otherwise handle as normal.
921 */
922 if (do_dsemulret(regs))
923 return;
924
925 die_if_kernel("Math emu break/trap", regs);
926 force_sig(SIGTRAP, current);
927 break;
928 default:
929 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
930 die_if_kernel(b, regs);
931 if (si_code) {
932 info.si_signo = SIGTRAP;
933 info.si_code = si_code;
934 force_sig_info(SIGTRAP, &info, current);
935 } else {
936 force_sig(SIGTRAP, current);
937 }
938 }
939 }
940
941 asmlinkage void do_bp(struct pt_regs *regs)
942 {
943 unsigned long epc = msk_isa16_mode(exception_epc(regs));
944 unsigned int opcode, bcode;
945 enum ctx_state prev_state;
946 mm_segment_t seg;
947
948 seg = get_fs();
949 if (!user_mode(regs))
950 set_fs(KERNEL_DS);
951
952 prev_state = exception_enter();
953 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
954 if (get_isa16_mode(regs->cp0_epc)) {
955 u16 instr[2];
956
957 if (__get_user(instr[0], (u16 __user *)epc))
958 goto out_sigsegv;
959
960 if (!cpu_has_mmips) {
961 /* MIPS16e mode */
962 bcode = (instr[0] >> 5) & 0x3f;
963 } else if (mm_insn_16bit(instr[0])) {
964 /* 16-bit microMIPS BREAK */
965 bcode = instr[0] & 0xf;
966 } else {
967 /* 32-bit microMIPS BREAK */
968 if (__get_user(instr[1], (u16 __user *)(epc + 2)))
969 goto out_sigsegv;
970 opcode = (instr[0] << 16) | instr[1];
971 bcode = (opcode >> 6) & ((1 << 20) - 1);
972 }
973 } else {
974 if (__get_user(opcode, (unsigned int __user *)epc))
975 goto out_sigsegv;
976 bcode = (opcode >> 6) & ((1 << 20) - 1);
977 }
978
979 /*
980 * There is the ancient bug in the MIPS assemblers that the break
981 * code starts left to bit 16 instead to bit 6 in the opcode.
982 * Gas is bug-compatible, but not always, grrr...
983 * We handle both cases with a simple heuristics. --macro
984 */
985 if (bcode >= (1 << 10))
986 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
987
988 /*
989 * notify the kprobe handlers, if instruction is likely to
990 * pertain to them.
991 */
992 switch (bcode) {
993 case BRK_UPROBE:
994 if (notify_die(DIE_UPROBE, "uprobe", regs, bcode,
995 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
996 goto out;
997 else
998 break;
999 case BRK_UPROBE_XOL:
1000 if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode,
1001 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1002 goto out;
1003 else
1004 break;
1005 case BRK_KPROBE_BP:
1006 if (notify_die(DIE_BREAK, "debug", regs, bcode,
1007 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1008 goto out;
1009 else
1010 break;
1011 case BRK_KPROBE_SSTEPBP:
1012 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
1013 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1014 goto out;
1015 else
1016 break;
1017 default:
1018 break;
1019 }
1020
1021 do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break");
1022
1023 out:
1024 set_fs(seg);
1025 exception_exit(prev_state);
1026 return;
1027
1028 out_sigsegv:
1029 force_sig(SIGSEGV, current);
1030 goto out;
1031 }
1032
1033 asmlinkage void do_tr(struct pt_regs *regs)
1034 {
1035 u32 opcode, tcode = 0;
1036 enum ctx_state prev_state;
1037 u16 instr[2];
1038 mm_segment_t seg;
1039 unsigned long epc = msk_isa16_mode(exception_epc(regs));
1040
1041 seg = get_fs();
1042 if (!user_mode(regs))
1043 set_fs(get_ds());
1044
1045 prev_state = exception_enter();
1046 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1047 if (get_isa16_mode(regs->cp0_epc)) {
1048 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
1049 __get_user(instr[1], (u16 __user *)(epc + 2)))
1050 goto out_sigsegv;
1051 opcode = (instr[0] << 16) | instr[1];
1052 /* Immediate versions don't provide a code. */
1053 if (!(opcode & OPCODE))
1054 tcode = (opcode >> 12) & ((1 << 4) - 1);
1055 } else {
1056 if (__get_user(opcode, (u32 __user *)epc))
1057 goto out_sigsegv;
1058 /* Immediate versions don't provide a code. */
1059 if (!(opcode & OPCODE))
1060 tcode = (opcode >> 6) & ((1 << 10) - 1);
1061 }
1062
1063 do_trap_or_bp(regs, tcode, 0, "Trap");
1064
1065 out:
1066 set_fs(seg);
1067 exception_exit(prev_state);
1068 return;
1069
1070 out_sigsegv:
1071 force_sig(SIGSEGV, current);
1072 goto out;
1073 }
1074
1075 asmlinkage void do_ri(struct pt_regs *regs)
1076 {
1077 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
1078 unsigned long old_epc = regs->cp0_epc;
1079 unsigned long old31 = regs->regs[31];
1080 enum ctx_state prev_state;
1081 unsigned int opcode = 0;
1082 int status = -1;
1083
1084 /*
1085 * Avoid any kernel code. Just emulate the R2 instruction
1086 * as quickly as possible.
1087 */
1088 if (mipsr2_emulation && cpu_has_mips_r6 &&
1089 likely(user_mode(regs)) &&
1090 likely(get_user(opcode, epc) >= 0)) {
1091 unsigned long fcr31 = 0;
1092
1093 status = mipsr2_decoder(regs, opcode, &fcr31);
1094 switch (status) {
1095 case 0:
1096 case SIGEMT:
1097 task_thread_info(current)->r2_emul_return = 1;
1098 return;
1099 case SIGILL:
1100 goto no_r2_instr;
1101 default:
1102 process_fpemu_return(status,
1103 &current->thread.cp0_baduaddr,
1104 fcr31);
1105 task_thread_info(current)->r2_emul_return = 1;
1106 return;
1107 }
1108 }
1109
1110 no_r2_instr:
1111
1112 prev_state = exception_enter();
1113 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1114
1115 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
1116 SIGILL) == NOTIFY_STOP)
1117 goto out;
1118
1119 die_if_kernel("Reserved instruction in kernel code", regs);
1120
1121 if (unlikely(compute_return_epc(regs) < 0))
1122 goto out;
1123
1124 if (!get_isa16_mode(regs->cp0_epc)) {
1125 if (unlikely(get_user(opcode, epc) < 0))
1126 status = SIGSEGV;
1127
1128 if (!cpu_has_llsc && status < 0)
1129 status = simulate_llsc(regs, opcode);
1130
1131 if (status < 0)
1132 status = simulate_rdhwr_normal(regs, opcode);
1133
1134 if (status < 0)
1135 status = simulate_sync(regs, opcode);
1136
1137 if (status < 0)
1138 status = simulate_fp(regs, opcode, old_epc, old31);
1139 } else if (cpu_has_mmips) {
1140 unsigned short mmop[2] = { 0 };
1141
1142 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
1143 status = SIGSEGV;
1144 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
1145 status = SIGSEGV;
1146 opcode = mmop[0];
1147 opcode = (opcode << 16) | mmop[1];
1148
1149 if (status < 0)
1150 status = simulate_rdhwr_mm(regs, opcode);
1151 }
1152
1153 if (status < 0)
1154 status = SIGILL;
1155
1156 if (unlikely(status > 0)) {
1157 regs->cp0_epc = old_epc; /* Undo skip-over. */
1158 regs->regs[31] = old31;
1159 force_sig(status, current);
1160 }
1161
1162 out:
1163 exception_exit(prev_state);
1164 }
1165
1166 /*
1167 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1168 * emulated more than some threshold number of instructions, force migration to
1169 * a "CPU" that has FP support.
1170 */
1171 static void mt_ase_fp_affinity(void)
1172 {
1173 #ifdef CONFIG_MIPS_MT_FPAFF
1174 if (mt_fpemul_threshold > 0 &&
1175 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1176 /*
1177 * If there's no FPU present, or if the application has already
1178 * restricted the allowed set to exclude any CPUs with FPUs,
1179 * we'll skip the procedure.
1180 */
1181 if (cpumask_intersects(&current->cpus_allowed, &mt_fpu_cpumask)) {
1182 cpumask_t tmask;
1183
1184 current->thread.user_cpus_allowed
1185 = current->cpus_allowed;
1186 cpumask_and(&tmask, &current->cpus_allowed,
1187 &mt_fpu_cpumask);
1188 set_cpus_allowed_ptr(current, &tmask);
1189 set_thread_flag(TIF_FPUBOUND);
1190 }
1191 }
1192 #endif /* CONFIG_MIPS_MT_FPAFF */
1193 }
1194
1195 /*
1196 * No lock; only written during early bootup by CPU 0.
1197 */
1198 static RAW_NOTIFIER_HEAD(cu2_chain);
1199
1200 int __ref register_cu2_notifier(struct notifier_block *nb)
1201 {
1202 return raw_notifier_chain_register(&cu2_chain, nb);
1203 }
1204
1205 int cu2_notifier_call_chain(unsigned long val, void *v)
1206 {
1207 return raw_notifier_call_chain(&cu2_chain, val, v);
1208 }
1209
1210 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1211 void *data)
1212 {
1213 struct pt_regs *regs = data;
1214
1215 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1216 "instruction", regs);
1217 force_sig(SIGILL, current);
1218
1219 return NOTIFY_OK;
1220 }
1221
1222 static int wait_on_fp_mode_switch(atomic_t *p)
1223 {
1224 /*
1225 * The FP mode for this task is currently being switched. That may
1226 * involve modifications to the format of this tasks FP context which
1227 * make it unsafe to proceed with execution for the moment. Instead,
1228 * schedule some other task.
1229 */
1230 schedule();
1231 return 0;
1232 }
1233
1234 static int enable_restore_fp_context(int msa)
1235 {
1236 int err, was_fpu_owner, prior_msa;
1237
1238 /*
1239 * If an FP mode switch is currently underway, wait for it to
1240 * complete before proceeding.
1241 */
1242 wait_on_atomic_t(&current->mm->context.fp_mode_switching,
1243 wait_on_fp_mode_switch, TASK_KILLABLE);
1244
1245 if (!used_math()) {
1246 /* First time FP context user. */
1247 preempt_disable();
1248 err = init_fpu();
1249 if (msa && !err) {
1250 enable_msa();
1251 init_msa_upper();
1252 set_thread_flag(TIF_USEDMSA);
1253 set_thread_flag(TIF_MSA_CTX_LIVE);
1254 }
1255 preempt_enable();
1256 if (!err)
1257 set_used_math();
1258 return err;
1259 }
1260
1261 /*
1262 * This task has formerly used the FP context.
1263 *
1264 * If this thread has no live MSA vector context then we can simply
1265 * restore the scalar FP context. If it has live MSA vector context
1266 * (that is, it has or may have used MSA since last performing a
1267 * function call) then we'll need to restore the vector context. This
1268 * applies even if we're currently only executing a scalar FP
1269 * instruction. This is because if we were to later execute an MSA
1270 * instruction then we'd either have to:
1271 *
1272 * - Restore the vector context & clobber any registers modified by
1273 * scalar FP instructions between now & then.
1274 *
1275 * or
1276 *
1277 * - Not restore the vector context & lose the most significant bits
1278 * of all vector registers.
1279 *
1280 * Neither of those options is acceptable. We cannot restore the least
1281 * significant bits of the registers now & only restore the most
1282 * significant bits later because the most significant bits of any
1283 * vector registers whose aliased FP register is modified now will have
1284 * been zeroed. We'd have no way to know that when restoring the vector
1285 * context & thus may load an outdated value for the most significant
1286 * bits of a vector register.
1287 */
1288 if (!msa && !thread_msa_context_live())
1289 return own_fpu(1);
1290
1291 /*
1292 * This task is using or has previously used MSA. Thus we require
1293 * that Status.FR == 1.
1294 */
1295 preempt_disable();
1296 was_fpu_owner = is_fpu_owner();
1297 err = own_fpu_inatomic(0);
1298 if (err)
1299 goto out;
1300
1301 enable_msa();
1302 write_msa_csr(current->thread.fpu.msacsr);
1303 set_thread_flag(TIF_USEDMSA);
1304
1305 /*
1306 * If this is the first time that the task is using MSA and it has
1307 * previously used scalar FP in this time slice then we already nave
1308 * FP context which we shouldn't clobber. We do however need to clear
1309 * the upper 64b of each vector register so that this task has no
1310 * opportunity to see data left behind by another.
1311 */
1312 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1313 if (!prior_msa && was_fpu_owner) {
1314 init_msa_upper();
1315
1316 goto out;
1317 }
1318
1319 if (!prior_msa) {
1320 /*
1321 * Restore the least significant 64b of each vector register
1322 * from the existing scalar FP context.
1323 */
1324 _restore_fp(current);
1325
1326 /*
1327 * The task has not formerly used MSA, so clear the upper 64b
1328 * of each vector register such that it cannot see data left
1329 * behind by another task.
1330 */
1331 init_msa_upper();
1332 } else {
1333 /* We need to restore the vector context. */
1334 restore_msa(current);
1335
1336 /* Restore the scalar FP control & status register */
1337 if (!was_fpu_owner)
1338 write_32bit_cp1_register(CP1_STATUS,
1339 current->thread.fpu.fcr31);
1340 }
1341
1342 out:
1343 preempt_enable();
1344
1345 return 0;
1346 }
1347
1348 asmlinkage void do_cpu(struct pt_regs *regs)
1349 {
1350 enum ctx_state prev_state;
1351 unsigned int __user *epc;
1352 unsigned long old_epc, old31;
1353 void __user *fault_addr;
1354 unsigned int opcode;
1355 unsigned long fcr31;
1356 unsigned int cpid;
1357 int status, err;
1358 int sig;
1359
1360 prev_state = exception_enter();
1361 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1362
1363 if (cpid != 2)
1364 die_if_kernel("do_cpu invoked from kernel context!", regs);
1365
1366 switch (cpid) {
1367 case 0:
1368 epc = (unsigned int __user *)exception_epc(regs);
1369 old_epc = regs->cp0_epc;
1370 old31 = regs->regs[31];
1371 opcode = 0;
1372 status = -1;
1373
1374 if (unlikely(compute_return_epc(regs) < 0))
1375 break;
1376
1377 if (!get_isa16_mode(regs->cp0_epc)) {
1378 if (unlikely(get_user(opcode, epc) < 0))
1379 status = SIGSEGV;
1380
1381 if (!cpu_has_llsc && status < 0)
1382 status = simulate_llsc(regs, opcode);
1383 }
1384
1385 if (status < 0)
1386 status = SIGILL;
1387
1388 if (unlikely(status > 0)) {
1389 regs->cp0_epc = old_epc; /* Undo skip-over. */
1390 regs->regs[31] = old31;
1391 force_sig(status, current);
1392 }
1393
1394 break;
1395
1396 case 3:
1397 /*
1398 * The COP3 opcode space and consequently the CP0.Status.CU3
1399 * bit and the CP0.Cause.CE=3 encoding have been removed as
1400 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
1401 * up the space has been reused for COP1X instructions, that
1402 * are enabled by the CP0.Status.CU1 bit and consequently
1403 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
1404 * exceptions. Some FPU-less processors that implement one
1405 * of these ISAs however use this code erroneously for COP1X
1406 * instructions. Therefore we redirect this trap to the FP
1407 * emulator too.
1408 */
1409 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
1410 force_sig(SIGILL, current);
1411 break;
1412 }
1413 /* Fall through. */
1414
1415 case 1:
1416 err = enable_restore_fp_context(0);
1417
1418 if (raw_cpu_has_fpu && !err)
1419 break;
1420
1421 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 0,
1422 &fault_addr);
1423 fcr31 = current->thread.fpu.fcr31;
1424
1425 /*
1426 * We can't allow the emulated instruction to leave
1427 * any of the cause bits set in $fcr31.
1428 */
1429 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
1430
1431 /* Send a signal if required. */
1432 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
1433 mt_ase_fp_affinity();
1434
1435 break;
1436
1437 case 2:
1438 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1439 break;
1440 }
1441
1442 exception_exit(prev_state);
1443 }
1444
1445 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
1446 {
1447 enum ctx_state prev_state;
1448
1449 prev_state = exception_enter();
1450 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1451 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
1452 current->thread.trap_nr, SIGFPE) == NOTIFY_STOP)
1453 goto out;
1454
1455 /* Clear MSACSR.Cause before enabling interrupts */
1456 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
1457 local_irq_enable();
1458
1459 die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
1460 force_sig(SIGFPE, current);
1461 out:
1462 exception_exit(prev_state);
1463 }
1464
1465 asmlinkage void do_msa(struct pt_regs *regs)
1466 {
1467 enum ctx_state prev_state;
1468 int err;
1469
1470 prev_state = exception_enter();
1471
1472 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
1473 force_sig(SIGILL, current);
1474 goto out;
1475 }
1476
1477 die_if_kernel("do_msa invoked from kernel context!", regs);
1478
1479 err = enable_restore_fp_context(1);
1480 if (err)
1481 force_sig(SIGILL, current);
1482 out:
1483 exception_exit(prev_state);
1484 }
1485
1486 asmlinkage void do_mdmx(struct pt_regs *regs)
1487 {
1488 enum ctx_state prev_state;
1489
1490 prev_state = exception_enter();
1491 force_sig(SIGILL, current);
1492 exception_exit(prev_state);
1493 }
1494
1495 /*
1496 * Called with interrupts disabled.
1497 */
1498 asmlinkage void do_watch(struct pt_regs *regs)
1499 {
1500 siginfo_t info = { .si_signo = SIGTRAP, .si_code = TRAP_HWBKPT };
1501 enum ctx_state prev_state;
1502
1503 prev_state = exception_enter();
1504 /*
1505 * Clear WP (bit 22) bit of cause register so we don't loop
1506 * forever.
1507 */
1508 clear_c0_cause(CAUSEF_WP);
1509
1510 /*
1511 * If the current thread has the watch registers loaded, save
1512 * their values and send SIGTRAP. Otherwise another thread
1513 * left the registers set, clear them and continue.
1514 */
1515 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1516 mips_read_watch_registers();
1517 local_irq_enable();
1518 force_sig_info(SIGTRAP, &info, current);
1519 } else {
1520 mips_clear_watch_registers();
1521 local_irq_enable();
1522 }
1523 exception_exit(prev_state);
1524 }
1525
1526 asmlinkage void do_mcheck(struct pt_regs *regs)
1527 {
1528 int multi_match = regs->cp0_status & ST0_TS;
1529 enum ctx_state prev_state;
1530 mm_segment_t old_fs = get_fs();
1531
1532 prev_state = exception_enter();
1533 show_regs(regs);
1534
1535 if (multi_match) {
1536 dump_tlb_regs();
1537 pr_info("\n");
1538 dump_tlb_all();
1539 }
1540
1541 if (!user_mode(regs))
1542 set_fs(KERNEL_DS);
1543
1544 show_code((unsigned int __user *) regs->cp0_epc);
1545
1546 set_fs(old_fs);
1547
1548 /*
1549 * Some chips may have other causes of machine check (e.g. SB1
1550 * graduation timer)
1551 */
1552 panic("Caught Machine Check exception - %scaused by multiple "
1553 "matching entries in the TLB.",
1554 (multi_match) ? "" : "not ");
1555 }
1556
1557 asmlinkage void do_mt(struct pt_regs *regs)
1558 {
1559 int subcode;
1560
1561 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1562 >> VPECONTROL_EXCPT_SHIFT;
1563 switch (subcode) {
1564 case 0:
1565 printk(KERN_DEBUG "Thread Underflow\n");
1566 break;
1567 case 1:
1568 printk(KERN_DEBUG "Thread Overflow\n");
1569 break;
1570 case 2:
1571 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1572 break;
1573 case 3:
1574 printk(KERN_DEBUG "Gating Storage Exception\n");
1575 break;
1576 case 4:
1577 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1578 break;
1579 case 5:
1580 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1581 break;
1582 default:
1583 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1584 subcode);
1585 break;
1586 }
1587 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1588
1589 force_sig(SIGILL, current);
1590 }
1591
1592
1593 asmlinkage void do_dsp(struct pt_regs *regs)
1594 {
1595 if (cpu_has_dsp)
1596 panic("Unexpected DSP exception");
1597
1598 force_sig(SIGILL, current);
1599 }
1600
1601 asmlinkage void do_reserved(struct pt_regs *regs)
1602 {
1603 /*
1604 * Game over - no way to handle this if it ever occurs. Most probably
1605 * caused by a new unknown cpu type or after another deadly
1606 * hard/software error.
1607 */
1608 show_regs(regs);
1609 panic("Caught reserved exception %ld - should not happen.",
1610 (regs->cp0_cause & 0x7f) >> 2);
1611 }
1612
1613 static int __initdata l1parity = 1;
1614 static int __init nol1parity(char *s)
1615 {
1616 l1parity = 0;
1617 return 1;
1618 }
1619 __setup("nol1par", nol1parity);
1620 static int __initdata l2parity = 1;
1621 static int __init nol2parity(char *s)
1622 {
1623 l2parity = 0;
1624 return 1;
1625 }
1626 __setup("nol2par", nol2parity);
1627
1628 /*
1629 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1630 * it different ways.
1631 */
1632 static inline void parity_protection_init(void)
1633 {
1634 switch (current_cpu_type()) {
1635 case CPU_24K:
1636 case CPU_34K:
1637 case CPU_74K:
1638 case CPU_1004K:
1639 case CPU_1074K:
1640 case CPU_INTERAPTIV:
1641 case CPU_PROAPTIV:
1642 case CPU_P5600:
1643 case CPU_QEMU_GENERIC:
1644 case CPU_I6400:
1645 case CPU_P6600:
1646 {
1647 #define ERRCTL_PE 0x80000000
1648 #define ERRCTL_L2P 0x00800000
1649 unsigned long errctl;
1650 unsigned int l1parity_present, l2parity_present;
1651
1652 errctl = read_c0_ecc();
1653 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1654
1655 /* probe L1 parity support */
1656 write_c0_ecc(errctl | ERRCTL_PE);
1657 back_to_back_c0_hazard();
1658 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1659
1660 /* probe L2 parity support */
1661 write_c0_ecc(errctl|ERRCTL_L2P);
1662 back_to_back_c0_hazard();
1663 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1664
1665 if (l1parity_present && l2parity_present) {
1666 if (l1parity)
1667 errctl |= ERRCTL_PE;
1668 if (l1parity ^ l2parity)
1669 errctl |= ERRCTL_L2P;
1670 } else if (l1parity_present) {
1671 if (l1parity)
1672 errctl |= ERRCTL_PE;
1673 } else if (l2parity_present) {
1674 if (l2parity)
1675 errctl |= ERRCTL_L2P;
1676 } else {
1677 /* No parity available */
1678 }
1679
1680 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1681
1682 write_c0_ecc(errctl);
1683 back_to_back_c0_hazard();
1684 errctl = read_c0_ecc();
1685 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1686
1687 if (l1parity_present)
1688 printk(KERN_INFO "Cache parity protection %sabled\n",
1689 (errctl & ERRCTL_PE) ? "en" : "dis");
1690
1691 if (l2parity_present) {
1692 if (l1parity_present && l1parity)
1693 errctl ^= ERRCTL_L2P;
1694 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1695 (errctl & ERRCTL_L2P) ? "en" : "dis");
1696 }
1697 }
1698 break;
1699
1700 case CPU_5KC:
1701 case CPU_5KE:
1702 case CPU_LOONGSON1:
1703 write_c0_ecc(0x80000000);
1704 back_to_back_c0_hazard();
1705 /* Set the PE bit (bit 31) in the c0_errctl register. */
1706 printk(KERN_INFO "Cache parity protection %sabled\n",
1707 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1708 break;
1709 case CPU_20KC:
1710 case CPU_25KF:
1711 /* Clear the DE bit (bit 16) in the c0_status register. */
1712 printk(KERN_INFO "Enable cache parity protection for "
1713 "MIPS 20KC/25KF CPUs.\n");
1714 clear_c0_status(ST0_DE);
1715 break;
1716 default:
1717 break;
1718 }
1719 }
1720
1721 asmlinkage void cache_parity_error(void)
1722 {
1723 const int field = 2 * sizeof(unsigned long);
1724 unsigned int reg_val;
1725
1726 /* For the moment, report the problem and hang. */
1727 printk("Cache error exception:\n");
1728 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1729 reg_val = read_c0_cacheerr();
1730 printk("c0_cacheerr == %08x\n", reg_val);
1731
1732 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1733 reg_val & (1<<30) ? "secondary" : "primary",
1734 reg_val & (1<<31) ? "data" : "insn");
1735 if ((cpu_has_mips_r2_r6) &&
1736 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1737 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1738 reg_val & (1<<29) ? "ED " : "",
1739 reg_val & (1<<28) ? "ET " : "",
1740 reg_val & (1<<27) ? "ES " : "",
1741 reg_val & (1<<26) ? "EE " : "",
1742 reg_val & (1<<25) ? "EB " : "",
1743 reg_val & (1<<24) ? "EI " : "",
1744 reg_val & (1<<23) ? "E1 " : "",
1745 reg_val & (1<<22) ? "E0 " : "");
1746 } else {
1747 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1748 reg_val & (1<<29) ? "ED " : "",
1749 reg_val & (1<<28) ? "ET " : "",
1750 reg_val & (1<<26) ? "EE " : "",
1751 reg_val & (1<<25) ? "EB " : "",
1752 reg_val & (1<<24) ? "EI " : "",
1753 reg_val & (1<<23) ? "E1 " : "",
1754 reg_val & (1<<22) ? "E0 " : "");
1755 }
1756 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1757
1758 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1759 if (reg_val & (1<<22))
1760 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1761
1762 if (reg_val & (1<<23))
1763 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1764 #endif
1765
1766 panic("Can't handle the cache error!");
1767 }
1768
1769 asmlinkage void do_ftlb(void)
1770 {
1771 const int field = 2 * sizeof(unsigned long);
1772 unsigned int reg_val;
1773
1774 /* For the moment, report the problem and hang. */
1775 if ((cpu_has_mips_r2_r6) &&
1776 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) ||
1777 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) {
1778 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1779 read_c0_ecc());
1780 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1781 reg_val = read_c0_cacheerr();
1782 pr_err("c0_cacheerr == %08x\n", reg_val);
1783
1784 if ((reg_val & 0xc0000000) == 0xc0000000) {
1785 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1786 } else {
1787 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1788 reg_val & (1<<30) ? "secondary" : "primary",
1789 reg_val & (1<<31) ? "data" : "insn");
1790 }
1791 } else {
1792 pr_err("FTLB error exception\n");
1793 }
1794 /* Just print the cacheerr bits for now */
1795 cache_parity_error();
1796 }
1797
1798 /*
1799 * SDBBP EJTAG debug exception handler.
1800 * We skip the instruction and return to the next instruction.
1801 */
1802 void ejtag_exception_handler(struct pt_regs *regs)
1803 {
1804 const int field = 2 * sizeof(unsigned long);
1805 unsigned long depc, old_epc, old_ra;
1806 unsigned int debug;
1807
1808 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1809 depc = read_c0_depc();
1810 debug = read_c0_debug();
1811 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1812 if (debug & 0x80000000) {
1813 /*
1814 * In branch delay slot.
1815 * We cheat a little bit here and use EPC to calculate the
1816 * debug return address (DEPC). EPC is restored after the
1817 * calculation.
1818 */
1819 old_epc = regs->cp0_epc;
1820 old_ra = regs->regs[31];
1821 regs->cp0_epc = depc;
1822 compute_return_epc(regs);
1823 depc = regs->cp0_epc;
1824 regs->cp0_epc = old_epc;
1825 regs->regs[31] = old_ra;
1826 } else
1827 depc += 4;
1828 write_c0_depc(depc);
1829
1830 #if 0
1831 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1832 write_c0_debug(debug | 0x100);
1833 #endif
1834 }
1835
1836 /*
1837 * NMI exception handler.
1838 * No lock; only written during early bootup by CPU 0.
1839 */
1840 static RAW_NOTIFIER_HEAD(nmi_chain);
1841
1842 int register_nmi_notifier(struct notifier_block *nb)
1843 {
1844 return raw_notifier_chain_register(&nmi_chain, nb);
1845 }
1846
1847 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1848 {
1849 char str[100];
1850
1851 nmi_enter();
1852 raw_notifier_call_chain(&nmi_chain, 0, regs);
1853 bust_spinlocks(1);
1854 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1855 smp_processor_id(), regs->cp0_epc);
1856 regs->cp0_epc = read_c0_errorepc();
1857 die(str, regs);
1858 nmi_exit();
1859 }
1860
1861 #define VECTORSPACING 0x100 /* for EI/VI mode */
1862
1863 unsigned long ebase;
1864 EXPORT_SYMBOL_GPL(ebase);
1865 unsigned long exception_handlers[32];
1866 unsigned long vi_handlers[64];
1867
1868 void __init *set_except_vector(int n, void *addr)
1869 {
1870 unsigned long handler = (unsigned long) addr;
1871 unsigned long old_handler;
1872
1873 #ifdef CONFIG_CPU_MICROMIPS
1874 /*
1875 * Only the TLB handlers are cache aligned with an even
1876 * address. All other handlers are on an odd address and
1877 * require no modification. Otherwise, MIPS32 mode will
1878 * be entered when handling any TLB exceptions. That
1879 * would be bad...since we must stay in microMIPS mode.
1880 */
1881 if (!(handler & 0x1))
1882 handler |= 1;
1883 #endif
1884 old_handler = xchg(&exception_handlers[n], handler);
1885
1886 if (n == 0 && cpu_has_divec) {
1887 #ifdef CONFIG_CPU_MICROMIPS
1888 unsigned long jump_mask = ~((1 << 27) - 1);
1889 #else
1890 unsigned long jump_mask = ~((1 << 28) - 1);
1891 #endif
1892 u32 *buf = (u32 *)(ebase + 0x200);
1893 unsigned int k0 = 26;
1894 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1895 uasm_i_j(&buf, handler & ~jump_mask);
1896 uasm_i_nop(&buf);
1897 } else {
1898 UASM_i_LA(&buf, k0, handler);
1899 uasm_i_jr(&buf, k0);
1900 uasm_i_nop(&buf);
1901 }
1902 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1903 }
1904 return (void *)old_handler;
1905 }
1906
1907 static void do_default_vi(void)
1908 {
1909 show_regs(get_irq_regs());
1910 panic("Caught unexpected vectored interrupt.");
1911 }
1912
1913 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1914 {
1915 unsigned long handler;
1916 unsigned long old_handler = vi_handlers[n];
1917 int srssets = current_cpu_data.srsets;
1918 u16 *h;
1919 unsigned char *b;
1920
1921 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1922
1923 if (addr == NULL) {
1924 handler = (unsigned long) do_default_vi;
1925 srs = 0;
1926 } else
1927 handler = (unsigned long) addr;
1928 vi_handlers[n] = handler;
1929
1930 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1931
1932 if (srs >= srssets)
1933 panic("Shadow register set %d not supported", srs);
1934
1935 if (cpu_has_veic) {
1936 if (board_bind_eic_interrupt)
1937 board_bind_eic_interrupt(n, srs);
1938 } else if (cpu_has_vint) {
1939 /* SRSMap is only defined if shadow sets are implemented */
1940 if (srssets > 1)
1941 change_c0_srsmap(0xf << n*4, srs << n*4);
1942 }
1943
1944 if (srs == 0) {
1945 /*
1946 * If no shadow set is selected then use the default handler
1947 * that does normal register saving and standard interrupt exit
1948 */
1949 extern char except_vec_vi, except_vec_vi_lui;
1950 extern char except_vec_vi_ori, except_vec_vi_end;
1951 extern char rollback_except_vec_vi;
1952 char *vec_start = using_rollback_handler() ?
1953 &rollback_except_vec_vi : &except_vec_vi;
1954 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1955 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
1956 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
1957 #else
1958 const int lui_offset = &except_vec_vi_lui - vec_start;
1959 const int ori_offset = &except_vec_vi_ori - vec_start;
1960 #endif
1961 const int handler_len = &except_vec_vi_end - vec_start;
1962
1963 if (handler_len > VECTORSPACING) {
1964 /*
1965 * Sigh... panicing won't help as the console
1966 * is probably not configured :(
1967 */
1968 panic("VECTORSPACING too small");
1969 }
1970
1971 set_handler(((unsigned long)b - ebase), vec_start,
1972 #ifdef CONFIG_CPU_MICROMIPS
1973 (handler_len - 1));
1974 #else
1975 handler_len);
1976 #endif
1977 h = (u16 *)(b + lui_offset);
1978 *h = (handler >> 16) & 0xffff;
1979 h = (u16 *)(b + ori_offset);
1980 *h = (handler & 0xffff);
1981 local_flush_icache_range((unsigned long)b,
1982 (unsigned long)(b+handler_len));
1983 }
1984 else {
1985 /*
1986 * In other cases jump directly to the interrupt handler. It
1987 * is the handler's responsibility to save registers if required
1988 * (eg hi/lo) and return from the exception using "eret".
1989 */
1990 u32 insn;
1991
1992 h = (u16 *)b;
1993 /* j handler */
1994 #ifdef CONFIG_CPU_MICROMIPS
1995 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
1996 #else
1997 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
1998 #endif
1999 h[0] = (insn >> 16) & 0xffff;
2000 h[1] = insn & 0xffff;
2001 h[2] = 0;
2002 h[3] = 0;
2003 local_flush_icache_range((unsigned long)b,
2004 (unsigned long)(b+8));
2005 }
2006
2007 return (void *)old_handler;
2008 }
2009
2010 void *set_vi_handler(int n, vi_handler_t addr)
2011 {
2012 return set_vi_srs_handler(n, addr, 0);
2013 }
2014
2015 extern void tlb_init(void);
2016
2017 /*
2018 * Timer interrupt
2019 */
2020 int cp0_compare_irq;
2021 EXPORT_SYMBOL_GPL(cp0_compare_irq);
2022 int cp0_compare_irq_shift;
2023
2024 /*
2025 * Performance counter IRQ or -1 if shared with timer
2026 */
2027 int cp0_perfcount_irq;
2028 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
2029
2030 /*
2031 * Fast debug channel IRQ or -1 if not present
2032 */
2033 int cp0_fdc_irq;
2034 EXPORT_SYMBOL_GPL(cp0_fdc_irq);
2035
2036 static int noulri;
2037
2038 static int __init ulri_disable(char *s)
2039 {
2040 pr_info("Disabling ulri\n");
2041 noulri = 1;
2042
2043 return 1;
2044 }
2045 __setup("noulri", ulri_disable);
2046
2047 /* configure STATUS register */
2048 static void configure_status(void)
2049 {
2050 /*
2051 * Disable coprocessors and select 32-bit or 64-bit addressing
2052 * and the 16/32 or 32/32 FPR register model. Reset the BEV
2053 * flag that some firmware may have left set and the TS bit (for
2054 * IP27). Set XX for ISA IV code to work.
2055 */
2056 unsigned int status_set = ST0_CU0;
2057 #ifdef CONFIG_64BIT
2058 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
2059 #endif
2060 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
2061 status_set |= ST0_XX;
2062 if (cpu_has_dsp)
2063 status_set |= ST0_MX;
2064
2065 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
2066 status_set);
2067 }
2068
2069 unsigned int hwrena;
2070 EXPORT_SYMBOL_GPL(hwrena);
2071
2072 /* configure HWRENA register */
2073 static void configure_hwrena(void)
2074 {
2075 hwrena = cpu_hwrena_impl_bits;
2076
2077 if (cpu_has_mips_r2_r6)
2078 hwrena |= MIPS_HWRENA_CPUNUM |
2079 MIPS_HWRENA_SYNCISTEP |
2080 MIPS_HWRENA_CC |
2081 MIPS_HWRENA_CCRES;
2082
2083 if (!noulri && cpu_has_userlocal)
2084 hwrena |= MIPS_HWRENA_ULR;
2085
2086 if (hwrena)
2087 write_c0_hwrena(hwrena);
2088 }
2089
2090 static void configure_exception_vector(void)
2091 {
2092 if (cpu_has_veic || cpu_has_vint) {
2093 unsigned long sr = set_c0_status(ST0_BEV);
2094 write_c0_ebase(ebase);
2095 write_c0_status(sr);
2096 /* Setting vector spacing enables EI/VI mode */
2097 change_c0_intctl(0x3e0, VECTORSPACING);
2098 }
2099 if (cpu_has_divec) {
2100 if (cpu_has_mipsmt) {
2101 unsigned int vpflags = dvpe();
2102 set_c0_cause(CAUSEF_IV);
2103 evpe(vpflags);
2104 } else
2105 set_c0_cause(CAUSEF_IV);
2106 }
2107 }
2108
2109 void per_cpu_trap_init(bool is_boot_cpu)
2110 {
2111 unsigned int cpu = smp_processor_id();
2112
2113 configure_status();
2114 configure_hwrena();
2115
2116 configure_exception_vector();
2117
2118 /*
2119 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2120 *
2121 * o read IntCtl.IPTI to determine the timer interrupt
2122 * o read IntCtl.IPPCI to determine the performance counter interrupt
2123 * o read IntCtl.IPFDC to determine the fast debug channel interrupt
2124 */
2125 if (cpu_has_mips_r2_r6) {
2126 /*
2127 * We shouldn't trust a secondary core has a sane EBASE register
2128 * so use the one calculated by the boot CPU.
2129 */
2130 if (!is_boot_cpu)
2131 write_c0_ebase(ebase);
2132
2133 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2134 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2135 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
2136 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
2137 if (!cp0_fdc_irq)
2138 cp0_fdc_irq = -1;
2139
2140 } else {
2141 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
2142 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
2143 cp0_perfcount_irq = -1;
2144 cp0_fdc_irq = -1;
2145 }
2146
2147 if (!cpu_data[cpu].asid_cache)
2148 cpu_data[cpu].asid_cache = asid_first_version(cpu);
2149
2150 atomic_inc(&init_mm.mm_count);
2151 current->active_mm = &init_mm;
2152 BUG_ON(current->mm);
2153 enter_lazy_tlb(&init_mm, current);
2154
2155 /* Boot CPU's cache setup in setup_arch(). */
2156 if (!is_boot_cpu)
2157 cpu_cache_init();
2158 tlb_init();
2159 TLBMISS_HANDLER_SETUP();
2160 }
2161
2162 /* Install CPU exception handler */
2163 void set_handler(unsigned long offset, void *addr, unsigned long size)
2164 {
2165 #ifdef CONFIG_CPU_MICROMIPS
2166 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
2167 #else
2168 memcpy((void *)(ebase + offset), addr, size);
2169 #endif
2170 local_flush_icache_range(ebase + offset, ebase + offset + size);
2171 }
2172
2173 static char panic_null_cerr[] =
2174 "Trying to set NULL cache error exception handler";
2175
2176 /*
2177 * Install uncached CPU exception handler.
2178 * This is suitable only for the cache error exception which is the only
2179 * exception handler that is being run uncached.
2180 */
2181 void set_uncached_handler(unsigned long offset, void *addr,
2182 unsigned long size)
2183 {
2184 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
2185
2186 if (!addr)
2187 panic(panic_null_cerr);
2188
2189 memcpy((void *)(uncached_ebase + offset), addr, size);
2190 }
2191
2192 static int __initdata rdhwr_noopt;
2193 static int __init set_rdhwr_noopt(char *str)
2194 {
2195 rdhwr_noopt = 1;
2196 return 1;
2197 }
2198
2199 __setup("rdhwr_noopt", set_rdhwr_noopt);
2200
2201 void __init trap_init(void)
2202 {
2203 extern char except_vec3_generic;
2204 extern char except_vec4;
2205 extern char except_vec3_r4000;
2206 unsigned long i;
2207
2208 check_wait();
2209
2210 if (cpu_has_veic || cpu_has_vint) {
2211 unsigned long size = 0x200 + VECTORSPACING*64;
2212 ebase = (unsigned long)
2213 __alloc_bootmem(size, 1 << fls(size), 0);
2214 } else {
2215 ebase = CAC_BASE;
2216
2217 if (cpu_has_mips_r2_r6)
2218 ebase += (read_c0_ebase() & 0x3ffff000);
2219 }
2220
2221 if (cpu_has_mmips) {
2222 unsigned int config3 = read_c0_config3();
2223
2224 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
2225 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
2226 else
2227 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
2228 }
2229
2230 if (board_ebase_setup)
2231 board_ebase_setup();
2232 per_cpu_trap_init(true);
2233
2234 /*
2235 * Copy the generic exception handlers to their final destination.
2236 * This will be overridden later as suitable for a particular
2237 * configuration.
2238 */
2239 set_handler(0x180, &except_vec3_generic, 0x80);
2240
2241 /*
2242 * Setup default vectors
2243 */
2244 for (i = 0; i <= 31; i++)
2245 set_except_vector(i, handle_reserved);
2246
2247 /*
2248 * Copy the EJTAG debug exception vector handler code to it's final
2249 * destination.
2250 */
2251 if (cpu_has_ejtag && board_ejtag_handler_setup)
2252 board_ejtag_handler_setup();
2253
2254 /*
2255 * Only some CPUs have the watch exceptions.
2256 */
2257 if (cpu_has_watch)
2258 set_except_vector(EXCCODE_WATCH, handle_watch);
2259
2260 /*
2261 * Initialise interrupt handlers
2262 */
2263 if (cpu_has_veic || cpu_has_vint) {
2264 int nvec = cpu_has_veic ? 64 : 8;
2265 for (i = 0; i < nvec; i++)
2266 set_vi_handler(i, NULL);
2267 }
2268 else if (cpu_has_divec)
2269 set_handler(0x200, &except_vec4, 0x8);
2270
2271 /*
2272 * Some CPUs can enable/disable for cache parity detection, but does
2273 * it different ways.
2274 */
2275 parity_protection_init();
2276
2277 /*
2278 * The Data Bus Errors / Instruction Bus Errors are signaled
2279 * by external hardware. Therefore these two exceptions
2280 * may have board specific handlers.
2281 */
2282 if (board_be_init)
2283 board_be_init();
2284
2285 set_except_vector(EXCCODE_INT, using_rollback_handler() ?
2286 rollback_handle_int : handle_int);
2287 set_except_vector(EXCCODE_MOD, handle_tlbm);
2288 set_except_vector(EXCCODE_TLBL, handle_tlbl);
2289 set_except_vector(EXCCODE_TLBS, handle_tlbs);
2290
2291 set_except_vector(EXCCODE_ADEL, handle_adel);
2292 set_except_vector(EXCCODE_ADES, handle_ades);
2293
2294 set_except_vector(EXCCODE_IBE, handle_ibe);
2295 set_except_vector(EXCCODE_DBE, handle_dbe);
2296
2297 set_except_vector(EXCCODE_SYS, handle_sys);
2298 set_except_vector(EXCCODE_BP, handle_bp);
2299 set_except_vector(EXCCODE_RI, rdhwr_noopt ? handle_ri :
2300 (cpu_has_vtag_icache ?
2301 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
2302 set_except_vector(EXCCODE_CPU, handle_cpu);
2303 set_except_vector(EXCCODE_OV, handle_ov);
2304 set_except_vector(EXCCODE_TR, handle_tr);
2305 set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe);
2306
2307 if (current_cpu_type() == CPU_R6000 ||
2308 current_cpu_type() == CPU_R6000A) {
2309 /*
2310 * The R6000 is the only R-series CPU that features a machine
2311 * check exception (similar to the R4000 cache error) and
2312 * unaligned ldc1/sdc1 exception. The handlers have not been
2313 * written yet. Well, anyway there is no R6000 machine on the
2314 * current list of targets for Linux/MIPS.
2315 * (Duh, crap, there is someone with a triple R6k machine)
2316 */
2317 //set_except_vector(14, handle_mc);
2318 //set_except_vector(15, handle_ndc);
2319 }
2320
2321
2322 if (board_nmi_handler_setup)
2323 board_nmi_handler_setup();
2324
2325 if (cpu_has_fpu && !cpu_has_nofpuex)
2326 set_except_vector(EXCCODE_FPE, handle_fpe);
2327
2328 set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
2329
2330 if (cpu_has_rixiex) {
2331 set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);
2332 set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);
2333 }
2334
2335 set_except_vector(EXCCODE_MSADIS, handle_msa);
2336 set_except_vector(EXCCODE_MDMX, handle_mdmx);
2337
2338 if (cpu_has_mcheck)
2339 set_except_vector(EXCCODE_MCHECK, handle_mcheck);
2340
2341 if (cpu_has_mipsmt)
2342 set_except_vector(EXCCODE_THREAD, handle_mt);
2343
2344 set_except_vector(EXCCODE_DSPDIS, handle_dsp);
2345
2346 if (board_cache_error_setup)
2347 board_cache_error_setup();
2348
2349 if (cpu_has_vce)
2350 /* Special exception: R4[04]00 uses also the divec space. */
2351 set_handler(0x180, &except_vec3_r4000, 0x100);
2352 else if (cpu_has_4kex)
2353 set_handler(0x180, &except_vec3_generic, 0x80);
2354 else
2355 set_handler(0x080, &except_vec3_generic, 0x80);
2356
2357 local_flush_icache_range(ebase, ebase + 0x400);
2358
2359 sort_extable(__start___dbe_table, __stop___dbe_table);
2360
2361 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
2362 }
2363
2364 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
2365 void *v)
2366 {
2367 switch (cmd) {
2368 case CPU_PM_ENTER_FAILED:
2369 case CPU_PM_EXIT:
2370 configure_status();
2371 configure_hwrena();
2372 configure_exception_vector();
2373
2374 /* Restore register with CPU number for TLB handlers */
2375 TLBMISS_HANDLER_RESTORE();
2376
2377 break;
2378 }
2379
2380 return NOTIFY_OK;
2381 }
2382
2383 static struct notifier_block trap_pm_notifier_block = {
2384 .notifier_call = trap_pm_notifier,
2385 };
2386
2387 static int __init trap_pm_init(void)
2388 {
2389 return cpu_pm_register_notifier(&trap_pm_notifier_block);
2390 }
2391 arch_initcall(trap_pm_init);
CRIS linux kernel tree