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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[cris-mirror.git] / drivers / net / wireless / ath / ath9k / hw.c
blob14b13f07cd1fa87658f22f8352ff6bc32b3935ac
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <linux/time.h>
21 #include <linux/bitops.h>
22 #include <linux/etherdevice.h>
23 #include <linux/gpio.h>
24 #include <asm/unaligned.h>
25
26 #include "hw.h"
27 #include "hw-ops.h"
28 #include "ar9003_mac.h"
29 #include "ar9003_mci.h"
30 #include "ar9003_phy.h"
31 #include "ath9k.h"
32
33 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
34
35 MODULE_AUTHOR("Atheros Communications");
36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38 MODULE_LICENSE("Dual BSD/GPL");
39
40 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
41 {
42 struct ath_common *common = ath9k_hw_common(ah);
43 struct ath9k_channel *chan = ah->curchan;
44 unsigned int clockrate;
45
46 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
48 clockrate = 117;
49 else if (!chan) /* should really check for CCK instead */
50 clockrate = ATH9K_CLOCK_RATE_CCK;
51 else if (IS_CHAN_2GHZ(chan))
52 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
54 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
55 else
56 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
57
58 if (chan) {
59 if (IS_CHAN_HT40(chan))
60 clockrate *= 2;
61 if (IS_CHAN_HALF_RATE(chan))
62 clockrate /= 2;
63 if (IS_CHAN_QUARTER_RATE(chan))
64 clockrate /= 4;
65 }
66
67 common->clockrate = clockrate;
68 }
69
70 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
71 {
72 struct ath_common *common = ath9k_hw_common(ah);
73
74 return usecs * common->clockrate;
75 }
76
77 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
78 {
79 int i;
80
81 BUG_ON(timeout < AH_TIME_QUANTUM);
82
83 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
84 if ((REG_READ(ah, reg) & mask) == val)
85 return true;
86
87 udelay(AH_TIME_QUANTUM);
88 }
89
90 ath_dbg(ath9k_hw_common(ah), ANY,
91 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
92 timeout, reg, REG_READ(ah, reg), mask, val);
93
94 return false;
95 }
96 EXPORT_SYMBOL(ath9k_hw_wait);
97
98 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
99 int hw_delay)
100 {
101 hw_delay /= 10;
102
103 if (IS_CHAN_HALF_RATE(chan))
104 hw_delay *= 2;
105 else if (IS_CHAN_QUARTER_RATE(chan))
106 hw_delay *= 4;
107
108 udelay(hw_delay + BASE_ACTIVATE_DELAY);
109 }
110
111 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
112 int column, unsigned int *writecnt)
113 {
114 int r;
115
116 ENABLE_REGWRITE_BUFFER(ah);
117 for (r = 0; r < array->ia_rows; r++) {
118 REG_WRITE(ah, INI_RA(array, r, 0),
119 INI_RA(array, r, column));
120 DO_DELAY(*writecnt);
121 }
122 REGWRITE_BUFFER_FLUSH(ah);
123 }
124
125 void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size)
126 {
127 u32 *tmp_reg_list, *tmp_data;
128 int i;
129
130 tmp_reg_list = kmalloc(size * sizeof(u32), GFP_KERNEL);
131 if (!tmp_reg_list) {
132 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__);
133 return;
134 }
135
136 tmp_data = kmalloc(size * sizeof(u32), GFP_KERNEL);
137 if (!tmp_data) {
138 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__);
139 goto error_tmp_data;
140 }
141
142 for (i = 0; i < size; i++)
143 tmp_reg_list[i] = array[i][0];
144
145 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size);
146
147 for (i = 0; i < size; i++)
148 array[i][1] = tmp_data[i];
149
150 kfree(tmp_data);
151 error_tmp_data:
152 kfree(tmp_reg_list);
153 }
154
155 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
156 {
157 u32 retval;
158 int i;
159
160 for (i = 0, retval = 0; i < n; i++) {
161 retval = (retval << 1) | (val & 1);
162 val >>= 1;
163 }
164 return retval;
165 }
166
167 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
168 u8 phy, int kbps,
169 u32 frameLen, u16 rateix,
170 bool shortPreamble)
171 {
172 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
173
174 if (kbps == 0)
175 return 0;
176
177 switch (phy) {
178 case WLAN_RC_PHY_CCK:
179 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
180 if (shortPreamble)
181 phyTime >>= 1;
182 numBits = frameLen << 3;
183 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
184 break;
185 case WLAN_RC_PHY_OFDM:
186 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
188 numBits = OFDM_PLCP_BITS + (frameLen << 3);
189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
190 txTime = OFDM_SIFS_TIME_QUARTER
191 + OFDM_PREAMBLE_TIME_QUARTER
192 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
193 } else if (ah->curchan &&
194 IS_CHAN_HALF_RATE(ah->curchan)) {
195 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
196 numBits = OFDM_PLCP_BITS + (frameLen << 3);
197 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
198 txTime = OFDM_SIFS_TIME_HALF +
199 OFDM_PREAMBLE_TIME_HALF
200 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
201 } else {
202 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
203 numBits = OFDM_PLCP_BITS + (frameLen << 3);
204 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
205 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
206 + (numSymbols * OFDM_SYMBOL_TIME);
207 }
208 break;
209 default:
210 ath_err(ath9k_hw_common(ah),
211 "Unknown phy %u (rate ix %u)\n", phy, rateix);
212 txTime = 0;
213 break;
214 }
215
216 return txTime;
217 }
218 EXPORT_SYMBOL(ath9k_hw_computetxtime);
219
220 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
221 struct ath9k_channel *chan,
222 struct chan_centers *centers)
223 {
224 int8_t extoff;
225
226 if (!IS_CHAN_HT40(chan)) {
227 centers->ctl_center = centers->ext_center =
228 centers->synth_center = chan->channel;
229 return;
230 }
231
232 if (IS_CHAN_HT40PLUS(chan)) {
233 centers->synth_center =
234 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
235 extoff = 1;
236 } else {
237 centers->synth_center =
238 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
239 extoff = -1;
240 }
241
242 centers->ctl_center =
243 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
244 /* 25 MHz spacing is supported by hw but not on upper layers */
245 centers->ext_center =
246 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
247 }
248
249 /******************/
250 /* Chip Revisions */
251 /******************/
252
253 static void ath9k_hw_read_revisions(struct ath_hw *ah)
254 {
255 u32 val;
256
257 if (ah->get_mac_revision)
258 ah->hw_version.macRev = ah->get_mac_revision();
259
260 switch (ah->hw_version.devid) {
261 case AR5416_AR9100_DEVID:
262 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
263 break;
264 case AR9300_DEVID_AR9330:
265 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
266 if (!ah->get_mac_revision) {
267 val = REG_READ(ah, AR_SREV);
268 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
269 }
270 return;
271 case AR9300_DEVID_AR9340:
272 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
273 return;
274 case AR9300_DEVID_QCA955X:
275 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
276 return;
277 case AR9300_DEVID_AR953X:
278 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
279 return;
280 case AR9300_DEVID_QCA956X:
281 ah->hw_version.macVersion = AR_SREV_VERSION_9561;
282 return;
283 }
284
285 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
286
287 if (val == 0xFF) {
288 val = REG_READ(ah, AR_SREV);
289 ah->hw_version.macVersion =
290 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
291 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
292
293 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
294 ah->is_pciexpress = true;
295 else
296 ah->is_pciexpress = (val &
297 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
298 } else {
299 if (!AR_SREV_9100(ah))
300 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
301
302 ah->hw_version.macRev = val & AR_SREV_REVISION;
303
304 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
305 ah->is_pciexpress = true;
306 }
307 }
308
309 /************************************/
310 /* HW Attach, Detach, Init Routines */
311 /************************************/
312
313 static void ath9k_hw_disablepcie(struct ath_hw *ah)
314 {
315 if (!AR_SREV_5416(ah))
316 return;
317
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
322 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
323 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
324 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
325 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
326 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
327
328 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
329 }
330
331 /* This should work for all families including legacy */
332 static bool ath9k_hw_chip_test(struct ath_hw *ah)
333 {
334 struct ath_common *common = ath9k_hw_common(ah);
335 u32 regAddr[2] = { AR_STA_ID0 };
336 u32 regHold[2];
337 static const u32 patternData[4] = {
338 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
339 };
340 int i, j, loop_max;
341
342 if (!AR_SREV_9300_20_OR_LATER(ah)) {
343 loop_max = 2;
344 regAddr[1] = AR_PHY_BASE + (8 << 2);
345 } else
346 loop_max = 1;
347
348 for (i = 0; i < loop_max; i++) {
349 u32 addr = regAddr[i];
350 u32 wrData, rdData;
351
352 regHold[i] = REG_READ(ah, addr);
353 for (j = 0; j < 0x100; j++) {
354 wrData = (j << 16) | j;
355 REG_WRITE(ah, addr, wrData);
356 rdData = REG_READ(ah, addr);
357 if (rdData != wrData) {
358 ath_err(common,
359 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
360 addr, wrData, rdData);
361 return false;
362 }
363 }
364 for (j = 0; j < 4; j++) {
365 wrData = patternData[j];
366 REG_WRITE(ah, addr, wrData);
367 rdData = REG_READ(ah, addr);
368 if (wrData != rdData) {
369 ath_err(common,
370 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
371 addr, wrData, rdData);
372 return false;
373 }
374 }
375 REG_WRITE(ah, regAddr[i], regHold[i]);
376 }
377 udelay(100);
378
379 return true;
380 }
381
382 static void ath9k_hw_init_config(struct ath_hw *ah)
383 {
384 struct ath_common *common = ath9k_hw_common(ah);
385
386 ah->config.dma_beacon_response_time = 1;
387 ah->config.sw_beacon_response_time = 6;
388 ah->config.cwm_ignore_extcca = false;
389 ah->config.analog_shiftreg = 1;
390
391 ah->config.rx_intr_mitigation = true;
392
393 if (AR_SREV_9300_20_OR_LATER(ah)) {
394 ah->config.rimt_last = 500;
395 ah->config.rimt_first = 2000;
396 } else {
397 ah->config.rimt_last = 250;
398 ah->config.rimt_first = 700;
399 }
400
401 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
402 ah->config.pll_pwrsave = 7;
403
404 /*
405 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
406 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
407 * This means we use it for all AR5416 devices, and the few
408 * minor PCI AR9280 devices out there.
409 *
410 * Serialization is required because these devices do not handle
411 * well the case of two concurrent reads/writes due to the latency
412 * involved. During one read/write another read/write can be issued
413 * on another CPU while the previous read/write may still be working
414 * on our hardware, if we hit this case the hardware poops in a loop.
415 * We prevent this by serializing reads and writes.
416 *
417 * This issue is not present on PCI-Express devices or pre-AR5416
418 * devices (legacy, 802.11abg).
419 */
420 if (num_possible_cpus() > 1)
421 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
422
423 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
424 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
425 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
426 !ah->is_pciexpress)) {
427 ah->config.serialize_regmode = SER_REG_MODE_ON;
428 } else {
429 ah->config.serialize_regmode = SER_REG_MODE_OFF;
430 }
431 }
432
433 ath_dbg(common, RESET, "serialize_regmode is %d\n",
434 ah->config.serialize_regmode);
435
436 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
437 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
438 else
439 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
440 }
441
442 static void ath9k_hw_init_defaults(struct ath_hw *ah)
443 {
444 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
445
446 regulatory->country_code = CTRY_DEFAULT;
447 regulatory->power_limit = MAX_RATE_POWER;
448
449 ah->hw_version.magic = AR5416_MAGIC;
450 ah->hw_version.subvendorid = 0;
451
452 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
453 AR_STA_ID1_MCAST_KSRCH;
454 if (AR_SREV_9100(ah))
455 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
456
457 ah->slottime = 9;
458 ah->globaltxtimeout = (u32) -1;
459 ah->power_mode = ATH9K_PM_UNDEFINED;
460 ah->htc_reset_init = true;
461
462 ah->tpc_enabled = false;
463
464 ah->ani_function = ATH9K_ANI_ALL;
465 if (!AR_SREV_9300_20_OR_LATER(ah))
466 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
467
468 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
469 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
470 else
471 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
472 }
473
474 static void ath9k_hw_init_macaddr(struct ath_hw *ah)
475 {
476 struct ath_common *common = ath9k_hw_common(ah);
477 int i;
478 u16 eeval;
479 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
480
481 /* MAC address may already be loaded via ath9k_platform_data */
482 if (is_valid_ether_addr(common->macaddr))
483 return;
484
485 for (i = 0; i < 3; i++) {
486 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
487 common->macaddr[2 * i] = eeval >> 8;
488 common->macaddr[2 * i + 1] = eeval & 0xff;
489 }
490
491 if (is_valid_ether_addr(common->macaddr))
492 return;
493
494 ath_err(common, "eeprom contains invalid mac address: %pM\n",
495 common->macaddr);
496
497 random_ether_addr(common->macaddr);
498 ath_err(common, "random mac address will be used: %pM\n",
499 common->macaddr);
500
501 return;
502 }
503
504 static int ath9k_hw_post_init(struct ath_hw *ah)
505 {
506 struct ath_common *common = ath9k_hw_common(ah);
507 int ecode;
508
509 if (common->bus_ops->ath_bus_type != ATH_USB) {
510 if (!ath9k_hw_chip_test(ah))
511 return -ENODEV;
512 }
513
514 if (!AR_SREV_9300_20_OR_LATER(ah)) {
515 ecode = ar9002_hw_rf_claim(ah);
516 if (ecode != 0)
517 return ecode;
518 }
519
520 ecode = ath9k_hw_eeprom_init(ah);
521 if (ecode != 0)
522 return ecode;
523
524 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
525 ah->eep_ops->get_eeprom_ver(ah),
526 ah->eep_ops->get_eeprom_rev(ah));
527
528 ath9k_hw_ani_init(ah);
529
530 /*
531 * EEPROM needs to be initialized before we do this.
532 * This is required for regulatory compliance.
533 */
534 if (AR_SREV_9300_20_OR_LATER(ah)) {
535 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
536 if ((regdmn & 0xF0) == CTL_FCC) {
537 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
538 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
539 }
540 }
541
542 return 0;
543 }
544
545 static int ath9k_hw_attach_ops(struct ath_hw *ah)
546 {
547 if (!AR_SREV_9300_20_OR_LATER(ah))
548 return ar9002_hw_attach_ops(ah);
549
550 ar9003_hw_attach_ops(ah);
551 return 0;
552 }
553
554 /* Called for all hardware families */
555 static int __ath9k_hw_init(struct ath_hw *ah)
556 {
557 struct ath_common *common = ath9k_hw_common(ah);
558 int r = 0;
559
560 ath9k_hw_read_revisions(ah);
561
562 switch (ah->hw_version.macVersion) {
563 case AR_SREV_VERSION_5416_PCI:
564 case AR_SREV_VERSION_5416_PCIE:
565 case AR_SREV_VERSION_9160:
566 case AR_SREV_VERSION_9100:
567 case AR_SREV_VERSION_9280:
568 case AR_SREV_VERSION_9285:
569 case AR_SREV_VERSION_9287:
570 case AR_SREV_VERSION_9271:
571 case AR_SREV_VERSION_9300:
572 case AR_SREV_VERSION_9330:
573 case AR_SREV_VERSION_9485:
574 case AR_SREV_VERSION_9340:
575 case AR_SREV_VERSION_9462:
576 case AR_SREV_VERSION_9550:
577 case AR_SREV_VERSION_9565:
578 case AR_SREV_VERSION_9531:
579 case AR_SREV_VERSION_9561:
580 break;
581 default:
582 ath_err(common,
583 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
584 ah->hw_version.macVersion, ah->hw_version.macRev);
585 return -EOPNOTSUPP;
586 }
587
588 /*
589 * Read back AR_WA into a permanent copy and set bits 14 and 17.
590 * We need to do this to avoid RMW of this register. We cannot
591 * read the reg when chip is asleep.
592 */
593 if (AR_SREV_9300_20_OR_LATER(ah)) {
594 ah->WARegVal = REG_READ(ah, AR_WA);
595 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
596 AR_WA_ASPM_TIMER_BASED_DISABLE);
597 }
598
599 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
600 ath_err(common, "Couldn't reset chip\n");
601 return -EIO;
602 }
603
604 if (AR_SREV_9565(ah)) {
605 ah->WARegVal |= AR_WA_BIT22;
606 REG_WRITE(ah, AR_WA, ah->WARegVal);
607 }
608
609 ath9k_hw_init_defaults(ah);
610 ath9k_hw_init_config(ah);
611
612 r = ath9k_hw_attach_ops(ah);
613 if (r)
614 return r;
615
616 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
617 ath_err(common, "Couldn't wakeup chip\n");
618 return -EIO;
619 }
620
621 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
622 AR_SREV_9330(ah) || AR_SREV_9550(ah))
623 ah->is_pciexpress = false;
624
625 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
626 ath9k_hw_init_cal_settings(ah);
627
628 if (!ah->is_pciexpress)
629 ath9k_hw_disablepcie(ah);
630
631 r = ath9k_hw_post_init(ah);
632 if (r)
633 return r;
634
635 ath9k_hw_init_mode_gain_regs(ah);
636 r = ath9k_hw_fill_cap_info(ah);
637 if (r)
638 return r;
639
640 ath9k_hw_init_macaddr(ah);
641 ath9k_hw_init_hang_checks(ah);
642
643 common->state = ATH_HW_INITIALIZED;
644
645 return 0;
646 }
647
648 int ath9k_hw_init(struct ath_hw *ah)
649 {
650 int ret;
651 struct ath_common *common = ath9k_hw_common(ah);
652
653 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
654 switch (ah->hw_version.devid) {
655 case AR5416_DEVID_PCI:
656 case AR5416_DEVID_PCIE:
657 case AR5416_AR9100_DEVID:
658 case AR9160_DEVID_PCI:
659 case AR9280_DEVID_PCI:
660 case AR9280_DEVID_PCIE:
661 case AR9285_DEVID_PCIE:
662 case AR9287_DEVID_PCI:
663 case AR9287_DEVID_PCIE:
664 case AR2427_DEVID_PCIE:
665 case AR9300_DEVID_PCIE:
666 case AR9300_DEVID_AR9485_PCIE:
667 case AR9300_DEVID_AR9330:
668 case AR9300_DEVID_AR9340:
669 case AR9300_DEVID_QCA955X:
670 case AR9300_DEVID_AR9580:
671 case AR9300_DEVID_AR9462:
672 case AR9485_DEVID_AR1111:
673 case AR9300_DEVID_AR9565:
674 case AR9300_DEVID_AR953X:
675 case AR9300_DEVID_QCA956X:
676 break;
677 default:
678 if (common->bus_ops->ath_bus_type == ATH_USB)
679 break;
680 ath_err(common, "Hardware device ID 0x%04x not supported\n",
681 ah->hw_version.devid);
682 return -EOPNOTSUPP;
683 }
684
685 ret = __ath9k_hw_init(ah);
686 if (ret) {
687 ath_err(common,
688 "Unable to initialize hardware; initialization status: %d\n",
689 ret);
690 return ret;
691 }
692
693 ath_dynack_init(ah);
694
695 return 0;
696 }
697 EXPORT_SYMBOL(ath9k_hw_init);
698
699 static void ath9k_hw_init_qos(struct ath_hw *ah)
700 {
701 ENABLE_REGWRITE_BUFFER(ah);
702
703 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
704 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
705
706 REG_WRITE(ah, AR_QOS_NO_ACK,
707 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
708 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
709 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
710
711 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
712 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
713 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
714 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
715 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
716
717 REGWRITE_BUFFER_FLUSH(ah);
718 }
719
720 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
721 {
722 struct ath_common *common = ath9k_hw_common(ah);
723 int i = 0;
724
725 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
726 udelay(100);
727 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
728
729 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
730
731 udelay(100);
732
733 if (WARN_ON_ONCE(i >= 100)) {
734 ath_err(common, "PLL4 meaurement not done\n");
735 break;
736 }
737
738 i++;
739 }
740
741 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
742 }
743 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
744
745 static void ath9k_hw_init_pll(struct ath_hw *ah,
746 struct ath9k_channel *chan)
747 {
748 u32 pll;
749
750 pll = ath9k_hw_compute_pll_control(ah, chan);
751
752 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
753 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
754 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
755 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
756 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
757 AR_CH0_DPLL2_KD, 0x40);
758 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
759 AR_CH0_DPLL2_KI, 0x4);
760
761 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
762 AR_CH0_BB_DPLL1_REFDIV, 0x5);
763 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
764 AR_CH0_BB_DPLL1_NINI, 0x58);
765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
766 AR_CH0_BB_DPLL1_NFRAC, 0x0);
767
768 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
769 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
770 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
771 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
772 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
773 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
774
775 /* program BB PLL phase_shift to 0x6 */
776 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
777 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
778
779 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
780 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
781 udelay(1000);
782 } else if (AR_SREV_9330(ah)) {
783 u32 ddr_dpll2, pll_control2, kd;
784
785 if (ah->is_clk_25mhz) {
786 ddr_dpll2 = 0x18e82f01;
787 pll_control2 = 0xe04a3d;
788 kd = 0x1d;
789 } else {
790 ddr_dpll2 = 0x19e82f01;
791 pll_control2 = 0x886666;
792 kd = 0x3d;
793 }
794
795 /* program DDR PLL ki and kd value */
796 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
797
798 /* program DDR PLL phase_shift */
799 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
800 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
801
802 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
803 pll | AR_RTC_9300_PLL_BYPASS);
804 udelay(1000);
805
806 /* program refdiv, nint, frac to RTC register */
807 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
808
809 /* program BB PLL kd and ki value */
810 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
811 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
812
813 /* program BB PLL phase_shift */
814 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
815 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
816 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
817 AR_SREV_9561(ah)) {
818 u32 regval, pll2_divint, pll2_divfrac, refdiv;
819
820 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
821 pll | AR_RTC_9300_SOC_PLL_BYPASS);
822 udelay(1000);
823
824 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
825 udelay(100);
826
827 if (ah->is_clk_25mhz) {
828 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
829 pll2_divint = 0x1c;
830 pll2_divfrac = 0xa3d2;
831 refdiv = 1;
832 } else {
833 pll2_divint = 0x54;
834 pll2_divfrac = 0x1eb85;
835 refdiv = 3;
836 }
837 } else {
838 if (AR_SREV_9340(ah)) {
839 pll2_divint = 88;
840 pll2_divfrac = 0;
841 refdiv = 5;
842 } else {
843 pll2_divint = 0x11;
844 pll2_divfrac = (AR_SREV_9531(ah) ||
845 AR_SREV_9561(ah)) ?
846 0x26665 : 0x26666;
847 refdiv = 1;
848 }
849 }
850
851 regval = REG_READ(ah, AR_PHY_PLL_MODE);
852 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
853 regval |= (0x1 << 22);
854 else
855 regval |= (0x1 << 16);
856 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
857 udelay(100);
858
859 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
860 (pll2_divint << 18) | pll2_divfrac);
861 udelay(100);
862
863 regval = REG_READ(ah, AR_PHY_PLL_MODE);
864 if (AR_SREV_9340(ah))
865 regval = (regval & 0x80071fff) |
866 (0x1 << 30) |
867 (0x1 << 13) |
868 (0x4 << 26) |
869 (0x18 << 19);
870 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
871 regval = (regval & 0x01c00fff) |
872 (0x1 << 31) |
873 (0x2 << 29) |
874 (0xa << 25) |
875 (0x1 << 19);
876
877 if (AR_SREV_9531(ah))
878 regval |= (0x6 << 12);
879 } else
880 regval = (regval & 0x80071fff) |
881 (0x3 << 30) |
882 (0x1 << 13) |
883 (0x4 << 26) |
884 (0x60 << 19);
885 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
886
887 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
888 REG_WRITE(ah, AR_PHY_PLL_MODE,
889 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
890 else
891 REG_WRITE(ah, AR_PHY_PLL_MODE,
892 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
893
894 udelay(1000);
895 }
896
897 if (AR_SREV_9565(ah))
898 pll |= 0x40000;
899 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
900
901 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
902 AR_SREV_9550(ah))
903 udelay(1000);
904
905 /* Switch the core clock for ar9271 to 117Mhz */
906 if (AR_SREV_9271(ah)) {
907 udelay(500);
908 REG_WRITE(ah, 0x50040, 0x304);
909 }
910
911 udelay(RTC_PLL_SETTLE_DELAY);
912
913 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
914 }
915
916 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
917 enum nl80211_iftype opmode)
918 {
919 u32 sync_default = AR_INTR_SYNC_DEFAULT;
920 u32 imr_reg = AR_IMR_TXERR |
921 AR_IMR_TXURN |
922 AR_IMR_RXERR |
923 AR_IMR_RXORN |
924 AR_IMR_BCNMISC;
925
926 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
927 AR_SREV_9561(ah))
928 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
929
930 if (AR_SREV_9300_20_OR_LATER(ah)) {
931 imr_reg |= AR_IMR_RXOK_HP;
932 if (ah->config.rx_intr_mitigation)
933 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
934 else
935 imr_reg |= AR_IMR_RXOK_LP;
936
937 } else {
938 if (ah->config.rx_intr_mitigation)
939 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
940 else
941 imr_reg |= AR_IMR_RXOK;
942 }
943
944 if (ah->config.tx_intr_mitigation)
945 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
946 else
947 imr_reg |= AR_IMR_TXOK;
948
949 ENABLE_REGWRITE_BUFFER(ah);
950
951 REG_WRITE(ah, AR_IMR, imr_reg);
952 ah->imrs2_reg |= AR_IMR_S2_GTT;
953 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
954
955 if (!AR_SREV_9100(ah)) {
956 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
957 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
958 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
959 }
960
961 REGWRITE_BUFFER_FLUSH(ah);
962
963 if (AR_SREV_9300_20_OR_LATER(ah)) {
964 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
965 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
966 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
967 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
968 }
969 }
970
971 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
972 {
973 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
974 val = min(val, (u32) 0xFFFF);
975 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
976 }
977
978 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
979 {
980 u32 val = ath9k_hw_mac_to_clks(ah, us);
981 val = min(val, (u32) 0xFFFF);
982 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
983 }
984
985 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
986 {
987 u32 val = ath9k_hw_mac_to_clks(ah, us);
988 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
989 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
990 }
991
992 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
993 {
994 u32 val = ath9k_hw_mac_to_clks(ah, us);
995 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
996 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
997 }
998
999 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1000 {
1001 if (tu > 0xFFFF) {
1002 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1003 tu);
1004 ah->globaltxtimeout = (u32) -1;
1005 return false;
1006 } else {
1007 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1008 ah->globaltxtimeout = tu;
1009 return true;
1010 }
1011 }
1012
1013 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1014 {
1015 struct ath_common *common = ath9k_hw_common(ah);
1016 const struct ath9k_channel *chan = ah->curchan;
1017 int acktimeout, ctstimeout, ack_offset = 0;
1018 int slottime;
1019 int sifstime;
1020 int rx_lat = 0, tx_lat = 0, eifs = 0;
1021 u32 reg;
1022
1023 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
1024 ah->misc_mode);
1025
1026 if (!chan)
1027 return;
1028
1029 if (ah->misc_mode != 0)
1030 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
1031
1032 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1033 rx_lat = 41;
1034 else
1035 rx_lat = 37;
1036 tx_lat = 54;
1037
1038 if (IS_CHAN_5GHZ(chan))
1039 sifstime = 16;
1040 else
1041 sifstime = 10;
1042
1043 if (IS_CHAN_HALF_RATE(chan)) {
1044 eifs = 175;
1045 rx_lat *= 2;
1046 tx_lat *= 2;
1047 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1048 tx_lat += 11;
1049
1050 sifstime = 32;
1051 ack_offset = 16;
1052 slottime = 13;
1053 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1054 eifs = 340;
1055 rx_lat = (rx_lat * 4) - 1;
1056 tx_lat *= 4;
1057 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1058 tx_lat += 22;
1059
1060 sifstime = 64;
1061 ack_offset = 32;
1062 slottime = 21;
1063 } else {
1064 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1065 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1066 reg = AR_USEC_ASYNC_FIFO;
1067 } else {
1068 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1069 common->clockrate;
1070 reg = REG_READ(ah, AR_USEC);
1071 }
1072 rx_lat = MS(reg, AR_USEC_RX_LAT);
1073 tx_lat = MS(reg, AR_USEC_TX_LAT);
1074
1075 slottime = ah->slottime;
1076 }
1077
1078 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1079 slottime += 3 * ah->coverage_class;
1080 acktimeout = slottime + sifstime + ack_offset;
1081 ctstimeout = acktimeout;
1082
1083 /*
1084 * Workaround for early ACK timeouts, add an offset to match the
1085 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
1086 * This was initially only meant to work around an issue with delayed
1087 * BA frames in some implementations, but it has been found to fix ACK
1088 * timeout issues in other cases as well.
1089 */
1090 if (IS_CHAN_2GHZ(chan) &&
1091 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
1092 acktimeout += 64 - sifstime - ah->slottime;
1093 ctstimeout += 48 - sifstime - ah->slottime;
1094 }
1095
1096 if (ah->dynack.enabled) {
1097 acktimeout = ah->dynack.ackto;
1098 ctstimeout = acktimeout;
1099 slottime = (acktimeout - 3) / 2;
1100 } else {
1101 ah->dynack.ackto = acktimeout;
1102 }
1103
1104 ath9k_hw_set_sifs_time(ah, sifstime);
1105 ath9k_hw_setslottime(ah, slottime);
1106 ath9k_hw_set_ack_timeout(ah, acktimeout);
1107 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1108 if (ah->globaltxtimeout != (u32) -1)
1109 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1110
1111 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1112 REG_RMW(ah, AR_USEC,
1113 (common->clockrate - 1) |
1114 SM(rx_lat, AR_USEC_RX_LAT) |
1115 SM(tx_lat, AR_USEC_TX_LAT),
1116 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1117
1118 }
1119 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1120
1121 void ath9k_hw_deinit(struct ath_hw *ah)
1122 {
1123 struct ath_common *common = ath9k_hw_common(ah);
1124
1125 if (common->state < ATH_HW_INITIALIZED)
1126 return;
1127
1128 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1129 }
1130 EXPORT_SYMBOL(ath9k_hw_deinit);
1131
1132 /*******/
1133 /* INI */
1134 /*******/
1135
1136 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1137 {
1138 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1139
1140 if (IS_CHAN_2GHZ(chan))
1141 ctl |= CTL_11G;
1142 else
1143 ctl |= CTL_11A;
1144
1145 return ctl;
1146 }
1147
1148 /****************************************/
1149 /* Reset and Channel Switching Routines */
1150 /****************************************/
1151
1152 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1153 {
1154 struct ath_common *common = ath9k_hw_common(ah);
1155 int txbuf_size;
1156
1157 ENABLE_REGWRITE_BUFFER(ah);
1158
1159 /*
1160 * set AHB_MODE not to do cacheline prefetches
1161 */
1162 if (!AR_SREV_9300_20_OR_LATER(ah))
1163 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1164
1165 /*
1166 * let mac dma reads be in 128 byte chunks
1167 */
1168 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1169
1170 REGWRITE_BUFFER_FLUSH(ah);
1171
1172 /*
1173 * Restore TX Trigger Level to its pre-reset value.
1174 * The initial value depends on whether aggregation is enabled, and is
1175 * adjusted whenever underruns are detected.
1176 */
1177 if (!AR_SREV_9300_20_OR_LATER(ah))
1178 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1179
1180 ENABLE_REGWRITE_BUFFER(ah);
1181
1182 /*
1183 * let mac dma writes be in 128 byte chunks
1184 */
1185 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1186
1187 /*
1188 * Setup receive FIFO threshold to hold off TX activities
1189 */
1190 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1191
1192 if (AR_SREV_9300_20_OR_LATER(ah)) {
1193 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1194 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1195
1196 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1197 ah->caps.rx_status_len);
1198 }
1199
1200 /*
1201 * reduce the number of usable entries in PCU TXBUF to avoid
1202 * wrap around issues.
1203 */
1204 if (AR_SREV_9285(ah)) {
1205 /* For AR9285 the number of Fifos are reduced to half.
1206 * So set the usable tx buf size also to half to
1207 * avoid data/delimiter underruns
1208 */
1209 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1210 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1211 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1212 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1213 } else {
1214 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
1215 }
1216
1217 if (!AR_SREV_9271(ah))
1218 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1219
1220 REGWRITE_BUFFER_FLUSH(ah);
1221
1222 if (AR_SREV_9300_20_OR_LATER(ah))
1223 ath9k_hw_reset_txstatus_ring(ah);
1224 }
1225
1226 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1227 {
1228 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1229 u32 set = AR_STA_ID1_KSRCH_MODE;
1230
1231 ENABLE_REG_RMW_BUFFER(ah);
1232 switch (opmode) {
1233 case NL80211_IFTYPE_ADHOC:
1234 if (!AR_SREV_9340_13(ah)) {
1235 set |= AR_STA_ID1_ADHOC;
1236 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1237 break;
1238 }
1239 /* fall through */
1240 case NL80211_IFTYPE_OCB:
1241 case NL80211_IFTYPE_MESH_POINT:
1242 case NL80211_IFTYPE_AP:
1243 set |= AR_STA_ID1_STA_AP;
1244 /* fall through */
1245 case NL80211_IFTYPE_STATION:
1246 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1247 break;
1248 default:
1249 if (!ah->is_monitoring)
1250 set = 0;
1251 break;
1252 }
1253 REG_RMW(ah, AR_STA_ID1, set, mask);
1254 REG_RMW_BUFFER_FLUSH(ah);
1255 }
1256
1257 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1258 u32 *coef_mantissa, u32 *coef_exponent)
1259 {
1260 u32 coef_exp, coef_man;
1261
1262 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1263 if ((coef_scaled >> coef_exp) & 0x1)
1264 break;
1265
1266 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1267
1268 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1269
1270 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1271 *coef_exponent = coef_exp - 16;
1272 }
1273
1274 /* AR9330 WAR:
1275 * call external reset function to reset WMAC if:
1276 * - doing a cold reset
1277 * - we have pending frames in the TX queues.
1278 */
1279 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1280 {
1281 int i, npend = 0;
1282
1283 for (i = 0; i < AR_NUM_QCU; i++) {
1284 npend = ath9k_hw_numtxpending(ah, i);
1285 if (npend)
1286 break;
1287 }
1288
1289 if (ah->external_reset &&
1290 (npend || type == ATH9K_RESET_COLD)) {
1291 int reset_err = 0;
1292
1293 ath_dbg(ath9k_hw_common(ah), RESET,
1294 "reset MAC via external reset\n");
1295
1296 reset_err = ah->external_reset();
1297 if (reset_err) {
1298 ath_err(ath9k_hw_common(ah),
1299 "External reset failed, err=%d\n",
1300 reset_err);
1301 return false;
1302 }
1303
1304 REG_WRITE(ah, AR_RTC_RESET, 1);
1305 }
1306
1307 return true;
1308 }
1309
1310 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1311 {
1312 u32 rst_flags;
1313 u32 tmpReg;
1314
1315 if (AR_SREV_9100(ah)) {
1316 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1317 AR_RTC_DERIVED_CLK_PERIOD, 1);
1318 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1319 }
1320
1321 ENABLE_REGWRITE_BUFFER(ah);
1322
1323 if (AR_SREV_9300_20_OR_LATER(ah)) {
1324 REG_WRITE(ah, AR_WA, ah->WARegVal);
1325 udelay(10);
1326 }
1327
1328 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1329 AR_RTC_FORCE_WAKE_ON_INT);
1330
1331 if (AR_SREV_9100(ah)) {
1332 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1333 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1334 } else {
1335 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1336 if (AR_SREV_9340(ah))
1337 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1338 else
1339 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1340 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1341
1342 if (tmpReg) {
1343 u32 val;
1344 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1345
1346 val = AR_RC_HOSTIF;
1347 if (!AR_SREV_9300_20_OR_LATER(ah))
1348 val |= AR_RC_AHB;
1349 REG_WRITE(ah, AR_RC, val);
1350
1351 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1352 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1353
1354 rst_flags = AR_RTC_RC_MAC_WARM;
1355 if (type == ATH9K_RESET_COLD)
1356 rst_flags |= AR_RTC_RC_MAC_COLD;
1357 }
1358
1359 if (AR_SREV_9330(ah)) {
1360 if (!ath9k_hw_ar9330_reset_war(ah, type))
1361 return false;
1362 }
1363
1364 if (ath9k_hw_mci_is_enabled(ah))
1365 ar9003_mci_check_gpm_offset(ah);
1366
1367 /* DMA HALT added to resolve ar9300 and ar9580 bus error during
1368 * RTC_RC reg read
1369 */
1370 if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) {
1371 REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
1372 ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK,
1373 20 * AH_WAIT_TIMEOUT);
1374 REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
1375 }
1376
1377 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1378
1379 REGWRITE_BUFFER_FLUSH(ah);
1380
1381 if (AR_SREV_9300_20_OR_LATER(ah))
1382 udelay(50);
1383 else if (AR_SREV_9100(ah))
1384 mdelay(10);
1385 else
1386 udelay(100);
1387
1388 REG_WRITE(ah, AR_RTC_RC, 0);
1389 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1390 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
1391 return false;
1392 }
1393
1394 if (!AR_SREV_9100(ah))
1395 REG_WRITE(ah, AR_RC, 0);
1396
1397 if (AR_SREV_9100(ah))
1398 udelay(50);
1399
1400 return true;
1401 }
1402
1403 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1404 {
1405 ENABLE_REGWRITE_BUFFER(ah);
1406
1407 if (AR_SREV_9300_20_OR_LATER(ah)) {
1408 REG_WRITE(ah, AR_WA, ah->WARegVal);
1409 udelay(10);
1410 }
1411
1412 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1413 AR_RTC_FORCE_WAKE_ON_INT);
1414
1415 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1416 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1417
1418 REG_WRITE(ah, AR_RTC_RESET, 0);
1419
1420 REGWRITE_BUFFER_FLUSH(ah);
1421
1422 udelay(2);
1423
1424 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1425 REG_WRITE(ah, AR_RC, 0);
1426
1427 REG_WRITE(ah, AR_RTC_RESET, 1);
1428
1429 if (!ath9k_hw_wait(ah,
1430 AR_RTC_STATUS,
1431 AR_RTC_STATUS_M,
1432 AR_RTC_STATUS_ON,
1433 AH_WAIT_TIMEOUT)) {
1434 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
1435 return false;
1436 }
1437
1438 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1439 }
1440
1441 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1442 {
1443 bool ret = false;
1444
1445 if (AR_SREV_9300_20_OR_LATER(ah)) {
1446 REG_WRITE(ah, AR_WA, ah->WARegVal);
1447 udelay(10);
1448 }
1449
1450 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1451 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1452
1453 if (!ah->reset_power_on)
1454 type = ATH9K_RESET_POWER_ON;
1455
1456 switch (type) {
1457 case ATH9K_RESET_POWER_ON:
1458 ret = ath9k_hw_set_reset_power_on(ah);
1459 if (ret)
1460 ah->reset_power_on = true;
1461 break;
1462 case ATH9K_RESET_WARM:
1463 case ATH9K_RESET_COLD:
1464 ret = ath9k_hw_set_reset(ah, type);
1465 break;
1466 default:
1467 break;
1468 }
1469
1470 return ret;
1471 }
1472
1473 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1474 struct ath9k_channel *chan)
1475 {
1476 int reset_type = ATH9K_RESET_WARM;
1477
1478 if (AR_SREV_9280(ah)) {
1479 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1480 reset_type = ATH9K_RESET_POWER_ON;
1481 else
1482 reset_type = ATH9K_RESET_COLD;
1483 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1484 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1485 reset_type = ATH9K_RESET_COLD;
1486
1487 if (!ath9k_hw_set_reset_reg(ah, reset_type))
1488 return false;
1489
1490 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1491 return false;
1492
1493 ah->chip_fullsleep = false;
1494
1495 if (AR_SREV_9330(ah))
1496 ar9003_hw_internal_regulator_apply(ah);
1497 ath9k_hw_init_pll(ah, chan);
1498
1499 return true;
1500 }
1501
1502 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1503 struct ath9k_channel *chan)
1504 {
1505 struct ath_common *common = ath9k_hw_common(ah);
1506 struct ath9k_hw_capabilities *pCap = &ah->caps;
1507 bool band_switch = false, mode_diff = false;
1508 u8 ini_reloaded = 0;
1509 u32 qnum;
1510 int r;
1511
1512 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
1513 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1514 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1515 mode_diff = !!(flags_diff & ~CHANNEL_HT);
1516 }
1517
1518 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1519 if (ath9k_hw_numtxpending(ah, qnum)) {
1520 ath_dbg(common, QUEUE,
1521 "Transmit frames pending on queue %d\n", qnum);
1522 return false;
1523 }
1524 }
1525
1526 if (!ath9k_hw_rfbus_req(ah)) {
1527 ath_err(common, "Could not kill baseband RX\n");
1528 return false;
1529 }
1530
1531 if (band_switch || mode_diff) {
1532 ath9k_hw_mark_phy_inactive(ah);
1533 udelay(5);
1534
1535 if (band_switch)
1536 ath9k_hw_init_pll(ah, chan);
1537
1538 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1539 ath_err(common, "Failed to do fast channel change\n");
1540 return false;
1541 }
1542 }
1543
1544 ath9k_hw_set_channel_regs(ah, chan);
1545
1546 r = ath9k_hw_rf_set_freq(ah, chan);
1547 if (r) {
1548 ath_err(common, "Failed to set channel\n");
1549 return false;
1550 }
1551 ath9k_hw_set_clockrate(ah);
1552 ath9k_hw_apply_txpower(ah, chan, false);
1553
1554 ath9k_hw_set_delta_slope(ah, chan);
1555 ath9k_hw_spur_mitigate_freq(ah, chan);
1556
1557 if (band_switch || ini_reloaded)
1558 ah->eep_ops->set_board_values(ah, chan);
1559
1560 ath9k_hw_init_bb(ah, chan);
1561 ath9k_hw_rfbus_done(ah);
1562
1563 if (band_switch || ini_reloaded) {
1564 ah->ah_flags |= AH_FASTCC;
1565 ath9k_hw_init_cal(ah, chan);
1566 ah->ah_flags &= ~AH_FASTCC;
1567 }
1568
1569 return true;
1570 }
1571
1572 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1573 {
1574 u32 gpio_mask = ah->gpio_mask;
1575 int i;
1576
1577 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1578 if (!(gpio_mask & 1))
1579 continue;
1580
1581 ath9k_hw_gpio_request_out(ah, i, NULL,
1582 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1583 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1584 ath9k_hw_gpio_free(ah, i);
1585 }
1586 }
1587
1588 void ath9k_hw_check_nav(struct ath_hw *ah)
1589 {
1590 struct ath_common *common = ath9k_hw_common(ah);
1591 u32 val;
1592
1593 val = REG_READ(ah, AR_NAV);
1594 if (val != 0xdeadbeef && val > 0x7fff) {
1595 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1596 REG_WRITE(ah, AR_NAV, 0);
1597 }
1598 }
1599 EXPORT_SYMBOL(ath9k_hw_check_nav);
1600
1601 bool ath9k_hw_check_alive(struct ath_hw *ah)
1602 {
1603 int count = 50;
1604 u32 reg, last_val;
1605
1606 if (AR_SREV_9300(ah))
1607 return !ath9k_hw_detect_mac_hang(ah);
1608
1609 if (AR_SREV_9285_12_OR_LATER(ah))
1610 return true;
1611
1612 last_val = REG_READ(ah, AR_OBS_BUS_1);
1613 do {
1614 reg = REG_READ(ah, AR_OBS_BUS_1);
1615 if (reg != last_val)
1616 return true;
1617
1618 udelay(1);
1619 last_val = reg;
1620 if ((reg & 0x7E7FFFEF) == 0x00702400)
1621 continue;
1622
1623 switch (reg & 0x7E000B00) {
1624 case 0x1E000000:
1625 case 0x52000B00:
1626 case 0x18000B00:
1627 continue;
1628 default:
1629 return true;
1630 }
1631 } while (count-- > 0);
1632
1633 return false;
1634 }
1635 EXPORT_SYMBOL(ath9k_hw_check_alive);
1636
1637 static void ath9k_hw_init_mfp(struct ath_hw *ah)
1638 {
1639 /* Setup MFP options for CCMP */
1640 if (AR_SREV_9280_20_OR_LATER(ah)) {
1641 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1642 * frames when constructing CCMP AAD. */
1643 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1644 0xc7ff);
1645 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah))
1646 ah->sw_mgmt_crypto_tx = true;
1647 else
1648 ah->sw_mgmt_crypto_tx = false;
1649 ah->sw_mgmt_crypto_rx = false;
1650 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1651 /* Disable hardware crypto for management frames */
1652 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1653 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1654 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1655 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1656 ah->sw_mgmt_crypto_tx = true;
1657 ah->sw_mgmt_crypto_rx = true;
1658 } else {
1659 ah->sw_mgmt_crypto_tx = true;
1660 ah->sw_mgmt_crypto_rx = true;
1661 }
1662 }
1663
1664 static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1665 u32 macStaId1, u32 saveDefAntenna)
1666 {
1667 struct ath_common *common = ath9k_hw_common(ah);
1668
1669 ENABLE_REGWRITE_BUFFER(ah);
1670
1671 REG_RMW(ah, AR_STA_ID1, macStaId1
1672 | AR_STA_ID1_RTS_USE_DEF
1673 | ah->sta_id1_defaults,
1674 ~AR_STA_ID1_SADH_MASK);
1675 ath_hw_setbssidmask(common);
1676 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1677 ath9k_hw_write_associd(ah);
1678 REG_WRITE(ah, AR_ISR, ~0);
1679 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1680
1681 REGWRITE_BUFFER_FLUSH(ah);
1682
1683 ath9k_hw_set_operating_mode(ah, ah->opmode);
1684 }
1685
1686 static void ath9k_hw_init_queues(struct ath_hw *ah)
1687 {
1688 int i;
1689
1690 ENABLE_REGWRITE_BUFFER(ah);
1691
1692 for (i = 0; i < AR_NUM_DCU; i++)
1693 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1694
1695 REGWRITE_BUFFER_FLUSH(ah);
1696
1697 ah->intr_txqs = 0;
1698 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1699 ath9k_hw_resettxqueue(ah, i);
1700 }
1701
1702 /*
1703 * For big endian systems turn on swapping for descriptors
1704 */
1705 static void ath9k_hw_init_desc(struct ath_hw *ah)
1706 {
1707 struct ath_common *common = ath9k_hw_common(ah);
1708
1709 if (AR_SREV_9100(ah)) {
1710 u32 mask;
1711 mask = REG_READ(ah, AR_CFG);
1712 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1713 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1714 mask);
1715 } else {
1716 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1717 REG_WRITE(ah, AR_CFG, mask);
1718 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1719 REG_READ(ah, AR_CFG));
1720 }
1721 } else {
1722 if (common->bus_ops->ath_bus_type == ATH_USB) {
1723 /* Configure AR9271 target WLAN */
1724 if (AR_SREV_9271(ah))
1725 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1726 else
1727 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1728 }
1729 #ifdef __BIG_ENDIAN
1730 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1731 AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
1732 AR_SREV_9561(ah))
1733 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1734 else
1735 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1736 #endif
1737 }
1738 }
1739
1740 /*
1741 * Fast channel change:
1742 * (Change synthesizer based on channel freq without resetting chip)
1743 */
1744 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1745 {
1746 struct ath_common *common = ath9k_hw_common(ah);
1747 struct ath9k_hw_capabilities *pCap = &ah->caps;
1748 int ret;
1749
1750 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1751 goto fail;
1752
1753 if (ah->chip_fullsleep)
1754 goto fail;
1755
1756 if (!ah->curchan)
1757 goto fail;
1758
1759 if (chan->channel == ah->curchan->channel)
1760 goto fail;
1761
1762 if ((ah->curchan->channelFlags | chan->channelFlags) &
1763 (CHANNEL_HALF | CHANNEL_QUARTER))
1764 goto fail;
1765
1766 /*
1767 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
1768 */
1769 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
1770 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
1771 goto fail;
1772
1773 if (!ath9k_hw_check_alive(ah))
1774 goto fail;
1775
1776 /*
1777 * For AR9462, make sure that calibration data for
1778 * re-using are present.
1779 */
1780 if (AR_SREV_9462(ah) && (ah->caldata &&
1781 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1782 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1783 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
1784 goto fail;
1785
1786 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1787 ah->curchan->channel, chan->channel);
1788
1789 ret = ath9k_hw_channel_change(ah, chan);
1790 if (!ret)
1791 goto fail;
1792
1793 if (ath9k_hw_mci_is_enabled(ah))
1794 ar9003_mci_2g5g_switch(ah, false);
1795
1796 ath9k_hw_loadnf(ah, ah->curchan);
1797 ath9k_hw_start_nfcal(ah, true);
1798
1799 if (AR_SREV_9271(ah))
1800 ar9002_hw_load_ani_reg(ah, chan);
1801
1802 return 0;
1803 fail:
1804 return -EINVAL;
1805 }
1806
1807 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur)
1808 {
1809 struct timespec ts;
1810 s64 usec;
1811
1812 if (!cur) {
1813 getrawmonotonic(&ts);
1814 cur = &ts;
1815 }
1816
1817 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000;
1818 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000;
1819
1820 return (u32) usec;
1821 }
1822 EXPORT_SYMBOL(ath9k_hw_get_tsf_offset);
1823
1824 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1825 struct ath9k_hw_cal_data *caldata, bool fastcc)
1826 {
1827 struct ath_common *common = ath9k_hw_common(ah);
1828 u32 saveLedState;
1829 u32 saveDefAntenna;
1830 u32 macStaId1;
1831 struct timespec tsf_ts;
1832 u32 tsf_offset;
1833 u64 tsf = 0;
1834 int r;
1835 bool start_mci_reset = false;
1836 bool save_fullsleep = ah->chip_fullsleep;
1837
1838 if (ath9k_hw_mci_is_enabled(ah)) {
1839 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1840 if (start_mci_reset)
1841 return 0;
1842 }
1843
1844 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1845 return -EIO;
1846
1847 if (ah->curchan && !ah->chip_fullsleep)
1848 ath9k_hw_getnf(ah, ah->curchan);
1849
1850 ah->caldata = caldata;
1851 if (caldata && (chan->channel != caldata->channel ||
1852 chan->channelFlags != caldata->channelFlags)) {
1853 /* Operating channel changed, reset channel calibration data */
1854 memset(caldata, 0, sizeof(*caldata));
1855 ath9k_init_nfcal_hist_buffer(ah, chan);
1856 } else if (caldata) {
1857 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
1858 }
1859 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
1860
1861 if (fastcc) {
1862 r = ath9k_hw_do_fastcc(ah, chan);
1863 if (!r)
1864 return r;
1865 }
1866
1867 if (ath9k_hw_mci_is_enabled(ah))
1868 ar9003_mci_stop_bt(ah, save_fullsleep);
1869
1870 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1871 if (saveDefAntenna == 0)
1872 saveDefAntenna = 1;
1873
1874 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1875
1876 /* Save TSF before chip reset, a cold reset clears it */
1877 getrawmonotonic(&tsf_ts);
1878 tsf = ath9k_hw_gettsf64(ah);
1879
1880 saveLedState = REG_READ(ah, AR_CFG_LED) &
1881 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1882 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1883
1884 ath9k_hw_mark_phy_inactive(ah);
1885
1886 ah->paprd_table_write_done = false;
1887
1888 /* Only required on the first reset */
1889 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1890 REG_WRITE(ah,
1891 AR9271_RESET_POWER_DOWN_CONTROL,
1892 AR9271_RADIO_RF_RST);
1893 udelay(50);
1894 }
1895
1896 if (!ath9k_hw_chip_reset(ah, chan)) {
1897 ath_err(common, "Chip reset failed\n");
1898 return -EINVAL;
1899 }
1900
1901 /* Only required on the first reset */
1902 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1903 ah->htc_reset_init = false;
1904 REG_WRITE(ah,
1905 AR9271_RESET_POWER_DOWN_CONTROL,
1906 AR9271_GATE_MAC_CTL);
1907 udelay(50);
1908 }
1909
1910 /* Restore TSF */
1911 tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL);
1912 ath9k_hw_settsf64(ah, tsf + tsf_offset);
1913
1914 if (AR_SREV_9280_20_OR_LATER(ah))
1915 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1916
1917 if (!AR_SREV_9300_20_OR_LATER(ah))
1918 ar9002_hw_enable_async_fifo(ah);
1919
1920 r = ath9k_hw_process_ini(ah, chan);
1921 if (r)
1922 return r;
1923
1924 ath9k_hw_set_rfmode(ah, chan);
1925
1926 if (ath9k_hw_mci_is_enabled(ah))
1927 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1928
1929 /*
1930 * Some AR91xx SoC devices frequently fail to accept TSF writes
1931 * right after the chip reset. When that happens, write a new
1932 * value after the initvals have been applied.
1933 */
1934 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1935 tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL);
1936 ath9k_hw_settsf64(ah, tsf + tsf_offset);
1937 }
1938
1939 ath9k_hw_init_mfp(ah);
1940
1941 ath9k_hw_set_delta_slope(ah, chan);
1942 ath9k_hw_spur_mitigate_freq(ah, chan);
1943 ah->eep_ops->set_board_values(ah, chan);
1944
1945 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
1946
1947 r = ath9k_hw_rf_set_freq(ah, chan);
1948 if (r)
1949 return r;
1950
1951 ath9k_hw_set_clockrate(ah);
1952
1953 ath9k_hw_init_queues(ah);
1954 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1955 ath9k_hw_ani_cache_ini_regs(ah);
1956 ath9k_hw_init_qos(ah);
1957
1958 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1959 ath9k_hw_gpio_request_in(ah, ah->rfkill_gpio, "ath9k-rfkill");
1960
1961 ath9k_hw_init_global_settings(ah);
1962
1963 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1964 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1965 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1966 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1967 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1968 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1969 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1970 }
1971
1972 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1973
1974 ath9k_hw_set_dma(ah);
1975
1976 if (!ath9k_hw_mci_is_enabled(ah))
1977 REG_WRITE(ah, AR_OBS, 8);
1978
1979 ENABLE_REG_RMW_BUFFER(ah);
1980 if (ah->config.rx_intr_mitigation) {
1981 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
1982 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
1983 }
1984
1985 if (ah->config.tx_intr_mitigation) {
1986 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1987 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1988 }
1989 REG_RMW_BUFFER_FLUSH(ah);
1990
1991 ath9k_hw_init_bb(ah, chan);
1992
1993 if (caldata) {
1994 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
1995 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
1996 }
1997 if (!ath9k_hw_init_cal(ah, chan))
1998 return -EIO;
1999
2000 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
2001 return -EIO;
2002
2003 ENABLE_REGWRITE_BUFFER(ah);
2004
2005 ath9k_hw_restore_chainmask(ah);
2006 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2007
2008 REGWRITE_BUFFER_FLUSH(ah);
2009
2010 ath9k_hw_gen_timer_start_tsf2(ah);
2011
2012 ath9k_hw_init_desc(ah);
2013
2014 if (ath9k_hw_btcoex_is_enabled(ah))
2015 ath9k_hw_btcoex_enable(ah);
2016
2017 if (ath9k_hw_mci_is_enabled(ah))
2018 ar9003_mci_check_bt(ah);
2019
2020 if (AR_SREV_9300_20_OR_LATER(ah)) {
2021 ath9k_hw_loadnf(ah, chan);
2022 ath9k_hw_start_nfcal(ah, true);
2023 }
2024
2025 if (AR_SREV_9300_20_OR_LATER(ah))
2026 ar9003_hw_bb_watchdog_config(ah);
2027
2028 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
2029 ar9003_hw_disable_phy_restart(ah);
2030
2031 ath9k_hw_apply_gpio_override(ah);
2032
2033 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
2034 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2035
2036 if (ah->hw->conf.radar_enabled) {
2037 /* set HW specific DFS configuration */
2038 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan);
2039 ath9k_hw_set_radar_params(ah);
2040 }
2041
2042 return 0;
2043 }
2044 EXPORT_SYMBOL(ath9k_hw_reset);
2045
2046 /******************************/
2047 /* Power Management (Chipset) */
2048 /******************************/
2049
2050 /*
2051 * Notify Power Mgt is disabled in self-generated frames.
2052 * If requested, force chip to sleep.
2053 */
2054 static void ath9k_set_power_sleep(struct ath_hw *ah)
2055 {
2056 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2057
2058 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2059 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2060 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2061 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
2062 /* xxx Required for WLAN only case ? */
2063 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2064 udelay(100);
2065 }
2066
2067 /*
2068 * Clear the RTC force wake bit to allow the
2069 * mac to go to sleep.
2070 */
2071 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2072
2073 if (ath9k_hw_mci_is_enabled(ah))
2074 udelay(100);
2075
2076 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2077 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2078
2079 /* Shutdown chip. Active low */
2080 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2081 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2082 udelay(2);
2083 }
2084
2085 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
2086 if (AR_SREV_9300_20_OR_LATER(ah))
2087 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2088 }
2089
2090 /*
2091 * Notify Power Management is enabled in self-generating
2092 * frames. If request, set power mode of chip to
2093 * auto/normal. Duration in units of 128us (1/8 TU).
2094 */
2095 static void ath9k_set_power_network_sleep(struct ath_hw *ah)
2096 {
2097 struct ath9k_hw_capabilities *pCap = &ah->caps;
2098
2099 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2100
2101 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2102 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2103 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2104 AR_RTC_FORCE_WAKE_ON_INT);
2105 } else {
2106
2107 /* When chip goes into network sleep, it could be waken
2108 * up by MCI_INT interrupt caused by BT's HW messages
2109 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2110 * rate (~100us). This will cause chip to leave and
2111 * re-enter network sleep mode frequently, which in
2112 * consequence will have WLAN MCI HW to generate lots of
2113 * SYS_WAKING and SYS_SLEEPING messages which will make
2114 * BT CPU to busy to process.
2115 */
2116 if (ath9k_hw_mci_is_enabled(ah))
2117 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2118 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
2119 /*
2120 * Clear the RTC force wake bit to allow the
2121 * mac to go to sleep.
2122 */
2123 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2124
2125 if (ath9k_hw_mci_is_enabled(ah))
2126 udelay(30);
2127 }
2128
2129 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2130 if (AR_SREV_9300_20_OR_LATER(ah))
2131 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2132 }
2133
2134 static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
2135 {
2136 u32 val;
2137 int i;
2138
2139 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2140 if (AR_SREV_9300_20_OR_LATER(ah)) {
2141 REG_WRITE(ah, AR_WA, ah->WARegVal);
2142 udelay(10);
2143 }
2144
2145 if ((REG_READ(ah, AR_RTC_STATUS) &
2146 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2147 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2148 return false;
2149 }
2150 if (!AR_SREV_9300_20_OR_LATER(ah))
2151 ath9k_hw_init_pll(ah, NULL);
2152 }
2153 if (AR_SREV_9100(ah))
2154 REG_SET_BIT(ah, AR_RTC_RESET,
2155 AR_RTC_RESET_EN);
2156
2157 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2158 AR_RTC_FORCE_WAKE_EN);
2159 if (AR_SREV_9100(ah))
2160 mdelay(10);
2161 else
2162 udelay(50);
2163
2164 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2165 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2166 if (val == AR_RTC_STATUS_ON)
2167 break;
2168 udelay(50);
2169 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2170 AR_RTC_FORCE_WAKE_EN);
2171 }
2172 if (i == 0) {
2173 ath_err(ath9k_hw_common(ah),
2174 "Failed to wakeup in %uus\n",
2175 POWER_UP_TIME / 20);
2176 return false;
2177 }
2178
2179 if (ath9k_hw_mci_is_enabled(ah))
2180 ar9003_mci_set_power_awake(ah);
2181
2182 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2183
2184 return true;
2185 }
2186
2187 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2188 {
2189 struct ath_common *common = ath9k_hw_common(ah);
2190 int status = true;
2191 static const char *modes[] = {
2192 "AWAKE",
2193 "FULL-SLEEP",
2194 "NETWORK SLEEP",
2195 "UNDEFINED"
2196 };
2197
2198 if (ah->power_mode == mode)
2199 return status;
2200
2201 ath_dbg(common, RESET, "%s -> %s\n",
2202 modes[ah->power_mode], modes[mode]);
2203
2204 switch (mode) {
2205 case ATH9K_PM_AWAKE:
2206 status = ath9k_hw_set_power_awake(ah);
2207 break;
2208 case ATH9K_PM_FULL_SLEEP:
2209 if (ath9k_hw_mci_is_enabled(ah))
2210 ar9003_mci_set_full_sleep(ah);
2211
2212 ath9k_set_power_sleep(ah);
2213 ah->chip_fullsleep = true;
2214 break;
2215 case ATH9K_PM_NETWORK_SLEEP:
2216 ath9k_set_power_network_sleep(ah);
2217 break;
2218 default:
2219 ath_err(common, "Unknown power mode %u\n", mode);
2220 return false;
2221 }
2222 ah->power_mode = mode;
2223
2224 /*
2225 * XXX: If this warning never comes up after a while then
2226 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2227 * ath9k_hw_setpower() return type void.
2228 */
2229
2230 if (!(ah->ah_flags & AH_UNPLUGGED))
2231 ATH_DBG_WARN_ON_ONCE(!status);
2232
2233 return status;
2234 }
2235 EXPORT_SYMBOL(ath9k_hw_setpower);
2236
2237 /*******************/
2238 /* Beacon Handling */
2239 /*******************/
2240
2241 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2242 {
2243 int flags = 0;
2244
2245 ENABLE_REGWRITE_BUFFER(ah);
2246
2247 switch (ah->opmode) {
2248 case NL80211_IFTYPE_ADHOC:
2249 REG_SET_BIT(ah, AR_TXCFG,
2250 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2251 case NL80211_IFTYPE_MESH_POINT:
2252 case NL80211_IFTYPE_AP:
2253 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2254 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2255 TU_TO_USEC(ah->config.dma_beacon_response_time));
2256 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2257 TU_TO_USEC(ah->config.sw_beacon_response_time));
2258 flags |=
2259 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2260 break;
2261 default:
2262 ath_dbg(ath9k_hw_common(ah), BEACON,
2263 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
2264 return;
2265 break;
2266 }
2267
2268 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2269 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2270 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2271
2272 REGWRITE_BUFFER_FLUSH(ah);
2273
2274 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2275 }
2276 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2277
2278 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2279 const struct ath9k_beacon_state *bs)
2280 {
2281 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2282 struct ath9k_hw_capabilities *pCap = &ah->caps;
2283 struct ath_common *common = ath9k_hw_common(ah);
2284
2285 ENABLE_REGWRITE_BUFFER(ah);
2286
2287 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2288 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2289 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
2290
2291 REGWRITE_BUFFER_FLUSH(ah);
2292
2293 REG_RMW_FIELD(ah, AR_RSSI_THR,
2294 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2295
2296 beaconintval = bs->bs_intval;
2297
2298 if (bs->bs_sleepduration > beaconintval)
2299 beaconintval = bs->bs_sleepduration;
2300
2301 dtimperiod = bs->bs_dtimperiod;
2302 if (bs->bs_sleepduration > dtimperiod)
2303 dtimperiod = bs->bs_sleepduration;
2304
2305 if (beaconintval == dtimperiod)
2306 nextTbtt = bs->bs_nextdtim;
2307 else
2308 nextTbtt = bs->bs_nexttbtt;
2309
2310 ath_dbg(common, BEACON, "next DTIM %u\n", bs->bs_nextdtim);
2311 ath_dbg(common, BEACON, "next beacon %u\n", nextTbtt);
2312 ath_dbg(common, BEACON, "beacon period %u\n", beaconintval);
2313 ath_dbg(common, BEACON, "DTIM period %u\n", dtimperiod);
2314
2315 ENABLE_REGWRITE_BUFFER(ah);
2316
2317 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2318 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
2319
2320 REG_WRITE(ah, AR_SLEEP1,
2321 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2322 | AR_SLEEP1_ASSUME_DTIM);
2323
2324 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2325 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2326 else
2327 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2328
2329 REG_WRITE(ah, AR_SLEEP2,
2330 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2331
2332 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2333 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
2334
2335 REGWRITE_BUFFER_FLUSH(ah);
2336
2337 REG_SET_BIT(ah, AR_TIMER_MODE,
2338 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2339 AR_DTIM_TIMER_EN);
2340
2341 /* TSF Out of Range Threshold */
2342 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2343 }
2344 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2345
2346 /*******************/
2347 /* HW Capabilities */
2348 /*******************/
2349
2350 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2351 {
2352 eeprom_chainmask &= chip_chainmask;
2353 if (eeprom_chainmask)
2354 return eeprom_chainmask;
2355 else
2356 return chip_chainmask;
2357 }
2358
2359 /**
2360 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2361 * @ah: the atheros hardware data structure
2362 *
2363 * We enable DFS support upstream on chipsets which have passed a series
2364 * of tests. The testing requirements are going to be documented. Desired
2365 * test requirements are documented at:
2366 *
2367 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2368 *
2369 * Once a new chipset gets properly tested an individual commit can be used
2370 * to document the testing for DFS for that chipset.
2371 */
2372 static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2373 {
2374
2375 switch (ah->hw_version.macVersion) {
2376 /* for temporary testing DFS with 9280 */
2377 case AR_SREV_VERSION_9280:
2378 /* AR9580 will likely be our first target to get testing on */
2379 case AR_SREV_VERSION_9580:
2380 return true;
2381 default:
2382 return false;
2383 }
2384 }
2385
2386 static void ath9k_gpio_cap_init(struct ath_hw *ah)
2387 {
2388 struct ath9k_hw_capabilities *pCap = &ah->caps;
2389
2390 if (AR_SREV_9271(ah)) {
2391 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2392 pCap->gpio_mask = AR9271_GPIO_MASK;
2393 } else if (AR_DEVID_7010(ah)) {
2394 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2395 pCap->gpio_mask = AR7010_GPIO_MASK;
2396 } else if (AR_SREV_9287(ah)) {
2397 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2398 pCap->gpio_mask = AR9287_GPIO_MASK;
2399 } else if (AR_SREV_9285(ah)) {
2400 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2401 pCap->gpio_mask = AR9285_GPIO_MASK;
2402 } else if (AR_SREV_9280(ah)) {
2403 pCap->num_gpio_pins = AR9280_NUM_GPIO;
2404 pCap->gpio_mask = AR9280_GPIO_MASK;
2405 } else if (AR_SREV_9300(ah)) {
2406 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2407 pCap->gpio_mask = AR9300_GPIO_MASK;
2408 } else if (AR_SREV_9330(ah)) {
2409 pCap->num_gpio_pins = AR9330_NUM_GPIO;
2410 pCap->gpio_mask = AR9330_GPIO_MASK;
2411 } else if (AR_SREV_9340(ah)) {
2412 pCap->num_gpio_pins = AR9340_NUM_GPIO;
2413 pCap->gpio_mask = AR9340_GPIO_MASK;
2414 } else if (AR_SREV_9462(ah)) {
2415 pCap->num_gpio_pins = AR9462_NUM_GPIO;
2416 pCap->gpio_mask = AR9462_GPIO_MASK;
2417 } else if (AR_SREV_9485(ah)) {
2418 pCap->num_gpio_pins = AR9485_NUM_GPIO;
2419 pCap->gpio_mask = AR9485_GPIO_MASK;
2420 } else if (AR_SREV_9531(ah)) {
2421 pCap->num_gpio_pins = AR9531_NUM_GPIO;
2422 pCap->gpio_mask = AR9531_GPIO_MASK;
2423 } else if (AR_SREV_9550(ah)) {
2424 pCap->num_gpio_pins = AR9550_NUM_GPIO;
2425 pCap->gpio_mask = AR9550_GPIO_MASK;
2426 } else if (AR_SREV_9561(ah)) {
2427 pCap->num_gpio_pins = AR9561_NUM_GPIO;
2428 pCap->gpio_mask = AR9561_GPIO_MASK;
2429 } else if (AR_SREV_9565(ah)) {
2430 pCap->num_gpio_pins = AR9565_NUM_GPIO;
2431 pCap->gpio_mask = AR9565_GPIO_MASK;
2432 } else if (AR_SREV_9580(ah)) {
2433 pCap->num_gpio_pins = AR9580_NUM_GPIO;
2434 pCap->gpio_mask = AR9580_GPIO_MASK;
2435 } else {
2436 pCap->num_gpio_pins = AR_NUM_GPIO;
2437 pCap->gpio_mask = AR_GPIO_MASK;
2438 }
2439 }
2440
2441 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2442 {
2443 struct ath9k_hw_capabilities *pCap = &ah->caps;
2444 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2445 struct ath_common *common = ath9k_hw_common(ah);
2446
2447 u16 eeval;
2448 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2449
2450 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2451 regulatory->current_rd = eeval;
2452
2453 if (ah->opmode != NL80211_IFTYPE_AP &&
2454 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2455 if (regulatory->current_rd == 0x64 ||
2456 regulatory->current_rd == 0x65)
2457 regulatory->current_rd += 5;
2458 else if (regulatory->current_rd == 0x41)
2459 regulatory->current_rd = 0x43;
2460 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2461 regulatory->current_rd);
2462 }
2463
2464 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2465
2466 if (eeval & AR5416_OPFLAGS_11A) {
2467 if (ah->disable_5ghz)
2468 ath_warn(common, "disabling 5GHz band\n");
2469 else
2470 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2471 }
2472
2473 if (eeval & AR5416_OPFLAGS_11G) {
2474 if (ah->disable_2ghz)
2475 ath_warn(common, "disabling 2GHz band\n");
2476 else
2477 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2478 }
2479
2480 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) {
2481 ath_err(common, "both bands are disabled\n");
2482 return -EINVAL;
2483 }
2484
2485 ath9k_gpio_cap_init(ah);
2486
2487 if (AR_SREV_9485(ah) ||
2488 AR_SREV_9285(ah) ||
2489 AR_SREV_9330(ah) ||
2490 AR_SREV_9565(ah))
2491 pCap->chip_chainmask = 1;
2492 else if (!AR_SREV_9280_20_OR_LATER(ah))
2493 pCap->chip_chainmask = 7;
2494 else if (!AR_SREV_9300_20_OR_LATER(ah) ||
2495 AR_SREV_9340(ah) ||
2496 AR_SREV_9462(ah) ||
2497 AR_SREV_9531(ah))
2498 pCap->chip_chainmask = 3;
2499 else
2500 pCap->chip_chainmask = 7;
2501
2502 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2503 /*
2504 * For AR9271 we will temporarilly uses the rx chainmax as read from
2505 * the EEPROM.
2506 */
2507 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2508 !(eeval & AR5416_OPFLAGS_11A) &&
2509 !(AR_SREV_9271(ah)))
2510 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2511 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2512 else if (AR_SREV_9100(ah))
2513 pCap->rx_chainmask = 0x7;
2514 else
2515 /* Use rx_chainmask from EEPROM. */
2516 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2517
2518 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask);
2519 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask);
2520 ah->txchainmask = pCap->tx_chainmask;
2521 ah->rxchainmask = pCap->rx_chainmask;
2522
2523 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2524
2525 /* enable key search for every frame in an aggregate */
2526 if (AR_SREV_9300_20_OR_LATER(ah))
2527 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2528
2529 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2530
2531 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2532 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2533 else
2534 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2535
2536 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
2537 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2538 else
2539 pCap->rts_aggr_limit = (8 * 1024);
2540
2541 #ifdef CONFIG_ATH9K_RFKILL
2542 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2543 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2544 ah->rfkill_gpio =
2545 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2546 ah->rfkill_polarity =
2547 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2548
2549 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2550 }
2551 #endif
2552 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2553 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2554 else
2555 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2556
2557 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2558 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2559 else
2560 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2561
2562 if (AR_SREV_9300_20_OR_LATER(ah)) {
2563 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2564 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) &&
2565 !AR_SREV_9561(ah) && !AR_SREV_9565(ah))
2566 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2567
2568 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2569 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2570 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2571 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2572 pCap->txs_len = sizeof(struct ar9003_txs);
2573 } else {
2574 pCap->tx_desc_len = sizeof(struct ath_desc);
2575 if (AR_SREV_9280_20(ah))
2576 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2577 }
2578
2579 if (AR_SREV_9300_20_OR_LATER(ah))
2580 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2581
2582 if (AR_SREV_9561(ah))
2583 ah->ent_mode = 0x3BDA000;
2584 else if (AR_SREV_9300_20_OR_LATER(ah))
2585 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2586
2587 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2588 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2589
2590 if (AR_SREV_9285(ah)) {
2591 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2592 ant_div_ctl1 =
2593 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2594 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
2595 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2596 ath_info(common, "Enable LNA combining\n");
2597 }
2598 }
2599 }
2600
2601 if (AR_SREV_9300_20_OR_LATER(ah)) {
2602 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2603 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2604 }
2605
2606 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
2607 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2608 if ((ant_div_ctl1 >> 0x6) == 0x3) {
2609 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2610 ath_info(common, "Enable LNA combining\n");
2611 }
2612 }
2613
2614 if (ath9k_hw_dfs_tested(ah))
2615 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2616
2617 tx_chainmask = pCap->tx_chainmask;
2618 rx_chainmask = pCap->rx_chainmask;
2619 while (tx_chainmask || rx_chainmask) {
2620 if (tx_chainmask & BIT(0))
2621 pCap->max_txchains++;
2622 if (rx_chainmask & BIT(0))
2623 pCap->max_rxchains++;
2624
2625 tx_chainmask >>= 1;
2626 rx_chainmask >>= 1;
2627 }
2628
2629 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2630 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2631 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2632
2633 if (AR_SREV_9462_20_OR_LATER(ah))
2634 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2635 }
2636
2637 if (AR_SREV_9300_20_OR_LATER(ah) &&
2638 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2639 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2640
2641 #ifdef CONFIG_ATH9K_WOW
2642 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah))
2643 ah->wow.max_patterns = MAX_NUM_PATTERN;
2644 else
2645 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY;
2646 #endif
2647
2648 return 0;
2649 }
2650
2651 /****************************/
2652 /* GPIO / RFKILL / Antennae */
2653 /****************************/
2654
2655 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type)
2656 {
2657 int addr;
2658 u32 gpio_shift, tmp;
2659
2660 if (gpio > 11)
2661 addr = AR_GPIO_OUTPUT_MUX3;
2662 else if (gpio > 5)
2663 addr = AR_GPIO_OUTPUT_MUX2;
2664 else
2665 addr = AR_GPIO_OUTPUT_MUX1;
2666
2667 gpio_shift = (gpio % 6) * 5;
2668
2669 if (AR_SREV_9280_20_OR_LATER(ah) ||
2670 (addr != AR_GPIO_OUTPUT_MUX1)) {
2671 REG_RMW(ah, addr, (type << gpio_shift),
2672 (0x1f << gpio_shift));
2673 } else {
2674 tmp = REG_READ(ah, addr);
2675 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2676 tmp &= ~(0x1f << gpio_shift);
2677 tmp |= (type << gpio_shift);
2678 REG_WRITE(ah, addr, tmp);
2679 }
2680 }
2681
2682 /* BSP should set the corresponding MUX register correctly.
2683 */
2684 static void ath9k_hw_gpio_cfg_soc(struct ath_hw *ah, u32 gpio, bool out,
2685 const char *label)
2686 {
2687 if (ah->caps.gpio_requested & BIT(gpio))
2688 return;
2689
2690 /* may be requested by BSP, free anyway */
2691 gpio_free(gpio);
2692
2693 if (gpio_request_one(gpio, out ? GPIOF_OUT_INIT_LOW : GPIOF_IN, label))
2694 return;
2695
2696 ah->caps.gpio_requested |= BIT(gpio);
2697 }
2698
2699 static void ath9k_hw_gpio_cfg_wmac(struct ath_hw *ah, u32 gpio, bool out,
2700 u32 ah_signal_type)
2701 {
2702 u32 gpio_set, gpio_shift = gpio;
2703
2704 if (AR_DEVID_7010(ah)) {
2705 gpio_set = out ?
2706 AR7010_GPIO_OE_AS_OUTPUT : AR7010_GPIO_OE_AS_INPUT;
2707 REG_RMW(ah, AR7010_GPIO_OE, gpio_set << gpio_shift,
2708 AR7010_GPIO_OE_MASK << gpio_shift);
2709 } else if (AR_SREV_SOC(ah)) {
2710 gpio_set = out ? 1 : 0;
2711 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift,
2712 gpio_set << gpio_shift);
2713 } else {
2714 gpio_shift = gpio << 1;
2715 gpio_set = out ?
2716 AR_GPIO_OE_OUT_DRV_ALL : AR_GPIO_OE_OUT_DRV_NO;
2717 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift,
2718 AR_GPIO_OE_OUT_DRV << gpio_shift);
2719
2720 if (out)
2721 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2722 }
2723 }
2724
2725 static void ath9k_hw_gpio_request(struct ath_hw *ah, u32 gpio, bool out,
2726 const char *label, u32 ah_signal_type)
2727 {
2728 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2729
2730 if (BIT(gpio) & ah->caps.gpio_mask)
2731 ath9k_hw_gpio_cfg_wmac(ah, gpio, out, ah_signal_type);
2732 else if (AR_SREV_SOC(ah))
2733 ath9k_hw_gpio_cfg_soc(ah, gpio, out, label);
2734 else
2735 WARN_ON(1);
2736 }
2737
2738 void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label)
2739 {
2740 ath9k_hw_gpio_request(ah, gpio, false, label, 0);
2741 }
2742 EXPORT_SYMBOL(ath9k_hw_gpio_request_in);
2743
2744 void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label,
2745 u32 ah_signal_type)
2746 {
2747 ath9k_hw_gpio_request(ah, gpio, true, label, ah_signal_type);
2748 }
2749 EXPORT_SYMBOL(ath9k_hw_gpio_request_out);
2750
2751 void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio)
2752 {
2753 if (!AR_SREV_SOC(ah))
2754 return;
2755
2756 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2757
2758 if (ah->caps.gpio_requested & BIT(gpio)) {
2759 gpio_free(gpio);
2760 ah->caps.gpio_requested &= ~BIT(gpio);
2761 }
2762 }
2763 EXPORT_SYMBOL(ath9k_hw_gpio_free);
2764
2765 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2766 {
2767 u32 val = 0xffffffff;
2768
2769 #define MS_REG_READ(x, y) \
2770 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & BIT(y))
2771
2772 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2773
2774 if (BIT(gpio) & ah->caps.gpio_mask) {
2775 if (AR_SREV_9271(ah))
2776 val = MS_REG_READ(AR9271, gpio);
2777 else if (AR_SREV_9287(ah))
2778 val = MS_REG_READ(AR9287, gpio);
2779 else if (AR_SREV_9285(ah))
2780 val = MS_REG_READ(AR9285, gpio);
2781 else if (AR_SREV_9280(ah))
2782 val = MS_REG_READ(AR928X, gpio);
2783 else if (AR_DEVID_7010(ah))
2784 val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio);
2785 else if (AR_SREV_9300_20_OR_LATER(ah))
2786 val = REG_READ(ah, AR_GPIO_IN) & BIT(gpio);
2787 else
2788 val = MS_REG_READ(AR, gpio);
2789 } else if (BIT(gpio) & ah->caps.gpio_requested) {
2790 val = gpio_get_value(gpio) & BIT(gpio);
2791 } else {
2792 WARN_ON(1);
2793 }
2794
2795 return val;
2796 }
2797 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2798
2799 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2800 {
2801 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2802
2803 if (AR_DEVID_7010(ah) || AR_SREV_9271(ah))
2804 val = !val;
2805 else
2806 val = !!val;
2807
2808 if (BIT(gpio) & ah->caps.gpio_mask) {
2809 u32 out_addr = AR_DEVID_7010(ah) ?
2810 AR7010_GPIO_OUT : AR_GPIO_IN_OUT;
2811
2812 REG_RMW(ah, out_addr, val << gpio, BIT(gpio));
2813 } else if (BIT(gpio) & ah->caps.gpio_requested) {
2814 gpio_set_value(gpio, val);
2815 } else {
2816 WARN_ON(1);
2817 }
2818 }
2819 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2820
2821 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2822 {
2823 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2824 }
2825 EXPORT_SYMBOL(ath9k_hw_setantenna);
2826
2827 /*********************/
2828 /* General Operation */
2829 /*********************/
2830
2831 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2832 {
2833 u32 bits = REG_READ(ah, AR_RX_FILTER);
2834 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2835
2836 if (phybits & AR_PHY_ERR_RADAR)
2837 bits |= ATH9K_RX_FILTER_PHYRADAR;
2838 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2839 bits |= ATH9K_RX_FILTER_PHYERR;
2840
2841 return bits;
2842 }
2843 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2844
2845 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2846 {
2847 u32 phybits;
2848
2849 ENABLE_REGWRITE_BUFFER(ah);
2850
2851 REG_WRITE(ah, AR_RX_FILTER, bits);
2852
2853 phybits = 0;
2854 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2855 phybits |= AR_PHY_ERR_RADAR;
2856 if (bits & ATH9K_RX_FILTER_PHYERR)
2857 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2858 REG_WRITE(ah, AR_PHY_ERR, phybits);
2859
2860 if (phybits)
2861 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2862 else
2863 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2864
2865 REGWRITE_BUFFER_FLUSH(ah);
2866 }
2867 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2868
2869 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2870 {
2871 if (ath9k_hw_mci_is_enabled(ah))
2872 ar9003_mci_bt_gain_ctrl(ah);
2873
2874 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2875 return false;
2876
2877 ath9k_hw_init_pll(ah, NULL);
2878 ah->htc_reset_init = true;
2879 return true;
2880 }
2881 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2882
2883 bool ath9k_hw_disable(struct ath_hw *ah)
2884 {
2885 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2886 return false;
2887
2888 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2889 return false;
2890
2891 ath9k_hw_init_pll(ah, NULL);
2892 return true;
2893 }
2894 EXPORT_SYMBOL(ath9k_hw_disable);
2895
2896 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2897 {
2898 enum eeprom_param gain_param;
2899
2900 if (IS_CHAN_2GHZ(chan))
2901 gain_param = EEP_ANTENNA_GAIN_2G;
2902 else
2903 gain_param = EEP_ANTENNA_GAIN_5G;
2904
2905 return ah->eep_ops->get_eeprom(ah, gain_param);
2906 }
2907
2908 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2909 bool test)
2910 {
2911 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2912 struct ieee80211_channel *channel;
2913 int chan_pwr, new_pwr;
2914
2915 if (!chan)
2916 return;
2917
2918 channel = chan->chan;
2919 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2920 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2921
2922 ah->eep_ops->set_txpower(ah, chan,
2923 ath9k_regd_get_ctl(reg, chan),
2924 get_antenna_gain(ah, chan), new_pwr, test);
2925 }
2926
2927 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2928 {
2929 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2930 struct ath9k_channel *chan = ah->curchan;
2931 struct ieee80211_channel *channel = chan->chan;
2932
2933 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
2934 if (test)
2935 channel->max_power = MAX_RATE_POWER / 2;
2936
2937 ath9k_hw_apply_txpower(ah, chan, test);
2938
2939 if (test)
2940 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2941 }
2942 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2943
2944 void ath9k_hw_setopmode(struct ath_hw *ah)
2945 {
2946 ath9k_hw_set_operating_mode(ah, ah->opmode);
2947 }
2948 EXPORT_SYMBOL(ath9k_hw_setopmode);
2949
2950 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2951 {
2952 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2953 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2954 }
2955 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2956
2957 void ath9k_hw_write_associd(struct ath_hw *ah)
2958 {
2959 struct ath_common *common = ath9k_hw_common(ah);
2960
2961 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2962 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2963 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2964 }
2965 EXPORT_SYMBOL(ath9k_hw_write_associd);
2966
2967 #define ATH9K_MAX_TSF_READ 10
2968
2969 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2970 {
2971 u32 tsf_lower, tsf_upper1, tsf_upper2;
2972 int i;
2973
2974 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2975 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2976 tsf_lower = REG_READ(ah, AR_TSF_L32);
2977 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2978 if (tsf_upper2 == tsf_upper1)
2979 break;
2980 tsf_upper1 = tsf_upper2;
2981 }
2982
2983 WARN_ON( i == ATH9K_MAX_TSF_READ );
2984
2985 return (((u64)tsf_upper1 << 32) | tsf_lower);
2986 }
2987 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2988
2989 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2990 {
2991 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2992 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2993 }
2994 EXPORT_SYMBOL(ath9k_hw_settsf64);
2995
2996 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2997 {
2998 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2999 AH_TSF_WRITE_TIMEOUT))
3000 ath_dbg(ath9k_hw_common(ah), RESET,
3001 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3002
3003 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3004 }
3005 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3006
3007 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
3008 {
3009 if (set)
3010 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3011 else
3012 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3013 }
3014 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3015
3016 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
3017 {
3018 u32 macmode;
3019
3020 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
3021 macmode = AR_2040_JOINED_RX_CLEAR;
3022 else
3023 macmode = 0;
3024
3025 REG_WRITE(ah, AR_2040_MODE, macmode);
3026 }
3027
3028 /* HW Generic timers configuration */
3029
3030 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3031 {
3032 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3033 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3034 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3035 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3036 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3037 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3038 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3039 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3040 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3041 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3042 AR_NDP2_TIMER_MODE, 0x0002},
3043 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3044 AR_NDP2_TIMER_MODE, 0x0004},
3045 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3046 AR_NDP2_TIMER_MODE, 0x0008},
3047 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3048 AR_NDP2_TIMER_MODE, 0x0010},
3049 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3050 AR_NDP2_TIMER_MODE, 0x0020},
3051 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3052 AR_NDP2_TIMER_MODE, 0x0040},
3053 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3054 AR_NDP2_TIMER_MODE, 0x0080}
3055 };
3056
3057 /* HW generic timer primitives */
3058
3059 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3060 {
3061 return REG_READ(ah, AR_TSF_L32);
3062 }
3063 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3064
3065 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah)
3066 {
3067 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3068
3069 if (timer_table->tsf2_enabled) {
3070 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN);
3071 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE);
3072 }
3073 }
3074
3075 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3076 void (*trigger)(void *),
3077 void (*overflow)(void *),
3078 void *arg,
3079 u8 timer_index)
3080 {
3081 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3082 struct ath_gen_timer *timer;
3083
3084 if ((timer_index < AR_FIRST_NDP_TIMER) ||
3085 (timer_index >= ATH_MAX_GEN_TIMER))
3086 return NULL;
3087
3088 if ((timer_index > AR_FIRST_NDP_TIMER) &&
3089 !AR_SREV_9300_20_OR_LATER(ah))
3090 return NULL;
3091
3092 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3093 if (timer == NULL)
3094 return NULL;
3095
3096 /* allocate a hardware generic timer slot */
3097 timer_table->timers[timer_index] = timer;
3098 timer->index = timer_index;
3099 timer->trigger = trigger;
3100 timer->overflow = overflow;
3101 timer->arg = arg;
3102
3103 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) {
3104 timer_table->tsf2_enabled = true;
3105 ath9k_hw_gen_timer_start_tsf2(ah);
3106 }
3107
3108 return timer;
3109 }
3110 EXPORT_SYMBOL(ath_gen_timer_alloc);
3111
3112 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3113 struct ath_gen_timer *timer,
3114 u32 timer_next,
3115 u32 timer_period)
3116 {
3117 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3118 u32 mask = 0;
3119
3120 timer_table->timer_mask |= BIT(timer->index);
3121
3122 /*
3123 * Program generic timer registers
3124 */
3125 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3126 timer_next);
3127 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3128 timer_period);
3129 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3130 gen_tmr_configuration[timer->index].mode_mask);
3131
3132 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3133 /*
3134 * Starting from AR9462, each generic timer can select which tsf
3135 * to use. But we still follow the old rule, 0 - 7 use tsf and
3136 * 8 - 15 use tsf2.
3137 */
3138 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3139 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3140 (1 << timer->index));
3141 else
3142 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3143 (1 << timer->index));
3144 }
3145
3146 if (timer->trigger)
3147 mask |= SM(AR_GENTMR_BIT(timer->index),
3148 AR_IMR_S5_GENTIMER_TRIG);
3149 if (timer->overflow)
3150 mask |= SM(AR_GENTMR_BIT(timer->index),
3151 AR_IMR_S5_GENTIMER_THRESH);
3152
3153 REG_SET_BIT(ah, AR_IMR_S5, mask);
3154
3155 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
3156 ah->imask |= ATH9K_INT_GENTIMER;
3157 ath9k_hw_set_interrupts(ah);
3158 }
3159 }
3160 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3161
3162 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3163 {
3164 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3165
3166 /* Clear generic timer enable bits. */
3167 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3168 gen_tmr_configuration[timer->index].mode_mask);
3169
3170 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3171 /*
3172 * Need to switch back to TSF if it was using TSF2.
3173 */
3174 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3175 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3176 (1 << timer->index));
3177 }
3178 }
3179
3180 /* Disable both trigger and thresh interrupt masks */
3181 REG_CLR_BIT(ah, AR_IMR_S5,
3182 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3183 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3184
3185 timer_table->timer_mask &= ~BIT(timer->index);
3186
3187 if (timer_table->timer_mask == 0) {
3188 ah->imask &= ~ATH9K_INT_GENTIMER;
3189 ath9k_hw_set_interrupts(ah);
3190 }
3191 }
3192 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3193
3194 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3195 {
3196 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3197
3198 /* free the hardware generic timer slot */
3199 timer_table->timers[timer->index] = NULL;
3200 kfree(timer);
3201 }
3202 EXPORT_SYMBOL(ath_gen_timer_free);
3203
3204 /*
3205 * Generic Timer Interrupts handling
3206 */
3207 void ath_gen_timer_isr(struct ath_hw *ah)
3208 {
3209 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3210 struct ath_gen_timer *timer;
3211 unsigned long trigger_mask, thresh_mask;
3212 unsigned int index;
3213
3214 /* get hardware generic timer interrupt status */
3215 trigger_mask = ah->intr_gen_timer_trigger;
3216 thresh_mask = ah->intr_gen_timer_thresh;
3217 trigger_mask &= timer_table->timer_mask;
3218 thresh_mask &= timer_table->timer_mask;
3219
3220 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
3221 timer = timer_table->timers[index];
3222 if (!timer)
3223 continue;
3224 if (!timer->overflow)
3225 continue;
3226
3227 trigger_mask &= ~BIT(index);
3228 timer->overflow(timer->arg);
3229 }
3230
3231 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
3232 timer = timer_table->timers[index];
3233 if (!timer)
3234 continue;
3235 if (!timer->trigger)
3236 continue;
3237 timer->trigger(timer->arg);
3238 }
3239 }
3240 EXPORT_SYMBOL(ath_gen_timer_isr);
3241
3242 /********/
3243 /* HTC */
3244 /********/
3245
3246 static struct {
3247 u32 version;
3248 const char * name;
3249 } ath_mac_bb_names[] = {
3250 /* Devices with external radios */
3251 { AR_SREV_VERSION_5416_PCI, "5416" },
3252 { AR_SREV_VERSION_5416_PCIE, "5418" },
3253 { AR_SREV_VERSION_9100, "9100" },
3254 { AR_SREV_VERSION_9160, "9160" },
3255 /* Single-chip solutions */
3256 { AR_SREV_VERSION_9280, "9280" },
3257 { AR_SREV_VERSION_9285, "9285" },
3258 { AR_SREV_VERSION_9287, "9287" },
3259 { AR_SREV_VERSION_9271, "9271" },
3260 { AR_SREV_VERSION_9300, "9300" },
3261 { AR_SREV_VERSION_9330, "9330" },
3262 { AR_SREV_VERSION_9340, "9340" },
3263 { AR_SREV_VERSION_9485, "9485" },
3264 { AR_SREV_VERSION_9462, "9462" },
3265 { AR_SREV_VERSION_9550, "9550" },
3266 { AR_SREV_VERSION_9565, "9565" },
3267 { AR_SREV_VERSION_9531, "9531" },
3268 { AR_SREV_VERSION_9561, "9561" },
3269 };
3270
3271 /* For devices with external radios */
3272 static struct {
3273 u16 version;
3274 const char * name;
3275 } ath_rf_names[] = {
3276 { 0, "5133" },
3277 { AR_RAD5133_SREV_MAJOR, "5133" },
3278 { AR_RAD5122_SREV_MAJOR, "5122" },
3279 { AR_RAD2133_SREV_MAJOR, "2133" },
3280 { AR_RAD2122_SREV_MAJOR, "2122" }
3281 };
3282
3283 /*
3284 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3285 */
3286 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3287 {
3288 int i;
3289
3290 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3291 if (ath_mac_bb_names[i].version == mac_bb_version) {
3292 return ath_mac_bb_names[i].name;
3293 }
3294 }
3295
3296 return "????";
3297 }
3298
3299 /*
3300 * Return the RF name. "????" is returned if the RF is unknown.
3301 * Used for devices with external radios.
3302 */
3303 static const char *ath9k_hw_rf_name(u16 rf_version)
3304 {
3305 int i;
3306
3307 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3308 if (ath_rf_names[i].version == rf_version) {
3309 return ath_rf_names[i].name;
3310 }
3311 }
3312
3313 return "????";
3314 }
3315
3316 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3317 {
3318 int used;
3319
3320 /* chipsets >= AR9280 are single-chip */
3321 if (AR_SREV_9280_20_OR_LATER(ah)) {
3322 used = scnprintf(hw_name, len,
3323 "Atheros AR%s Rev:%x",
3324 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3325 ah->hw_version.macRev);
3326 }
3327 else {
3328 used = scnprintf(hw_name, len,
3329 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3330 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3331 ah->hw_version.macRev,
3332 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3333 & AR_RADIO_SREV_MAJOR)),
3334 ah->hw_version.phyRev);
3335 }
3336
3337 hw_name[used] = '\0';
3338 }
3339 EXPORT_SYMBOL(ath9k_hw_name);
CRIS linux kernel tree