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x86/topology: Update the 'cpu cores' field in /proc/cpuinfo correctly across CPU...
[cris-mirror.git] / arch / x86 / kvm / vmx.c
blob3dec126aa3022eb11f49d5de695d3658183a48ee
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "cpuid.h"
22 #include "lapic.h"
23
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/mm.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include <linux/nospec.h>
38 #include "kvm_cache_regs.h"
39 #include "x86.h"
40
41 #include <asm/cpu.h>
42 #include <asm/io.h>
43 #include <asm/desc.h>
44 #include <asm/vmx.h>
45 #include <asm/virtext.h>
46 #include <asm/mce.h>
47 #include <asm/fpu/internal.h>
48 #include <asm/perf_event.h>
49 #include <asm/debugreg.h>
50 #include <asm/kexec.h>
51 #include <asm/apic.h>
52 #include <asm/irq_remapping.h>
53 #include <asm/mmu_context.h>
54 #include <asm/nospec-branch.h>
55
56 #include "trace.h"
57 #include "pmu.h"
58
59 #define __ex(x) __kvm_handle_fault_on_reboot(x)
60 #define __ex_clear(x, reg) \
61 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
62
63 MODULE_AUTHOR("Qumranet");
64 MODULE_LICENSE("GPL");
65
66 static const struct x86_cpu_id vmx_cpu_id[] = {
67 X86_FEATURE_MATCH(X86_FEATURE_VMX),
68 {}
69 };
70 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
71
72 static bool __read_mostly enable_vpid = 1;
73 module_param_named(vpid, enable_vpid, bool, 0444);
74
75 static bool __read_mostly enable_vnmi = 1;
76 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
77
78 static bool __read_mostly flexpriority_enabled = 1;
79 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
80
81 static bool __read_mostly enable_ept = 1;
82 module_param_named(ept, enable_ept, bool, S_IRUGO);
83
84 static bool __read_mostly enable_unrestricted_guest = 1;
85 module_param_named(unrestricted_guest,
86 enable_unrestricted_guest, bool, S_IRUGO);
87
88 static bool __read_mostly enable_ept_ad_bits = 1;
89 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
90
91 static bool __read_mostly emulate_invalid_guest_state = true;
92 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
93
94 static bool __read_mostly fasteoi = 1;
95 module_param(fasteoi, bool, S_IRUGO);
96
97 static bool __read_mostly enable_apicv = 1;
98 module_param(enable_apicv, bool, S_IRUGO);
99
100 static bool __read_mostly enable_shadow_vmcs = 1;
101 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
102 /*
103 * If nested=1, nested virtualization is supported, i.e., guests may use
104 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
105 * use VMX instructions.
106 */
107 static bool __read_mostly nested = 0;
108 module_param(nested, bool, S_IRUGO);
109
110 static u64 __read_mostly host_xss;
111
112 static bool __read_mostly enable_pml = 1;
113 module_param_named(pml, enable_pml, bool, S_IRUGO);
114
115 #define MSR_TYPE_R 1
116 #define MSR_TYPE_W 2
117 #define MSR_TYPE_RW 3
118
119 #define MSR_BITMAP_MODE_X2APIC 1
120 #define MSR_BITMAP_MODE_X2APIC_APICV 2
121 #define MSR_BITMAP_MODE_LM 4
122
123 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
124
125 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
126 static int __read_mostly cpu_preemption_timer_multi;
127 static bool __read_mostly enable_preemption_timer = 1;
128 #ifdef CONFIG_X86_64
129 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
130 #endif
131
132 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
133 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
134 #define KVM_VM_CR0_ALWAYS_ON \
135 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
136 #define KVM_CR4_GUEST_OWNED_BITS \
137 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
138 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
139
140 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
141 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
142
143 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
144
145 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
146
147 /*
148 * Hyper-V requires all of these, so mark them as supported even though
149 * they are just treated the same as all-context.
150 */
151 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
152 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
153 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
154 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
155 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
156
157 /*
158 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
159 * ple_gap: upper bound on the amount of time between two successive
160 * executions of PAUSE in a loop. Also indicate if ple enabled.
161 * According to test, this time is usually smaller than 128 cycles.
162 * ple_window: upper bound on the amount of time a guest is allowed to execute
163 * in a PAUSE loop. Tests indicate that most spinlocks are held for
164 * less than 2^12 cycles
165 * Time is measured based on a counter that runs at the same rate as the TSC,
166 * refer SDM volume 3b section 21.6.13 & 22.1.3.
167 */
168 #define KVM_VMX_DEFAULT_PLE_GAP 128
169 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
170 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
171 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
172 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
173 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
174
175 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
176 module_param(ple_gap, int, S_IRUGO);
177
178 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
179 module_param(ple_window, int, S_IRUGO);
180
181 /* Default doubles per-vcpu window every exit. */
182 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
183 module_param(ple_window_grow, int, S_IRUGO);
184
185 /* Default resets per-vcpu window every exit to ple_window. */
186 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
187 module_param(ple_window_shrink, int, S_IRUGO);
188
189 /* Default is to compute the maximum so we can never overflow. */
190 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
191 static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
192 module_param(ple_window_max, int, S_IRUGO);
193
194 extern const ulong vmx_return;
195
196 #define NR_AUTOLOAD_MSRS 8
197
198 struct vmcs {
199 u32 revision_id;
200 u32 abort;
201 char data[0];
202 };
203
204 /*
205 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
206 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
207 * loaded on this CPU (so we can clear them if the CPU goes down).
208 */
209 struct loaded_vmcs {
210 struct vmcs *vmcs;
211 struct vmcs *shadow_vmcs;
212 int cpu;
213 bool launched;
214 bool nmi_known_unmasked;
215 unsigned long vmcs_host_cr3; /* May not match real cr3 */
216 unsigned long vmcs_host_cr4; /* May not match real cr4 */
217 /* Support for vnmi-less CPUs */
218 int soft_vnmi_blocked;
219 ktime_t entry_time;
220 s64 vnmi_blocked_time;
221 unsigned long *msr_bitmap;
222 struct list_head loaded_vmcss_on_cpu_link;
223 };
224
225 struct shared_msr_entry {
226 unsigned index;
227 u64 data;
228 u64 mask;
229 };
230
231 /*
232 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
233 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
234 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
235 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
236 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
237 * More than one of these structures may exist, if L1 runs multiple L2 guests.
238 * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
239 * underlying hardware which will be used to run L2.
240 * This structure is packed to ensure that its layout is identical across
241 * machines (necessary for live migration).
242 * If there are changes in this struct, VMCS12_REVISION must be changed.
243 */
244 typedef u64 natural_width;
245 struct __packed vmcs12 {
246 /* According to the Intel spec, a VMCS region must start with the
247 * following two fields. Then follow implementation-specific data.
248 */
249 u32 revision_id;
250 u32 abort;
251
252 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
253 u32 padding[7]; /* room for future expansion */
254
255 u64 io_bitmap_a;
256 u64 io_bitmap_b;
257 u64 msr_bitmap;
258 u64 vm_exit_msr_store_addr;
259 u64 vm_exit_msr_load_addr;
260 u64 vm_entry_msr_load_addr;
261 u64 tsc_offset;
262 u64 virtual_apic_page_addr;
263 u64 apic_access_addr;
264 u64 posted_intr_desc_addr;
265 u64 vm_function_control;
266 u64 ept_pointer;
267 u64 eoi_exit_bitmap0;
268 u64 eoi_exit_bitmap1;
269 u64 eoi_exit_bitmap2;
270 u64 eoi_exit_bitmap3;
271 u64 eptp_list_address;
272 u64 xss_exit_bitmap;
273 u64 guest_physical_address;
274 u64 vmcs_link_pointer;
275 u64 pml_address;
276 u64 guest_ia32_debugctl;
277 u64 guest_ia32_pat;
278 u64 guest_ia32_efer;
279 u64 guest_ia32_perf_global_ctrl;
280 u64 guest_pdptr0;
281 u64 guest_pdptr1;
282 u64 guest_pdptr2;
283 u64 guest_pdptr3;
284 u64 guest_bndcfgs;
285 u64 host_ia32_pat;
286 u64 host_ia32_efer;
287 u64 host_ia32_perf_global_ctrl;
288 u64 padding64[8]; /* room for future expansion */
289 /*
290 * To allow migration of L1 (complete with its L2 guests) between
291 * machines of different natural widths (32 or 64 bit), we cannot have
292 * unsigned long fields with no explict size. We use u64 (aliased
293 * natural_width) instead. Luckily, x86 is little-endian.
294 */
295 natural_width cr0_guest_host_mask;
296 natural_width cr4_guest_host_mask;
297 natural_width cr0_read_shadow;
298 natural_width cr4_read_shadow;
299 natural_width cr3_target_value0;
300 natural_width cr3_target_value1;
301 natural_width cr3_target_value2;
302 natural_width cr3_target_value3;
303 natural_width exit_qualification;
304 natural_width guest_linear_address;
305 natural_width guest_cr0;
306 natural_width guest_cr3;
307 natural_width guest_cr4;
308 natural_width guest_es_base;
309 natural_width guest_cs_base;
310 natural_width guest_ss_base;
311 natural_width guest_ds_base;
312 natural_width guest_fs_base;
313 natural_width guest_gs_base;
314 natural_width guest_ldtr_base;
315 natural_width guest_tr_base;
316 natural_width guest_gdtr_base;
317 natural_width guest_idtr_base;
318 natural_width guest_dr7;
319 natural_width guest_rsp;
320 natural_width guest_rip;
321 natural_width guest_rflags;
322 natural_width guest_pending_dbg_exceptions;
323 natural_width guest_sysenter_esp;
324 natural_width guest_sysenter_eip;
325 natural_width host_cr0;
326 natural_width host_cr3;
327 natural_width host_cr4;
328 natural_width host_fs_base;
329 natural_width host_gs_base;
330 natural_width host_tr_base;
331 natural_width host_gdtr_base;
332 natural_width host_idtr_base;
333 natural_width host_ia32_sysenter_esp;
334 natural_width host_ia32_sysenter_eip;
335 natural_width host_rsp;
336 natural_width host_rip;
337 natural_width paddingl[8]; /* room for future expansion */
338 u32 pin_based_vm_exec_control;
339 u32 cpu_based_vm_exec_control;
340 u32 exception_bitmap;
341 u32 page_fault_error_code_mask;
342 u32 page_fault_error_code_match;
343 u32 cr3_target_count;
344 u32 vm_exit_controls;
345 u32 vm_exit_msr_store_count;
346 u32 vm_exit_msr_load_count;
347 u32 vm_entry_controls;
348 u32 vm_entry_msr_load_count;
349 u32 vm_entry_intr_info_field;
350 u32 vm_entry_exception_error_code;
351 u32 vm_entry_instruction_len;
352 u32 tpr_threshold;
353 u32 secondary_vm_exec_control;
354 u32 vm_instruction_error;
355 u32 vm_exit_reason;
356 u32 vm_exit_intr_info;
357 u32 vm_exit_intr_error_code;
358 u32 idt_vectoring_info_field;
359 u32 idt_vectoring_error_code;
360 u32 vm_exit_instruction_len;
361 u32 vmx_instruction_info;
362 u32 guest_es_limit;
363 u32 guest_cs_limit;
364 u32 guest_ss_limit;
365 u32 guest_ds_limit;
366 u32 guest_fs_limit;
367 u32 guest_gs_limit;
368 u32 guest_ldtr_limit;
369 u32 guest_tr_limit;
370 u32 guest_gdtr_limit;
371 u32 guest_idtr_limit;
372 u32 guest_es_ar_bytes;
373 u32 guest_cs_ar_bytes;
374 u32 guest_ss_ar_bytes;
375 u32 guest_ds_ar_bytes;
376 u32 guest_fs_ar_bytes;
377 u32 guest_gs_ar_bytes;
378 u32 guest_ldtr_ar_bytes;
379 u32 guest_tr_ar_bytes;
380 u32 guest_interruptibility_info;
381 u32 guest_activity_state;
382 u32 guest_sysenter_cs;
383 u32 host_ia32_sysenter_cs;
384 u32 vmx_preemption_timer_value;
385 u32 padding32[7]; /* room for future expansion */
386 u16 virtual_processor_id;
387 u16 posted_intr_nv;
388 u16 guest_es_selector;
389 u16 guest_cs_selector;
390 u16 guest_ss_selector;
391 u16 guest_ds_selector;
392 u16 guest_fs_selector;
393 u16 guest_gs_selector;
394 u16 guest_ldtr_selector;
395 u16 guest_tr_selector;
396 u16 guest_intr_status;
397 u16 guest_pml_index;
398 u16 host_es_selector;
399 u16 host_cs_selector;
400 u16 host_ss_selector;
401 u16 host_ds_selector;
402 u16 host_fs_selector;
403 u16 host_gs_selector;
404 u16 host_tr_selector;
405 };
406
407 /*
408 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
409 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
410 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
411 */
412 #define VMCS12_REVISION 0x11e57ed0
413
414 /*
415 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
416 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
417 * current implementation, 4K are reserved to avoid future complications.
418 */
419 #define VMCS12_SIZE 0x1000
420
421 /*
422 * VMCS12_MAX_FIELD_INDEX is the highest index value used in any
423 * supported VMCS12 field encoding.
424 */
425 #define VMCS12_MAX_FIELD_INDEX 0x17
426
427 /*
428 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
429 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
430 */
431 struct nested_vmx {
432 /* Has the level1 guest done vmxon? */
433 bool vmxon;
434 gpa_t vmxon_ptr;
435 bool pml_full;
436
437 /* The guest-physical address of the current VMCS L1 keeps for L2 */
438 gpa_t current_vmptr;
439 /*
440 * Cache of the guest's VMCS, existing outside of guest memory.
441 * Loaded from guest memory during VMPTRLD. Flushed to guest
442 * memory during VMCLEAR and VMPTRLD.
443 */
444 struct vmcs12 *cached_vmcs12;
445 /*
446 * Indicates if the shadow vmcs must be updated with the
447 * data hold by vmcs12
448 */
449 bool sync_shadow_vmcs;
450 bool dirty_vmcs12;
451
452 bool change_vmcs01_virtual_x2apic_mode;
453 /* L2 must run next, and mustn't decide to exit to L1. */
454 bool nested_run_pending;
455
456 struct loaded_vmcs vmcs02;
457
458 /*
459 * Guest pages referred to in the vmcs02 with host-physical
460 * pointers, so we must keep them pinned while L2 runs.
461 */
462 struct page *apic_access_page;
463 struct page *virtual_apic_page;
464 struct page *pi_desc_page;
465 struct pi_desc *pi_desc;
466 bool pi_pending;
467 u16 posted_intr_nv;
468
469 struct hrtimer preemption_timer;
470 bool preemption_timer_expired;
471
472 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
473 u64 vmcs01_debugctl;
474
475 u16 vpid02;
476 u16 last_vpid;
477
478 /*
479 * We only store the "true" versions of the VMX capability MSRs. We
480 * generate the "non-true" versions by setting the must-be-1 bits
481 * according to the SDM.
482 */
483 u32 nested_vmx_procbased_ctls_low;
484 u32 nested_vmx_procbased_ctls_high;
485 u32 nested_vmx_secondary_ctls_low;
486 u32 nested_vmx_secondary_ctls_high;
487 u32 nested_vmx_pinbased_ctls_low;
488 u32 nested_vmx_pinbased_ctls_high;
489 u32 nested_vmx_exit_ctls_low;
490 u32 nested_vmx_exit_ctls_high;
491 u32 nested_vmx_entry_ctls_low;
492 u32 nested_vmx_entry_ctls_high;
493 u32 nested_vmx_misc_low;
494 u32 nested_vmx_misc_high;
495 u32 nested_vmx_ept_caps;
496 u32 nested_vmx_vpid_caps;
497 u64 nested_vmx_basic;
498 u64 nested_vmx_cr0_fixed0;
499 u64 nested_vmx_cr0_fixed1;
500 u64 nested_vmx_cr4_fixed0;
501 u64 nested_vmx_cr4_fixed1;
502 u64 nested_vmx_vmcs_enum;
503 u64 nested_vmx_vmfunc_controls;
504
505 /* SMM related state */
506 struct {
507 /* in VMX operation on SMM entry? */
508 bool vmxon;
509 /* in guest mode on SMM entry? */
510 bool guest_mode;
511 } smm;
512 };
513
514 #define POSTED_INTR_ON 0
515 #define POSTED_INTR_SN 1
516
517 /* Posted-Interrupt Descriptor */
518 struct pi_desc {
519 u32 pir[8]; /* Posted interrupt requested */
520 union {
521 struct {
522 /* bit 256 - Outstanding Notification */
523 u16 on : 1,
524 /* bit 257 - Suppress Notification */
525 sn : 1,
526 /* bit 271:258 - Reserved */
527 rsvd_1 : 14;
528 /* bit 279:272 - Notification Vector */
529 u8 nv;
530 /* bit 287:280 - Reserved */
531 u8 rsvd_2;
532 /* bit 319:288 - Notification Destination */
533 u32 ndst;
534 };
535 u64 control;
536 };
537 u32 rsvd[6];
538 } __aligned(64);
539
540 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
541 {
542 return test_and_set_bit(POSTED_INTR_ON,
543 (unsigned long *)&pi_desc->control);
544 }
545
546 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
547 {
548 return test_and_clear_bit(POSTED_INTR_ON,
549 (unsigned long *)&pi_desc->control);
550 }
551
552 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
553 {
554 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
555 }
556
557 static inline void pi_clear_sn(struct pi_desc *pi_desc)
558 {
559 return clear_bit(POSTED_INTR_SN,
560 (unsigned long *)&pi_desc->control);
561 }
562
563 static inline void pi_set_sn(struct pi_desc *pi_desc)
564 {
565 return set_bit(POSTED_INTR_SN,
566 (unsigned long *)&pi_desc->control);
567 }
568
569 static inline void pi_clear_on(struct pi_desc *pi_desc)
570 {
571 clear_bit(POSTED_INTR_ON,
572 (unsigned long *)&pi_desc->control);
573 }
574
575 static inline int pi_test_on(struct pi_desc *pi_desc)
576 {
577 return test_bit(POSTED_INTR_ON,
578 (unsigned long *)&pi_desc->control);
579 }
580
581 static inline int pi_test_sn(struct pi_desc *pi_desc)
582 {
583 return test_bit(POSTED_INTR_SN,
584 (unsigned long *)&pi_desc->control);
585 }
586
587 struct vcpu_vmx {
588 struct kvm_vcpu vcpu;
589 unsigned long host_rsp;
590 u8 fail;
591 u8 msr_bitmap_mode;
592 u32 exit_intr_info;
593 u32 idt_vectoring_info;
594 ulong rflags;
595 struct shared_msr_entry *guest_msrs;
596 int nmsrs;
597 int save_nmsrs;
598 unsigned long host_idt_base;
599 #ifdef CONFIG_X86_64
600 u64 msr_host_kernel_gs_base;
601 u64 msr_guest_kernel_gs_base;
602 #endif
603
604 u64 arch_capabilities;
605 u64 spec_ctrl;
606
607 u32 vm_entry_controls_shadow;
608 u32 vm_exit_controls_shadow;
609 u32 secondary_exec_control;
610
611 /*
612 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
613 * non-nested (L1) guest, it always points to vmcs01. For a nested
614 * guest (L2), it points to a different VMCS.
615 */
616 struct loaded_vmcs vmcs01;
617 struct loaded_vmcs *loaded_vmcs;
618 bool __launched; /* temporary, used in vmx_vcpu_run */
619 struct msr_autoload {
620 unsigned nr;
621 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
622 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
623 } msr_autoload;
624 struct {
625 int loaded;
626 u16 fs_sel, gs_sel, ldt_sel;
627 #ifdef CONFIG_X86_64
628 u16 ds_sel, es_sel;
629 #endif
630 int gs_ldt_reload_needed;
631 int fs_reload_needed;
632 u64 msr_host_bndcfgs;
633 } host_state;
634 struct {
635 int vm86_active;
636 ulong save_rflags;
637 struct kvm_segment segs[8];
638 } rmode;
639 struct {
640 u32 bitmask; /* 4 bits per segment (1 bit per field) */
641 struct kvm_save_segment {
642 u16 selector;
643 unsigned long base;
644 u32 limit;
645 u32 ar;
646 } seg[8];
647 } segment_cache;
648 int vpid;
649 bool emulation_required;
650
651 u32 exit_reason;
652
653 /* Posted interrupt descriptor */
654 struct pi_desc pi_desc;
655
656 /* Support for a guest hypervisor (nested VMX) */
657 struct nested_vmx nested;
658
659 /* Dynamic PLE window. */
660 int ple_window;
661 bool ple_window_dirty;
662
663 /* Support for PML */
664 #define PML_ENTITY_NUM 512
665 struct page *pml_pg;
666
667 /* apic deadline value in host tsc */
668 u64 hv_deadline_tsc;
669
670 u64 current_tsc_ratio;
671
672 u32 host_pkru;
673
674 unsigned long host_debugctlmsr;
675
676 /*
677 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
678 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
679 * in msr_ia32_feature_control_valid_bits.
680 */
681 u64 msr_ia32_feature_control;
682 u64 msr_ia32_feature_control_valid_bits;
683 };
684
685 enum segment_cache_field {
686 SEG_FIELD_SEL = 0,
687 SEG_FIELD_BASE = 1,
688 SEG_FIELD_LIMIT = 2,
689 SEG_FIELD_AR = 3,
690
691 SEG_FIELD_NR = 4
692 };
693
694 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
695 {
696 return container_of(vcpu, struct vcpu_vmx, vcpu);
697 }
698
699 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
700 {
701 return &(to_vmx(vcpu)->pi_desc);
702 }
703
704 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
705 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
706 #define FIELD(number, name) [ROL16(number, 6)] = VMCS12_OFFSET(name)
707 #define FIELD64(number, name) \
708 FIELD(number, name), \
709 [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
710
711
712 static u16 shadow_read_only_fields[] = {
713 #define SHADOW_FIELD_RO(x) x,
714 #include "vmx_shadow_fields.h"
715 };
716 static int max_shadow_read_only_fields =
717 ARRAY_SIZE(shadow_read_only_fields);
718
719 static u16 shadow_read_write_fields[] = {
720 #define SHADOW_FIELD_RW(x) x,
721 #include "vmx_shadow_fields.h"
722 };
723 static int max_shadow_read_write_fields =
724 ARRAY_SIZE(shadow_read_write_fields);
725
726 static const unsigned short vmcs_field_to_offset_table[] = {
727 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
728 FIELD(POSTED_INTR_NV, posted_intr_nv),
729 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
730 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
731 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
732 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
733 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
734 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
735 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
736 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
737 FIELD(GUEST_INTR_STATUS, guest_intr_status),
738 FIELD(GUEST_PML_INDEX, guest_pml_index),
739 FIELD(HOST_ES_SELECTOR, host_es_selector),
740 FIELD(HOST_CS_SELECTOR, host_cs_selector),
741 FIELD(HOST_SS_SELECTOR, host_ss_selector),
742 FIELD(HOST_DS_SELECTOR, host_ds_selector),
743 FIELD(HOST_FS_SELECTOR, host_fs_selector),
744 FIELD(HOST_GS_SELECTOR, host_gs_selector),
745 FIELD(HOST_TR_SELECTOR, host_tr_selector),
746 FIELD64(IO_BITMAP_A, io_bitmap_a),
747 FIELD64(IO_BITMAP_B, io_bitmap_b),
748 FIELD64(MSR_BITMAP, msr_bitmap),
749 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
750 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
751 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
752 FIELD64(TSC_OFFSET, tsc_offset),
753 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
754 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
755 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
756 FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
757 FIELD64(EPT_POINTER, ept_pointer),
758 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
759 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
760 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
761 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
762 FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
763 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
764 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
765 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
766 FIELD64(PML_ADDRESS, pml_address),
767 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
768 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
769 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
770 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
771 FIELD64(GUEST_PDPTR0, guest_pdptr0),
772 FIELD64(GUEST_PDPTR1, guest_pdptr1),
773 FIELD64(GUEST_PDPTR2, guest_pdptr2),
774 FIELD64(GUEST_PDPTR3, guest_pdptr3),
775 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
776 FIELD64(HOST_IA32_PAT, host_ia32_pat),
777 FIELD64(HOST_IA32_EFER, host_ia32_efer),
778 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
779 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
780 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
781 FIELD(EXCEPTION_BITMAP, exception_bitmap),
782 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
783 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
784 FIELD(CR3_TARGET_COUNT, cr3_target_count),
785 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
786 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
787 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
788 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
789 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
790 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
791 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
792 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
793 FIELD(TPR_THRESHOLD, tpr_threshold),
794 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
795 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
796 FIELD(VM_EXIT_REASON, vm_exit_reason),
797 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
798 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
799 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
800 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
801 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
802 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
803 FIELD(GUEST_ES_LIMIT, guest_es_limit),
804 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
805 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
806 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
807 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
808 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
809 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
810 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
811 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
812 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
813 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
814 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
815 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
816 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
817 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
818 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
819 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
820 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
821 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
822 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
823 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
824 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
825 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
826 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
827 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
828 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
829 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
830 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
831 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
832 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
833 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
834 FIELD(EXIT_QUALIFICATION, exit_qualification),
835 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
836 FIELD(GUEST_CR0, guest_cr0),
837 FIELD(GUEST_CR3, guest_cr3),
838 FIELD(GUEST_CR4, guest_cr4),
839 FIELD(GUEST_ES_BASE, guest_es_base),
840 FIELD(GUEST_CS_BASE, guest_cs_base),
841 FIELD(GUEST_SS_BASE, guest_ss_base),
842 FIELD(GUEST_DS_BASE, guest_ds_base),
843 FIELD(GUEST_FS_BASE, guest_fs_base),
844 FIELD(GUEST_GS_BASE, guest_gs_base),
845 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
846 FIELD(GUEST_TR_BASE, guest_tr_base),
847 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
848 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
849 FIELD(GUEST_DR7, guest_dr7),
850 FIELD(GUEST_RSP, guest_rsp),
851 FIELD(GUEST_RIP, guest_rip),
852 FIELD(GUEST_RFLAGS, guest_rflags),
853 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
854 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
855 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
856 FIELD(HOST_CR0, host_cr0),
857 FIELD(HOST_CR3, host_cr3),
858 FIELD(HOST_CR4, host_cr4),
859 FIELD(HOST_FS_BASE, host_fs_base),
860 FIELD(HOST_GS_BASE, host_gs_base),
861 FIELD(HOST_TR_BASE, host_tr_base),
862 FIELD(HOST_GDTR_BASE, host_gdtr_base),
863 FIELD(HOST_IDTR_BASE, host_idtr_base),
864 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
865 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
866 FIELD(HOST_RSP, host_rsp),
867 FIELD(HOST_RIP, host_rip),
868 };
869
870 static inline short vmcs_field_to_offset(unsigned long field)
871 {
872 const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table);
873 unsigned short offset;
874 unsigned index;
875
876 if (field >> 15)
877 return -ENOENT;
878
879 index = ROL16(field, 6);
880 if (index >= size)
881 return -ENOENT;
882
883 index = array_index_nospec(index, size);
884 offset = vmcs_field_to_offset_table[index];
885 if (offset == 0)
886 return -ENOENT;
887 return offset;
888 }
889
890 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
891 {
892 return to_vmx(vcpu)->nested.cached_vmcs12;
893 }
894
895 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
896 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
897 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
898 static bool vmx_xsaves_supported(void);
899 static void vmx_set_segment(struct kvm_vcpu *vcpu,
900 struct kvm_segment *var, int seg);
901 static void vmx_get_segment(struct kvm_vcpu *vcpu,
902 struct kvm_segment *var, int seg);
903 static bool guest_state_valid(struct kvm_vcpu *vcpu);
904 static u32 vmx_segment_access_rights(struct kvm_segment *var);
905 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
906 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
907 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
908 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
909 u16 error_code);
910 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
911 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
912 u32 msr, int type);
913
914 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
915 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
916 /*
917 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
918 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
919 */
920 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
921
922 /*
923 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
924 * can find which vCPU should be waken up.
925 */
926 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
927 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
928
929 enum {
930 VMX_VMREAD_BITMAP,
931 VMX_VMWRITE_BITMAP,
932 VMX_BITMAP_NR
933 };
934
935 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
936
937 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
938 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
939
940 static bool cpu_has_load_ia32_efer;
941 static bool cpu_has_load_perf_global_ctrl;
942
943 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
944 static DEFINE_SPINLOCK(vmx_vpid_lock);
945
946 static struct vmcs_config {
947 int size;
948 int order;
949 u32 basic_cap;
950 u32 revision_id;
951 u32 pin_based_exec_ctrl;
952 u32 cpu_based_exec_ctrl;
953 u32 cpu_based_2nd_exec_ctrl;
954 u32 vmexit_ctrl;
955 u32 vmentry_ctrl;
956 } vmcs_config;
957
958 static struct vmx_capability {
959 u32 ept;
960 u32 vpid;
961 } vmx_capability;
962
963 #define VMX_SEGMENT_FIELD(seg) \
964 [VCPU_SREG_##seg] = { \
965 .selector = GUEST_##seg##_SELECTOR, \
966 .base = GUEST_##seg##_BASE, \
967 .limit = GUEST_##seg##_LIMIT, \
968 .ar_bytes = GUEST_##seg##_AR_BYTES, \
969 }
970
971 static const struct kvm_vmx_segment_field {
972 unsigned selector;
973 unsigned base;
974 unsigned limit;
975 unsigned ar_bytes;
976 } kvm_vmx_segment_fields[] = {
977 VMX_SEGMENT_FIELD(CS),
978 VMX_SEGMENT_FIELD(DS),
979 VMX_SEGMENT_FIELD(ES),
980 VMX_SEGMENT_FIELD(FS),
981 VMX_SEGMENT_FIELD(GS),
982 VMX_SEGMENT_FIELD(SS),
983 VMX_SEGMENT_FIELD(TR),
984 VMX_SEGMENT_FIELD(LDTR),
985 };
986
987 static u64 host_efer;
988
989 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
990
991 /*
992 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
993 * away by decrementing the array size.
994 */
995 static const u32 vmx_msr_index[] = {
996 #ifdef CONFIG_X86_64
997 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
998 #endif
999 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1000 };
1001
1002 static inline bool is_exception_n(u32 intr_info, u8 vector)
1003 {
1004 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1005 INTR_INFO_VALID_MASK)) ==
1006 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1007 }
1008
1009 static inline bool is_debug(u32 intr_info)
1010 {
1011 return is_exception_n(intr_info, DB_VECTOR);
1012 }
1013
1014 static inline bool is_breakpoint(u32 intr_info)
1015 {
1016 return is_exception_n(intr_info, BP_VECTOR);
1017 }
1018
1019 static inline bool is_page_fault(u32 intr_info)
1020 {
1021 return is_exception_n(intr_info, PF_VECTOR);
1022 }
1023
1024 static inline bool is_no_device(u32 intr_info)
1025 {
1026 return is_exception_n(intr_info, NM_VECTOR);
1027 }
1028
1029 static inline bool is_invalid_opcode(u32 intr_info)
1030 {
1031 return is_exception_n(intr_info, UD_VECTOR);
1032 }
1033
1034 static inline bool is_external_interrupt(u32 intr_info)
1035 {
1036 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1037 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1038 }
1039
1040 static inline bool is_machine_check(u32 intr_info)
1041 {
1042 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1043 INTR_INFO_VALID_MASK)) ==
1044 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1045 }
1046
1047 static inline bool cpu_has_vmx_msr_bitmap(void)
1048 {
1049 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1050 }
1051
1052 static inline bool cpu_has_vmx_tpr_shadow(void)
1053 {
1054 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1055 }
1056
1057 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1058 {
1059 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1060 }
1061
1062 static inline bool cpu_has_secondary_exec_ctrls(void)
1063 {
1064 return vmcs_config.cpu_based_exec_ctrl &
1065 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1066 }
1067
1068 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1069 {
1070 return vmcs_config.cpu_based_2nd_exec_ctrl &
1071 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1072 }
1073
1074 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1075 {
1076 return vmcs_config.cpu_based_2nd_exec_ctrl &
1077 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1078 }
1079
1080 static inline bool cpu_has_vmx_apic_register_virt(void)
1081 {
1082 return vmcs_config.cpu_based_2nd_exec_ctrl &
1083 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1084 }
1085
1086 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1087 {
1088 return vmcs_config.cpu_based_2nd_exec_ctrl &
1089 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1090 }
1091
1092 /*
1093 * Comment's format: document - errata name - stepping - processor name.
1094 * Refer from
1095 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1096 */
1097 static u32 vmx_preemption_cpu_tfms[] = {
1098 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1099 0x000206E6,
1100 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1101 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1102 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1103 0x00020652,
1104 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1105 0x00020655,
1106 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1107 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1108 /*
1109 * 320767.pdf - AAP86 - B1 -
1110 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1111 */
1112 0x000106E5,
1113 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1114 0x000106A0,
1115 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1116 0x000106A1,
1117 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1118 0x000106A4,
1119 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1120 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1121 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1122 0x000106A5,
1123 };
1124
1125 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1126 {
1127 u32 eax = cpuid_eax(0x00000001), i;
1128
1129 /* Clear the reserved bits */
1130 eax &= ~(0x3U << 14 | 0xfU << 28);
1131 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1132 if (eax == vmx_preemption_cpu_tfms[i])
1133 return true;
1134
1135 return false;
1136 }
1137
1138 static inline bool cpu_has_vmx_preemption_timer(void)
1139 {
1140 return vmcs_config.pin_based_exec_ctrl &
1141 PIN_BASED_VMX_PREEMPTION_TIMER;
1142 }
1143
1144 static inline bool cpu_has_vmx_posted_intr(void)
1145 {
1146 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1147 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1148 }
1149
1150 static inline bool cpu_has_vmx_apicv(void)
1151 {
1152 return cpu_has_vmx_apic_register_virt() &&
1153 cpu_has_vmx_virtual_intr_delivery() &&
1154 cpu_has_vmx_posted_intr();
1155 }
1156
1157 static inline bool cpu_has_vmx_flexpriority(void)
1158 {
1159 return cpu_has_vmx_tpr_shadow() &&
1160 cpu_has_vmx_virtualize_apic_accesses();
1161 }
1162
1163 static inline bool cpu_has_vmx_ept_execute_only(void)
1164 {
1165 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1166 }
1167
1168 static inline bool cpu_has_vmx_ept_2m_page(void)
1169 {
1170 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1171 }
1172
1173 static inline bool cpu_has_vmx_ept_1g_page(void)
1174 {
1175 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1176 }
1177
1178 static inline bool cpu_has_vmx_ept_4levels(void)
1179 {
1180 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1181 }
1182
1183 static inline bool cpu_has_vmx_ept_mt_wb(void)
1184 {
1185 return vmx_capability.ept & VMX_EPTP_WB_BIT;
1186 }
1187
1188 static inline bool cpu_has_vmx_ept_5levels(void)
1189 {
1190 return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1191 }
1192
1193 static inline bool cpu_has_vmx_ept_ad_bits(void)
1194 {
1195 return vmx_capability.ept & VMX_EPT_AD_BIT;
1196 }
1197
1198 static inline bool cpu_has_vmx_invept_context(void)
1199 {
1200 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1201 }
1202
1203 static inline bool cpu_has_vmx_invept_global(void)
1204 {
1205 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1206 }
1207
1208 static inline bool cpu_has_vmx_invvpid_single(void)
1209 {
1210 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1211 }
1212
1213 static inline bool cpu_has_vmx_invvpid_global(void)
1214 {
1215 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1216 }
1217
1218 static inline bool cpu_has_vmx_invvpid(void)
1219 {
1220 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1221 }
1222
1223 static inline bool cpu_has_vmx_ept(void)
1224 {
1225 return vmcs_config.cpu_based_2nd_exec_ctrl &
1226 SECONDARY_EXEC_ENABLE_EPT;
1227 }
1228
1229 static inline bool cpu_has_vmx_unrestricted_guest(void)
1230 {
1231 return vmcs_config.cpu_based_2nd_exec_ctrl &
1232 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1233 }
1234
1235 static inline bool cpu_has_vmx_ple(void)
1236 {
1237 return vmcs_config.cpu_based_2nd_exec_ctrl &
1238 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1239 }
1240
1241 static inline bool cpu_has_vmx_basic_inout(void)
1242 {
1243 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1244 }
1245
1246 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1247 {
1248 return flexpriority_enabled && lapic_in_kernel(vcpu);
1249 }
1250
1251 static inline bool cpu_has_vmx_vpid(void)
1252 {
1253 return vmcs_config.cpu_based_2nd_exec_ctrl &
1254 SECONDARY_EXEC_ENABLE_VPID;
1255 }
1256
1257 static inline bool cpu_has_vmx_rdtscp(void)
1258 {
1259 return vmcs_config.cpu_based_2nd_exec_ctrl &
1260 SECONDARY_EXEC_RDTSCP;
1261 }
1262
1263 static inline bool cpu_has_vmx_invpcid(void)
1264 {
1265 return vmcs_config.cpu_based_2nd_exec_ctrl &
1266 SECONDARY_EXEC_ENABLE_INVPCID;
1267 }
1268
1269 static inline bool cpu_has_virtual_nmis(void)
1270 {
1271 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1272 }
1273
1274 static inline bool cpu_has_vmx_wbinvd_exit(void)
1275 {
1276 return vmcs_config.cpu_based_2nd_exec_ctrl &
1277 SECONDARY_EXEC_WBINVD_EXITING;
1278 }
1279
1280 static inline bool cpu_has_vmx_shadow_vmcs(void)
1281 {
1282 u64 vmx_msr;
1283 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1284 /* check if the cpu supports writing r/o exit information fields */
1285 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1286 return false;
1287
1288 return vmcs_config.cpu_based_2nd_exec_ctrl &
1289 SECONDARY_EXEC_SHADOW_VMCS;
1290 }
1291
1292 static inline bool cpu_has_vmx_pml(void)
1293 {
1294 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1295 }
1296
1297 static inline bool cpu_has_vmx_tsc_scaling(void)
1298 {
1299 return vmcs_config.cpu_based_2nd_exec_ctrl &
1300 SECONDARY_EXEC_TSC_SCALING;
1301 }
1302
1303 static inline bool cpu_has_vmx_vmfunc(void)
1304 {
1305 return vmcs_config.cpu_based_2nd_exec_ctrl &
1306 SECONDARY_EXEC_ENABLE_VMFUNC;
1307 }
1308
1309 static inline bool report_flexpriority(void)
1310 {
1311 return flexpriority_enabled;
1312 }
1313
1314 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1315 {
1316 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1317 }
1318
1319 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1320 {
1321 return vmcs12->cpu_based_vm_exec_control & bit;
1322 }
1323
1324 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1325 {
1326 return (vmcs12->cpu_based_vm_exec_control &
1327 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1328 (vmcs12->secondary_vm_exec_control & bit);
1329 }
1330
1331 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1332 {
1333 return vmcs12->pin_based_vm_exec_control &
1334 PIN_BASED_VMX_PREEMPTION_TIMER;
1335 }
1336
1337 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1338 {
1339 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1340 }
1341
1342 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1343 {
1344 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
1345 }
1346
1347 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1348 {
1349 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1350 }
1351
1352 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1353 {
1354 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1355 }
1356
1357 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1358 {
1359 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1360 }
1361
1362 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1363 {
1364 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1365 }
1366
1367 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1368 {
1369 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1370 }
1371
1372 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1373 {
1374 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1375 }
1376
1377 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
1378 {
1379 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
1380 }
1381
1382 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
1383 {
1384 return nested_cpu_has_vmfunc(vmcs12) &&
1385 (vmcs12->vm_function_control &
1386 VMX_VMFUNC_EPTP_SWITCHING);
1387 }
1388
1389 static inline bool is_nmi(u32 intr_info)
1390 {
1391 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1392 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1393 }
1394
1395 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1396 u32 exit_intr_info,
1397 unsigned long exit_qualification);
1398 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1399 struct vmcs12 *vmcs12,
1400 u32 reason, unsigned long qualification);
1401
1402 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1403 {
1404 int i;
1405
1406 for (i = 0; i < vmx->nmsrs; ++i)
1407 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1408 return i;
1409 return -1;
1410 }
1411
1412 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1413 {
1414 struct {
1415 u64 vpid : 16;
1416 u64 rsvd : 48;
1417 u64 gva;
1418 } operand = { vpid, 0, gva };
1419
1420 asm volatile (__ex(ASM_VMX_INVVPID)
1421 /* CF==1 or ZF==1 --> rc = -1 */
1422 "; ja 1f ; ud2 ; 1:"
1423 : : "a"(&operand), "c"(ext) : "cc", "memory");
1424 }
1425
1426 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1427 {
1428 struct {
1429 u64 eptp, gpa;
1430 } operand = {eptp, gpa};
1431
1432 asm volatile (__ex(ASM_VMX_INVEPT)
1433 /* CF==1 or ZF==1 --> rc = -1 */
1434 "; ja 1f ; ud2 ; 1:\n"
1435 : : "a" (&operand), "c" (ext) : "cc", "memory");
1436 }
1437
1438 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1439 {
1440 int i;
1441
1442 i = __find_msr_index(vmx, msr);
1443 if (i >= 0)
1444 return &vmx->guest_msrs[i];
1445 return NULL;
1446 }
1447
1448 static void vmcs_clear(struct vmcs *vmcs)
1449 {
1450 u64 phys_addr = __pa(vmcs);
1451 u8 error;
1452
1453 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1454 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1455 : "cc", "memory");
1456 if (error)
1457 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1458 vmcs, phys_addr);
1459 }
1460
1461 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1462 {
1463 vmcs_clear(loaded_vmcs->vmcs);
1464 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1465 vmcs_clear(loaded_vmcs->shadow_vmcs);
1466 loaded_vmcs->cpu = -1;
1467 loaded_vmcs->launched = 0;
1468 }
1469
1470 static void vmcs_load(struct vmcs *vmcs)
1471 {
1472 u64 phys_addr = __pa(vmcs);
1473 u8 error;
1474
1475 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1476 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1477 : "cc", "memory");
1478 if (error)
1479 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1480 vmcs, phys_addr);
1481 }
1482
1483 #ifdef CONFIG_KEXEC_CORE
1484 /*
1485 * This bitmap is used to indicate whether the vmclear
1486 * operation is enabled on all cpus. All disabled by
1487 * default.
1488 */
1489 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1490
1491 static inline void crash_enable_local_vmclear(int cpu)
1492 {
1493 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1494 }
1495
1496 static inline void crash_disable_local_vmclear(int cpu)
1497 {
1498 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1499 }
1500
1501 static inline int crash_local_vmclear_enabled(int cpu)
1502 {
1503 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1504 }
1505
1506 static void crash_vmclear_local_loaded_vmcss(void)
1507 {
1508 int cpu = raw_smp_processor_id();
1509 struct loaded_vmcs *v;
1510
1511 if (!crash_local_vmclear_enabled(cpu))
1512 return;
1513
1514 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1515 loaded_vmcss_on_cpu_link)
1516 vmcs_clear(v->vmcs);
1517 }
1518 #else
1519 static inline void crash_enable_local_vmclear(int cpu) { }
1520 static inline void crash_disable_local_vmclear(int cpu) { }
1521 #endif /* CONFIG_KEXEC_CORE */
1522
1523 static void __loaded_vmcs_clear(void *arg)
1524 {
1525 struct loaded_vmcs *loaded_vmcs = arg;
1526 int cpu = raw_smp_processor_id();
1527
1528 if (loaded_vmcs->cpu != cpu)
1529 return; /* vcpu migration can race with cpu offline */
1530 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1531 per_cpu(current_vmcs, cpu) = NULL;
1532 crash_disable_local_vmclear(cpu);
1533 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1534
1535 /*
1536 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1537 * is before setting loaded_vmcs->vcpu to -1 which is done in
1538 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1539 * then adds the vmcs into percpu list before it is deleted.
1540 */
1541 smp_wmb();
1542
1543 loaded_vmcs_init(loaded_vmcs);
1544 crash_enable_local_vmclear(cpu);
1545 }
1546
1547 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1548 {
1549 int cpu = loaded_vmcs->cpu;
1550
1551 if (cpu != -1)
1552 smp_call_function_single(cpu,
1553 __loaded_vmcs_clear, loaded_vmcs, 1);
1554 }
1555
1556 static inline void vpid_sync_vcpu_single(int vpid)
1557 {
1558 if (vpid == 0)
1559 return;
1560
1561 if (cpu_has_vmx_invvpid_single())
1562 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1563 }
1564
1565 static inline void vpid_sync_vcpu_global(void)
1566 {
1567 if (cpu_has_vmx_invvpid_global())
1568 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1569 }
1570
1571 static inline void vpid_sync_context(int vpid)
1572 {
1573 if (cpu_has_vmx_invvpid_single())
1574 vpid_sync_vcpu_single(vpid);
1575 else
1576 vpid_sync_vcpu_global();
1577 }
1578
1579 static inline void ept_sync_global(void)
1580 {
1581 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1582 }
1583
1584 static inline void ept_sync_context(u64 eptp)
1585 {
1586 if (cpu_has_vmx_invept_context())
1587 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1588 else
1589 ept_sync_global();
1590 }
1591
1592 static __always_inline void vmcs_check16(unsigned long field)
1593 {
1594 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1595 "16-bit accessor invalid for 64-bit field");
1596 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1597 "16-bit accessor invalid for 64-bit high field");
1598 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1599 "16-bit accessor invalid for 32-bit high field");
1600 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1601 "16-bit accessor invalid for natural width field");
1602 }
1603
1604 static __always_inline void vmcs_check32(unsigned long field)
1605 {
1606 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1607 "32-bit accessor invalid for 16-bit field");
1608 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1609 "32-bit accessor invalid for natural width field");
1610 }
1611
1612 static __always_inline void vmcs_check64(unsigned long field)
1613 {
1614 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1615 "64-bit accessor invalid for 16-bit field");
1616 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1617 "64-bit accessor invalid for 64-bit high field");
1618 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1619 "64-bit accessor invalid for 32-bit field");
1620 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1621 "64-bit accessor invalid for natural width field");
1622 }
1623
1624 static __always_inline void vmcs_checkl(unsigned long field)
1625 {
1626 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1627 "Natural width accessor invalid for 16-bit field");
1628 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1629 "Natural width accessor invalid for 64-bit field");
1630 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1631 "Natural width accessor invalid for 64-bit high field");
1632 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1633 "Natural width accessor invalid for 32-bit field");
1634 }
1635
1636 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1637 {
1638 unsigned long value;
1639
1640 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1641 : "=a"(value) : "d"(field) : "cc");
1642 return value;
1643 }
1644
1645 static __always_inline u16 vmcs_read16(unsigned long field)
1646 {
1647 vmcs_check16(field);
1648 return __vmcs_readl(field);
1649 }
1650
1651 static __always_inline u32 vmcs_read32(unsigned long field)
1652 {
1653 vmcs_check32(field);
1654 return __vmcs_readl(field);
1655 }
1656
1657 static __always_inline u64 vmcs_read64(unsigned long field)
1658 {
1659 vmcs_check64(field);
1660 #ifdef CONFIG_X86_64
1661 return __vmcs_readl(field);
1662 #else
1663 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1664 #endif
1665 }
1666
1667 static __always_inline unsigned long vmcs_readl(unsigned long field)
1668 {
1669 vmcs_checkl(field);
1670 return __vmcs_readl(field);
1671 }
1672
1673 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1674 {
1675 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1676 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1677 dump_stack();
1678 }
1679
1680 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1681 {
1682 u8 error;
1683
1684 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1685 : "=q"(error) : "a"(value), "d"(field) : "cc");
1686 if (unlikely(error))
1687 vmwrite_error(field, value);
1688 }
1689
1690 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1691 {
1692 vmcs_check16(field);
1693 __vmcs_writel(field, value);
1694 }
1695
1696 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1697 {
1698 vmcs_check32(field);
1699 __vmcs_writel(field, value);
1700 }
1701
1702 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1703 {
1704 vmcs_check64(field);
1705 __vmcs_writel(field, value);
1706 #ifndef CONFIG_X86_64
1707 asm volatile ("");
1708 __vmcs_writel(field+1, value >> 32);
1709 #endif
1710 }
1711
1712 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1713 {
1714 vmcs_checkl(field);
1715 __vmcs_writel(field, value);
1716 }
1717
1718 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1719 {
1720 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1721 "vmcs_clear_bits does not support 64-bit fields");
1722 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1723 }
1724
1725 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1726 {
1727 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1728 "vmcs_set_bits does not support 64-bit fields");
1729 __vmcs_writel(field, __vmcs_readl(field) | mask);
1730 }
1731
1732 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1733 {
1734 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1735 }
1736
1737 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1738 {
1739 vmcs_write32(VM_ENTRY_CONTROLS, val);
1740 vmx->vm_entry_controls_shadow = val;
1741 }
1742
1743 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1744 {
1745 if (vmx->vm_entry_controls_shadow != val)
1746 vm_entry_controls_init(vmx, val);
1747 }
1748
1749 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1750 {
1751 return vmx->vm_entry_controls_shadow;
1752 }
1753
1754
1755 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1756 {
1757 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1758 }
1759
1760 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1761 {
1762 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1763 }
1764
1765 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1766 {
1767 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1768 }
1769
1770 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1771 {
1772 vmcs_write32(VM_EXIT_CONTROLS, val);
1773 vmx->vm_exit_controls_shadow = val;
1774 }
1775
1776 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1777 {
1778 if (vmx->vm_exit_controls_shadow != val)
1779 vm_exit_controls_init(vmx, val);
1780 }
1781
1782 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1783 {
1784 return vmx->vm_exit_controls_shadow;
1785 }
1786
1787
1788 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1789 {
1790 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1791 }
1792
1793 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1794 {
1795 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1796 }
1797
1798 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1799 {
1800 vmx->segment_cache.bitmask = 0;
1801 }
1802
1803 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1804 unsigned field)
1805 {
1806 bool ret;
1807 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1808
1809 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1810 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1811 vmx->segment_cache.bitmask = 0;
1812 }
1813 ret = vmx->segment_cache.bitmask & mask;
1814 vmx->segment_cache.bitmask |= mask;
1815 return ret;
1816 }
1817
1818 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1819 {
1820 u16 *p = &vmx->segment_cache.seg[seg].selector;
1821
1822 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1823 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1824 return *p;
1825 }
1826
1827 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1828 {
1829 ulong *p = &vmx->segment_cache.seg[seg].base;
1830
1831 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1832 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1833 return *p;
1834 }
1835
1836 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1837 {
1838 u32 *p = &vmx->segment_cache.seg[seg].limit;
1839
1840 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1841 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1842 return *p;
1843 }
1844
1845 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1846 {
1847 u32 *p = &vmx->segment_cache.seg[seg].ar;
1848
1849 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1850 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1851 return *p;
1852 }
1853
1854 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1855 {
1856 u32 eb;
1857
1858 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1859 (1u << DB_VECTOR) | (1u << AC_VECTOR);
1860 if ((vcpu->guest_debug &
1861 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1862 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1863 eb |= 1u << BP_VECTOR;
1864 if (to_vmx(vcpu)->rmode.vm86_active)
1865 eb = ~0;
1866 if (enable_ept)
1867 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1868
1869 /* When we are running a nested L2 guest and L1 specified for it a
1870 * certain exception bitmap, we must trap the same exceptions and pass
1871 * them to L1. When running L2, we will only handle the exceptions
1872 * specified above if L1 did not want them.
1873 */
1874 if (is_guest_mode(vcpu))
1875 eb |= get_vmcs12(vcpu)->exception_bitmap;
1876
1877 vmcs_write32(EXCEPTION_BITMAP, eb);
1878 }
1879
1880 /*
1881 * Check if MSR is intercepted for currently loaded MSR bitmap.
1882 */
1883 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
1884 {
1885 unsigned long *msr_bitmap;
1886 int f = sizeof(unsigned long);
1887
1888 if (!cpu_has_vmx_msr_bitmap())
1889 return true;
1890
1891 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
1892
1893 if (msr <= 0x1fff) {
1894 return !!test_bit(msr, msr_bitmap + 0x800 / f);
1895 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1896 msr &= 0x1fff;
1897 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
1898 }
1899
1900 return true;
1901 }
1902
1903 /*
1904 * Check if MSR is intercepted for L01 MSR bitmap.
1905 */
1906 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
1907 {
1908 unsigned long *msr_bitmap;
1909 int f = sizeof(unsigned long);
1910
1911 if (!cpu_has_vmx_msr_bitmap())
1912 return true;
1913
1914 msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
1915
1916 if (msr <= 0x1fff) {
1917 return !!test_bit(msr, msr_bitmap + 0x800 / f);
1918 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1919 msr &= 0x1fff;
1920 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
1921 }
1922
1923 return true;
1924 }
1925
1926 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1927 unsigned long entry, unsigned long exit)
1928 {
1929 vm_entry_controls_clearbit(vmx, entry);
1930 vm_exit_controls_clearbit(vmx, exit);
1931 }
1932
1933 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1934 {
1935 unsigned i;
1936 struct msr_autoload *m = &vmx->msr_autoload;
1937
1938 switch (msr) {
1939 case MSR_EFER:
1940 if (cpu_has_load_ia32_efer) {
1941 clear_atomic_switch_msr_special(vmx,
1942 VM_ENTRY_LOAD_IA32_EFER,
1943 VM_EXIT_LOAD_IA32_EFER);
1944 return;
1945 }
1946 break;
1947 case MSR_CORE_PERF_GLOBAL_CTRL:
1948 if (cpu_has_load_perf_global_ctrl) {
1949 clear_atomic_switch_msr_special(vmx,
1950 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1951 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1952 return;
1953 }
1954 break;
1955 }
1956
1957 for (i = 0; i < m->nr; ++i)
1958 if (m->guest[i].index == msr)
1959 break;
1960
1961 if (i == m->nr)
1962 return;
1963 --m->nr;
1964 m->guest[i] = m->guest[m->nr];
1965 m->host[i] = m->host[m->nr];
1966 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1967 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1968 }
1969
1970 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1971 unsigned long entry, unsigned long exit,
1972 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1973 u64 guest_val, u64 host_val)
1974 {
1975 vmcs_write64(guest_val_vmcs, guest_val);
1976 vmcs_write64(host_val_vmcs, host_val);
1977 vm_entry_controls_setbit(vmx, entry);
1978 vm_exit_controls_setbit(vmx, exit);
1979 }
1980
1981 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1982 u64 guest_val, u64 host_val)
1983 {
1984 unsigned i;
1985 struct msr_autoload *m = &vmx->msr_autoload;
1986
1987 switch (msr) {
1988 case MSR_EFER:
1989 if (cpu_has_load_ia32_efer) {
1990 add_atomic_switch_msr_special(vmx,
1991 VM_ENTRY_LOAD_IA32_EFER,
1992 VM_EXIT_LOAD_IA32_EFER,
1993 GUEST_IA32_EFER,
1994 HOST_IA32_EFER,
1995 guest_val, host_val);
1996 return;
1997 }
1998 break;
1999 case MSR_CORE_PERF_GLOBAL_CTRL:
2000 if (cpu_has_load_perf_global_ctrl) {
2001 add_atomic_switch_msr_special(vmx,
2002 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2003 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2004 GUEST_IA32_PERF_GLOBAL_CTRL,
2005 HOST_IA32_PERF_GLOBAL_CTRL,
2006 guest_val, host_val);
2007 return;
2008 }
2009 break;
2010 case MSR_IA32_PEBS_ENABLE:
2011 /* PEBS needs a quiescent period after being disabled (to write
2012 * a record). Disabling PEBS through VMX MSR swapping doesn't
2013 * provide that period, so a CPU could write host's record into
2014 * guest's memory.
2015 */
2016 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
2017 }
2018
2019 for (i = 0; i < m->nr; ++i)
2020 if (m->guest[i].index == msr)
2021 break;
2022
2023 if (i == NR_AUTOLOAD_MSRS) {
2024 printk_once(KERN_WARNING "Not enough msr switch entries. "
2025 "Can't add msr %x\n", msr);
2026 return;
2027 } else if (i == m->nr) {
2028 ++m->nr;
2029 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2030 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2031 }
2032
2033 m->guest[i].index = msr;
2034 m->guest[i].value = guest_val;
2035 m->host[i].index = msr;
2036 m->host[i].value = host_val;
2037 }
2038
2039 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2040 {
2041 u64 guest_efer = vmx->vcpu.arch.efer;
2042 u64 ignore_bits = 0;
2043
2044 if (!enable_ept) {
2045 /*
2046 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2047 * host CPUID is more efficient than testing guest CPUID
2048 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2049 */
2050 if (boot_cpu_has(X86_FEATURE_SMEP))
2051 guest_efer |= EFER_NX;
2052 else if (!(guest_efer & EFER_NX))
2053 ignore_bits |= EFER_NX;
2054 }
2055
2056 /*
2057 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2058 */
2059 ignore_bits |= EFER_SCE;
2060 #ifdef CONFIG_X86_64
2061 ignore_bits |= EFER_LMA | EFER_LME;
2062 /* SCE is meaningful only in long mode on Intel */
2063 if (guest_efer & EFER_LMA)
2064 ignore_bits &= ~(u64)EFER_SCE;
2065 #endif
2066
2067 clear_atomic_switch_msr(vmx, MSR_EFER);
2068
2069 /*
2070 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2071 * On CPUs that support "load IA32_EFER", always switch EFER
2072 * atomically, since it's faster than switching it manually.
2073 */
2074 if (cpu_has_load_ia32_efer ||
2075 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2076 if (!(guest_efer & EFER_LMA))
2077 guest_efer &= ~EFER_LME;
2078 if (guest_efer != host_efer)
2079 add_atomic_switch_msr(vmx, MSR_EFER,
2080 guest_efer, host_efer);
2081 return false;
2082 } else {
2083 guest_efer &= ~ignore_bits;
2084 guest_efer |= host_efer & ignore_bits;
2085
2086 vmx->guest_msrs[efer_offset].data = guest_efer;
2087 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2088
2089 return true;
2090 }
2091 }
2092
2093 #ifdef CONFIG_X86_32
2094 /*
2095 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2096 * VMCS rather than the segment table. KVM uses this helper to figure
2097 * out the current bases to poke them into the VMCS before entry.
2098 */
2099 static unsigned long segment_base(u16 selector)
2100 {
2101 struct desc_struct *table;
2102 unsigned long v;
2103
2104 if (!(selector & ~SEGMENT_RPL_MASK))
2105 return 0;
2106
2107 table = get_current_gdt_ro();
2108
2109 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2110 u16 ldt_selector = kvm_read_ldt();
2111
2112 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2113 return 0;
2114
2115 table = (struct desc_struct *)segment_base(ldt_selector);
2116 }
2117 v = get_desc_base(&table[selector >> 3]);
2118 return v;
2119 }
2120 #endif
2121
2122 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2123 {
2124 struct vcpu_vmx *vmx = to_vmx(vcpu);
2125 int i;
2126
2127 if (vmx->host_state.loaded)
2128 return;
2129
2130 vmx->host_state.loaded = 1;
2131 /*
2132 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2133 * allow segment selectors with cpl > 0 or ti == 1.
2134 */
2135 vmx->host_state.ldt_sel = kvm_read_ldt();
2136 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2137 savesegment(fs, vmx->host_state.fs_sel);
2138 if (!(vmx->host_state.fs_sel & 7)) {
2139 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2140 vmx->host_state.fs_reload_needed = 0;
2141 } else {
2142 vmcs_write16(HOST_FS_SELECTOR, 0);
2143 vmx->host_state.fs_reload_needed = 1;
2144 }
2145 savesegment(gs, vmx->host_state.gs_sel);
2146 if (!(vmx->host_state.gs_sel & 7))
2147 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2148 else {
2149 vmcs_write16(HOST_GS_SELECTOR, 0);
2150 vmx->host_state.gs_ldt_reload_needed = 1;
2151 }
2152
2153 #ifdef CONFIG_X86_64
2154 savesegment(ds, vmx->host_state.ds_sel);
2155 savesegment(es, vmx->host_state.es_sel);
2156 #endif
2157
2158 #ifdef CONFIG_X86_64
2159 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2160 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2161 #else
2162 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2163 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2164 #endif
2165
2166 #ifdef CONFIG_X86_64
2167 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2168 if (is_long_mode(&vmx->vcpu))
2169 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2170 #endif
2171 if (boot_cpu_has(X86_FEATURE_MPX))
2172 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2173 for (i = 0; i < vmx->save_nmsrs; ++i)
2174 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2175 vmx->guest_msrs[i].data,
2176 vmx->guest_msrs[i].mask);
2177 }
2178
2179 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2180 {
2181 if (!vmx->host_state.loaded)
2182 return;
2183
2184 ++vmx->vcpu.stat.host_state_reload;
2185 vmx->host_state.loaded = 0;
2186 #ifdef CONFIG_X86_64
2187 if (is_long_mode(&vmx->vcpu))
2188 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2189 #endif
2190 if (vmx->host_state.gs_ldt_reload_needed) {
2191 kvm_load_ldt(vmx->host_state.ldt_sel);
2192 #ifdef CONFIG_X86_64
2193 load_gs_index(vmx->host_state.gs_sel);
2194 #else
2195 loadsegment(gs, vmx->host_state.gs_sel);
2196 #endif
2197 }
2198 if (vmx->host_state.fs_reload_needed)
2199 loadsegment(fs, vmx->host_state.fs_sel);
2200 #ifdef CONFIG_X86_64
2201 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2202 loadsegment(ds, vmx->host_state.ds_sel);
2203 loadsegment(es, vmx->host_state.es_sel);
2204 }
2205 #endif
2206 invalidate_tss_limit();
2207 #ifdef CONFIG_X86_64
2208 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2209 #endif
2210 if (vmx->host_state.msr_host_bndcfgs)
2211 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2212 load_fixmap_gdt(raw_smp_processor_id());
2213 }
2214
2215 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2216 {
2217 preempt_disable();
2218 __vmx_load_host_state(vmx);
2219 preempt_enable();
2220 }
2221
2222 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2223 {
2224 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2225 struct pi_desc old, new;
2226 unsigned int dest;
2227
2228 /*
2229 * In case of hot-plug or hot-unplug, we may have to undo
2230 * vmx_vcpu_pi_put even if there is no assigned device. And we
2231 * always keep PI.NDST up to date for simplicity: it makes the
2232 * code easier, and CPU migration is not a fast path.
2233 */
2234 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
2235 return;
2236
2237 /*
2238 * First handle the simple case where no cmpxchg is necessary; just
2239 * allow posting non-urgent interrupts.
2240 *
2241 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2242 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2243 * expects the VCPU to be on the blocked_vcpu_list that matches
2244 * PI.NDST.
2245 */
2246 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
2247 vcpu->cpu == cpu) {
2248 pi_clear_sn(pi_desc);
2249 return;
2250 }
2251
2252 /* The full case. */
2253 do {
2254 old.control = new.control = pi_desc->control;
2255
2256 dest = cpu_physical_id(cpu);
2257
2258 if (x2apic_enabled())
2259 new.ndst = dest;
2260 else
2261 new.ndst = (dest << 8) & 0xFF00;
2262
2263 new.sn = 0;
2264 } while (cmpxchg64(&pi_desc->control, old.control,
2265 new.control) != old.control);
2266 }
2267
2268 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2269 {
2270 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2271 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2272 }
2273
2274 /*
2275 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2276 * vcpu mutex is already taken.
2277 */
2278 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2279 {
2280 struct vcpu_vmx *vmx = to_vmx(vcpu);
2281 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2282
2283 if (!already_loaded) {
2284 loaded_vmcs_clear(vmx->loaded_vmcs);
2285 local_irq_disable();
2286 crash_disable_local_vmclear(cpu);
2287
2288 /*
2289 * Read loaded_vmcs->cpu should be before fetching
2290 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2291 * See the comments in __loaded_vmcs_clear().
2292 */
2293 smp_rmb();
2294
2295 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2296 &per_cpu(loaded_vmcss_on_cpu, cpu));
2297 crash_enable_local_vmclear(cpu);
2298 local_irq_enable();
2299 }
2300
2301 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2302 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2303 vmcs_load(vmx->loaded_vmcs->vmcs);
2304 indirect_branch_prediction_barrier();
2305 }
2306
2307 if (!already_loaded) {
2308 void *gdt = get_current_gdt_ro();
2309 unsigned long sysenter_esp;
2310
2311 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2312
2313 /*
2314 * Linux uses per-cpu TSS and GDT, so set these when switching
2315 * processors. See 22.2.4.
2316 */
2317 vmcs_writel(HOST_TR_BASE,
2318 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
2319 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
2320
2321 /*
2322 * VM exits change the host TR limit to 0x67 after a VM
2323 * exit. This is okay, since 0x67 covers everything except
2324 * the IO bitmap and have have code to handle the IO bitmap
2325 * being lost after a VM exit.
2326 */
2327 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2328
2329 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2330 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2331
2332 vmx->loaded_vmcs->cpu = cpu;
2333 }
2334
2335 /* Setup TSC multiplier */
2336 if (kvm_has_tsc_control &&
2337 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2338 decache_tsc_multiplier(vmx);
2339
2340 vmx_vcpu_pi_load(vcpu, cpu);
2341 vmx->host_pkru = read_pkru();
2342 vmx->host_debugctlmsr = get_debugctlmsr();
2343 }
2344
2345 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2346 {
2347 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2348
2349 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2350 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2351 !kvm_vcpu_apicv_active(vcpu))
2352 return;
2353
2354 /* Set SN when the vCPU is preempted */
2355 if (vcpu->preempted)
2356 pi_set_sn(pi_desc);
2357 }
2358
2359 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2360 {
2361 vmx_vcpu_pi_put(vcpu);
2362
2363 __vmx_load_host_state(to_vmx(vcpu));
2364 }
2365
2366 static bool emulation_required(struct kvm_vcpu *vcpu)
2367 {
2368 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2369 }
2370
2371 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2372
2373 /*
2374 * Return the cr0 value that a nested guest would read. This is a combination
2375 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2376 * its hypervisor (cr0_read_shadow).
2377 */
2378 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2379 {
2380 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2381 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2382 }
2383 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2384 {
2385 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2386 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2387 }
2388
2389 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2390 {
2391 unsigned long rflags, save_rflags;
2392
2393 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2394 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2395 rflags = vmcs_readl(GUEST_RFLAGS);
2396 if (to_vmx(vcpu)->rmode.vm86_active) {
2397 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2398 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2399 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2400 }
2401 to_vmx(vcpu)->rflags = rflags;
2402 }
2403 return to_vmx(vcpu)->rflags;
2404 }
2405
2406 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2407 {
2408 unsigned long old_rflags = vmx_get_rflags(vcpu);
2409
2410 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2411 to_vmx(vcpu)->rflags = rflags;
2412 if (to_vmx(vcpu)->rmode.vm86_active) {
2413 to_vmx(vcpu)->rmode.save_rflags = rflags;
2414 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2415 }
2416 vmcs_writel(GUEST_RFLAGS, rflags);
2417
2418 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2419 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2420 }
2421
2422 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2423 {
2424 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2425 int ret = 0;
2426
2427 if (interruptibility & GUEST_INTR_STATE_STI)
2428 ret |= KVM_X86_SHADOW_INT_STI;
2429 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2430 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2431
2432 return ret;
2433 }
2434
2435 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2436 {
2437 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2438 u32 interruptibility = interruptibility_old;
2439
2440 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2441
2442 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2443 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2444 else if (mask & KVM_X86_SHADOW_INT_STI)
2445 interruptibility |= GUEST_INTR_STATE_STI;
2446
2447 if ((interruptibility != interruptibility_old))
2448 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2449 }
2450
2451 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2452 {
2453 unsigned long rip;
2454
2455 rip = kvm_rip_read(vcpu);
2456 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2457 kvm_rip_write(vcpu, rip);
2458
2459 /* skipping an emulated instruction also counts */
2460 vmx_set_interrupt_shadow(vcpu, 0);
2461 }
2462
2463 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2464 unsigned long exit_qual)
2465 {
2466 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2467 unsigned int nr = vcpu->arch.exception.nr;
2468 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2469
2470 if (vcpu->arch.exception.has_error_code) {
2471 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2472 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2473 }
2474
2475 if (kvm_exception_is_soft(nr))
2476 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2477 else
2478 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2479
2480 if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2481 vmx_get_nmi_mask(vcpu))
2482 intr_info |= INTR_INFO_UNBLOCK_NMI;
2483
2484 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2485 }
2486
2487 /*
2488 * KVM wants to inject page-faults which it got to the guest. This function
2489 * checks whether in a nested guest, we need to inject them to L1 or L2.
2490 */
2491 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
2492 {
2493 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2494 unsigned int nr = vcpu->arch.exception.nr;
2495
2496 if (nr == PF_VECTOR) {
2497 if (vcpu->arch.exception.nested_apf) {
2498 *exit_qual = vcpu->arch.apf.nested_apf_token;
2499 return 1;
2500 }
2501 /*
2502 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2503 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2504 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2505 * can be written only when inject_pending_event runs. This should be
2506 * conditional on a new capability---if the capability is disabled,
2507 * kvm_multiple_exception would write the ancillary information to
2508 * CR2 or DR6, for backwards ABI-compatibility.
2509 */
2510 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2511 vcpu->arch.exception.error_code)) {
2512 *exit_qual = vcpu->arch.cr2;
2513 return 1;
2514 }
2515 } else {
2516 if (vmcs12->exception_bitmap & (1u << nr)) {
2517 if (nr == DB_VECTOR)
2518 *exit_qual = vcpu->arch.dr6;
2519 else
2520 *exit_qual = 0;
2521 return 1;
2522 }
2523 }
2524
2525 return 0;
2526 }
2527
2528 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2529 {
2530 struct vcpu_vmx *vmx = to_vmx(vcpu);
2531 unsigned nr = vcpu->arch.exception.nr;
2532 bool has_error_code = vcpu->arch.exception.has_error_code;
2533 u32 error_code = vcpu->arch.exception.error_code;
2534 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2535
2536 if (has_error_code) {
2537 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2538 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2539 }
2540
2541 if (vmx->rmode.vm86_active) {
2542 int inc_eip = 0;
2543 if (kvm_exception_is_soft(nr))
2544 inc_eip = vcpu->arch.event_exit_inst_len;
2545 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2546 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2547 return;
2548 }
2549
2550 if (kvm_exception_is_soft(nr)) {
2551 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2552 vmx->vcpu.arch.event_exit_inst_len);
2553 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2554 } else
2555 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2556
2557 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2558 }
2559
2560 static bool vmx_rdtscp_supported(void)
2561 {
2562 return cpu_has_vmx_rdtscp();
2563 }
2564
2565 static bool vmx_invpcid_supported(void)
2566 {
2567 return cpu_has_vmx_invpcid() && enable_ept;
2568 }
2569
2570 /*
2571 * Swap MSR entry in host/guest MSR entry array.
2572 */
2573 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2574 {
2575 struct shared_msr_entry tmp;
2576
2577 tmp = vmx->guest_msrs[to];
2578 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2579 vmx->guest_msrs[from] = tmp;
2580 }
2581
2582 /*
2583 * Set up the vmcs to automatically save and restore system
2584 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2585 * mode, as fiddling with msrs is very expensive.
2586 */
2587 static void setup_msrs(struct vcpu_vmx *vmx)
2588 {
2589 int save_nmsrs, index;
2590
2591 save_nmsrs = 0;
2592 #ifdef CONFIG_X86_64
2593 if (is_long_mode(&vmx->vcpu)) {
2594 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2595 if (index >= 0)
2596 move_msr_up(vmx, index, save_nmsrs++);
2597 index = __find_msr_index(vmx, MSR_LSTAR);
2598 if (index >= 0)
2599 move_msr_up(vmx, index, save_nmsrs++);
2600 index = __find_msr_index(vmx, MSR_CSTAR);
2601 if (index >= 0)
2602 move_msr_up(vmx, index, save_nmsrs++);
2603 index = __find_msr_index(vmx, MSR_TSC_AUX);
2604 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
2605 move_msr_up(vmx, index, save_nmsrs++);
2606 /*
2607 * MSR_STAR is only needed on long mode guests, and only
2608 * if efer.sce is enabled.
2609 */
2610 index = __find_msr_index(vmx, MSR_STAR);
2611 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2612 move_msr_up(vmx, index, save_nmsrs++);
2613 }
2614 #endif
2615 index = __find_msr_index(vmx, MSR_EFER);
2616 if (index >= 0 && update_transition_efer(vmx, index))
2617 move_msr_up(vmx, index, save_nmsrs++);
2618
2619 vmx->save_nmsrs = save_nmsrs;
2620
2621 if (cpu_has_vmx_msr_bitmap())
2622 vmx_update_msr_bitmap(&vmx->vcpu);
2623 }
2624
2625 /*
2626 * reads and returns guest's timestamp counter "register"
2627 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2628 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2629 */
2630 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2631 {
2632 u64 host_tsc, tsc_offset;
2633
2634 host_tsc = rdtsc();
2635 tsc_offset = vmcs_read64(TSC_OFFSET);
2636 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2637 }
2638
2639 /*
2640 * writes 'offset' into guest's timestamp counter offset register
2641 */
2642 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2643 {
2644 if (is_guest_mode(vcpu)) {
2645 /*
2646 * We're here if L1 chose not to trap WRMSR to TSC. According
2647 * to the spec, this should set L1's TSC; The offset that L1
2648 * set for L2 remains unchanged, and still needs to be added
2649 * to the newly set TSC to get L2's TSC.
2650 */
2651 struct vmcs12 *vmcs12;
2652 /* recalculate vmcs02.TSC_OFFSET: */
2653 vmcs12 = get_vmcs12(vcpu);
2654 vmcs_write64(TSC_OFFSET, offset +
2655 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2656 vmcs12->tsc_offset : 0));
2657 } else {
2658 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2659 vmcs_read64(TSC_OFFSET), offset);
2660 vmcs_write64(TSC_OFFSET, offset);
2661 }
2662 }
2663
2664 /*
2665 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2666 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2667 * all guests if the "nested" module option is off, and can also be disabled
2668 * for a single guest by disabling its VMX cpuid bit.
2669 */
2670 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2671 {
2672 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
2673 }
2674
2675 /*
2676 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2677 * returned for the various VMX controls MSRs when nested VMX is enabled.
2678 * The same values should also be used to verify that vmcs12 control fields are
2679 * valid during nested entry from L1 to L2.
2680 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2681 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2682 * bit in the high half is on if the corresponding bit in the control field
2683 * may be on. See also vmx_control_verify().
2684 */
2685 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2686 {
2687 /*
2688 * Note that as a general rule, the high half of the MSRs (bits in
2689 * the control fields which may be 1) should be initialized by the
2690 * intersection of the underlying hardware's MSR (i.e., features which
2691 * can be supported) and the list of features we want to expose -
2692 * because they are known to be properly supported in our code.
2693 * Also, usually, the low half of the MSRs (bits which must be 1) can
2694 * be set to 0, meaning that L1 may turn off any of these bits. The
2695 * reason is that if one of these bits is necessary, it will appear
2696 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2697 * fields of vmcs01 and vmcs02, will turn these bits off - and
2698 * nested_vmx_exit_reflected() will not pass related exits to L1.
2699 * These rules have exceptions below.
2700 */
2701
2702 /* pin-based controls */
2703 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2704 vmx->nested.nested_vmx_pinbased_ctls_low,
2705 vmx->nested.nested_vmx_pinbased_ctls_high);
2706 vmx->nested.nested_vmx_pinbased_ctls_low |=
2707 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2708 vmx->nested.nested_vmx_pinbased_ctls_high &=
2709 PIN_BASED_EXT_INTR_MASK |
2710 PIN_BASED_NMI_EXITING |
2711 PIN_BASED_VIRTUAL_NMIS;
2712 vmx->nested.nested_vmx_pinbased_ctls_high |=
2713 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2714 PIN_BASED_VMX_PREEMPTION_TIMER;
2715 if (kvm_vcpu_apicv_active(&vmx->vcpu))
2716 vmx->nested.nested_vmx_pinbased_ctls_high |=
2717 PIN_BASED_POSTED_INTR;
2718
2719 /* exit controls */
2720 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2721 vmx->nested.nested_vmx_exit_ctls_low,
2722 vmx->nested.nested_vmx_exit_ctls_high);
2723 vmx->nested.nested_vmx_exit_ctls_low =
2724 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2725
2726 vmx->nested.nested_vmx_exit_ctls_high &=
2727 #ifdef CONFIG_X86_64
2728 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2729 #endif
2730 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2731 vmx->nested.nested_vmx_exit_ctls_high |=
2732 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2733 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2734 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2735
2736 if (kvm_mpx_supported())
2737 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2738
2739 /* We support free control of debug control saving. */
2740 vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2741
2742 /* entry controls */
2743 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2744 vmx->nested.nested_vmx_entry_ctls_low,
2745 vmx->nested.nested_vmx_entry_ctls_high);
2746 vmx->nested.nested_vmx_entry_ctls_low =
2747 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2748 vmx->nested.nested_vmx_entry_ctls_high &=
2749 #ifdef CONFIG_X86_64
2750 VM_ENTRY_IA32E_MODE |
2751 #endif
2752 VM_ENTRY_LOAD_IA32_PAT;
2753 vmx->nested.nested_vmx_entry_ctls_high |=
2754 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2755 if (kvm_mpx_supported())
2756 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2757
2758 /* We support free control of debug control loading. */
2759 vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2760
2761 /* cpu-based controls */
2762 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2763 vmx->nested.nested_vmx_procbased_ctls_low,
2764 vmx->nested.nested_vmx_procbased_ctls_high);
2765 vmx->nested.nested_vmx_procbased_ctls_low =
2766 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2767 vmx->nested.nested_vmx_procbased_ctls_high &=
2768 CPU_BASED_VIRTUAL_INTR_PENDING |
2769 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2770 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2771 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2772 CPU_BASED_CR3_STORE_EXITING |
2773 #ifdef CONFIG_X86_64
2774 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2775 #endif
2776 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2777 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2778 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2779 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2780 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2781 /*
2782 * We can allow some features even when not supported by the
2783 * hardware. For example, L1 can specify an MSR bitmap - and we
2784 * can use it to avoid exits to L1 - even when L0 runs L2
2785 * without MSR bitmaps.
2786 */
2787 vmx->nested.nested_vmx_procbased_ctls_high |=
2788 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2789 CPU_BASED_USE_MSR_BITMAPS;
2790
2791 /* We support free control of CR3 access interception. */
2792 vmx->nested.nested_vmx_procbased_ctls_low &=
2793 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2794
2795 /*
2796 * secondary cpu-based controls. Do not include those that
2797 * depend on CPUID bits, they are added later by vmx_cpuid_update.
2798 */
2799 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2800 vmx->nested.nested_vmx_secondary_ctls_low,
2801 vmx->nested.nested_vmx_secondary_ctls_high);
2802 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2803 vmx->nested.nested_vmx_secondary_ctls_high &=
2804 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2805 SECONDARY_EXEC_DESC |
2806 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2807 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2808 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2809 SECONDARY_EXEC_WBINVD_EXITING;
2810
2811 if (enable_ept) {
2812 /* nested EPT: emulate EPT also to L1 */
2813 vmx->nested.nested_vmx_secondary_ctls_high |=
2814 SECONDARY_EXEC_ENABLE_EPT;
2815 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2816 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2817 if (cpu_has_vmx_ept_execute_only())
2818 vmx->nested.nested_vmx_ept_caps |=
2819 VMX_EPT_EXECUTE_ONLY_BIT;
2820 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2821 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2822 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2823 VMX_EPT_1GB_PAGE_BIT;
2824 if (enable_ept_ad_bits) {
2825 vmx->nested.nested_vmx_secondary_ctls_high |=
2826 SECONDARY_EXEC_ENABLE_PML;
2827 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2828 }
2829 }
2830
2831 if (cpu_has_vmx_vmfunc()) {
2832 vmx->nested.nested_vmx_secondary_ctls_high |=
2833 SECONDARY_EXEC_ENABLE_VMFUNC;
2834 /*
2835 * Advertise EPTP switching unconditionally
2836 * since we emulate it
2837 */
2838 if (enable_ept)
2839 vmx->nested.nested_vmx_vmfunc_controls =
2840 VMX_VMFUNC_EPTP_SWITCHING;
2841 }
2842
2843 /*
2844 * Old versions of KVM use the single-context version without
2845 * checking for support, so declare that it is supported even
2846 * though it is treated as global context. The alternative is
2847 * not failing the single-context invvpid, and it is worse.
2848 */
2849 if (enable_vpid) {
2850 vmx->nested.nested_vmx_secondary_ctls_high |=
2851 SECONDARY_EXEC_ENABLE_VPID;
2852 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2853 VMX_VPID_EXTENT_SUPPORTED_MASK;
2854 }
2855
2856 if (enable_unrestricted_guest)
2857 vmx->nested.nested_vmx_secondary_ctls_high |=
2858 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2859
2860 /* miscellaneous data */
2861 rdmsr(MSR_IA32_VMX_MISC,
2862 vmx->nested.nested_vmx_misc_low,
2863 vmx->nested.nested_vmx_misc_high);
2864 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2865 vmx->nested.nested_vmx_misc_low |=
2866 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2867 VMX_MISC_ACTIVITY_HLT;
2868 vmx->nested.nested_vmx_misc_high = 0;
2869
2870 /*
2871 * This MSR reports some information about VMX support. We
2872 * should return information about the VMX we emulate for the
2873 * guest, and the VMCS structure we give it - not about the
2874 * VMX support of the underlying hardware.
2875 */
2876 vmx->nested.nested_vmx_basic =
2877 VMCS12_REVISION |
2878 VMX_BASIC_TRUE_CTLS |
2879 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2880 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2881
2882 if (cpu_has_vmx_basic_inout())
2883 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2884
2885 /*
2886 * These MSRs specify bits which the guest must keep fixed on
2887 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2888 * We picked the standard core2 setting.
2889 */
2890 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2891 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2892 vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2893 vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2894
2895 /* These MSRs specify bits which the guest must keep fixed off. */
2896 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2897 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2898
2899 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2900 vmx->nested.nested_vmx_vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1;
2901 }
2902
2903 /*
2904 * if fixed0[i] == 1: val[i] must be 1
2905 * if fixed1[i] == 0: val[i] must be 0
2906 */
2907 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2908 {
2909 return ((val & fixed1) | fixed0) == val;
2910 }
2911
2912 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2913 {
2914 return fixed_bits_valid(control, low, high);
2915 }
2916
2917 static inline u64 vmx_control_msr(u32 low, u32 high)
2918 {
2919 return low | ((u64)high << 32);
2920 }
2921
2922 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2923 {
2924 superset &= mask;
2925 subset &= mask;
2926
2927 return (superset | subset) == superset;
2928 }
2929
2930 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2931 {
2932 const u64 feature_and_reserved =
2933 /* feature (except bit 48; see below) */
2934 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2935 /* reserved */
2936 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2937 u64 vmx_basic = vmx->nested.nested_vmx_basic;
2938
2939 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2940 return -EINVAL;
2941
2942 /*
2943 * KVM does not emulate a version of VMX that constrains physical
2944 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2945 */
2946 if (data & BIT_ULL(48))
2947 return -EINVAL;
2948
2949 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2950 vmx_basic_vmcs_revision_id(data))
2951 return -EINVAL;
2952
2953 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2954 return -EINVAL;
2955
2956 vmx->nested.nested_vmx_basic = data;
2957 return 0;
2958 }
2959
2960 static int
2961 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2962 {
2963 u64 supported;
2964 u32 *lowp, *highp;
2965
2966 switch (msr_index) {
2967 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2968 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2969 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2970 break;
2971 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2972 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2973 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2974 break;
2975 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2976 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2977 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2978 break;
2979 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2980 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2981 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2982 break;
2983 case MSR_IA32_VMX_PROCBASED_CTLS2:
2984 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2985 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2986 break;
2987 default:
2988 BUG();
2989 }
2990
2991 supported = vmx_control_msr(*lowp, *highp);
2992
2993 /* Check must-be-1 bits are still 1. */
2994 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2995 return -EINVAL;
2996
2997 /* Check must-be-0 bits are still 0. */
2998 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2999 return -EINVAL;
3000
3001 *lowp = data;
3002 *highp = data >> 32;
3003 return 0;
3004 }
3005
3006 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3007 {
3008 const u64 feature_and_reserved_bits =
3009 /* feature */
3010 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3011 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3012 /* reserved */
3013 GENMASK_ULL(13, 9) | BIT_ULL(31);
3014 u64 vmx_misc;
3015
3016 vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
3017 vmx->nested.nested_vmx_misc_high);
3018
3019 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3020 return -EINVAL;
3021
3022 if ((vmx->nested.nested_vmx_pinbased_ctls_high &
3023 PIN_BASED_VMX_PREEMPTION_TIMER) &&
3024 vmx_misc_preemption_timer_rate(data) !=
3025 vmx_misc_preemption_timer_rate(vmx_misc))
3026 return -EINVAL;
3027
3028 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3029 return -EINVAL;
3030
3031 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3032 return -EINVAL;
3033
3034 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3035 return -EINVAL;
3036
3037 vmx->nested.nested_vmx_misc_low = data;
3038 vmx->nested.nested_vmx_misc_high = data >> 32;
3039 return 0;
3040 }
3041
3042 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3043 {
3044 u64 vmx_ept_vpid_cap;
3045
3046 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3047 vmx->nested.nested_vmx_vpid_caps);
3048
3049 /* Every bit is either reserved or a feature bit. */
3050 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3051 return -EINVAL;
3052
3053 vmx->nested.nested_vmx_ept_caps = data;
3054 vmx->nested.nested_vmx_vpid_caps = data >> 32;
3055 return 0;
3056 }
3057
3058 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3059 {
3060 u64 *msr;
3061
3062 switch (msr_index) {
3063 case MSR_IA32_VMX_CR0_FIXED0:
3064 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3065 break;
3066 case MSR_IA32_VMX_CR4_FIXED0:
3067 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3068 break;
3069 default:
3070 BUG();
3071 }
3072
3073 /*
3074 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3075 * must be 1 in the restored value.
3076 */
3077 if (!is_bitwise_subset(data, *msr, -1ULL))
3078 return -EINVAL;
3079
3080 *msr = data;
3081 return 0;
3082 }
3083
3084 /*
3085 * Called when userspace is restoring VMX MSRs.
3086 *
3087 * Returns 0 on success, non-0 otherwise.
3088 */
3089 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3090 {
3091 struct vcpu_vmx *vmx = to_vmx(vcpu);
3092
3093 switch (msr_index) {
3094 case MSR_IA32_VMX_BASIC:
3095 return vmx_restore_vmx_basic(vmx, data);
3096 case MSR_IA32_VMX_PINBASED_CTLS:
3097 case MSR_IA32_VMX_PROCBASED_CTLS:
3098 case MSR_IA32_VMX_EXIT_CTLS:
3099 case MSR_IA32_VMX_ENTRY_CTLS:
3100 /*
3101 * The "non-true" VMX capability MSRs are generated from the
3102 * "true" MSRs, so we do not support restoring them directly.
3103 *
3104 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3105 * should restore the "true" MSRs with the must-be-1 bits
3106 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3107 * DEFAULT SETTINGS".
3108 */
3109 return -EINVAL;
3110 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3111 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3112 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3113 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3114 case MSR_IA32_VMX_PROCBASED_CTLS2:
3115 return vmx_restore_control_msr(vmx, msr_index, data);
3116 case MSR_IA32_VMX_MISC:
3117 return vmx_restore_vmx_misc(vmx, data);
3118 case MSR_IA32_VMX_CR0_FIXED0:
3119 case MSR_IA32_VMX_CR4_FIXED0:
3120 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3121 case MSR_IA32_VMX_CR0_FIXED1:
3122 case MSR_IA32_VMX_CR4_FIXED1:
3123 /*
3124 * These MSRs are generated based on the vCPU's CPUID, so we
3125 * do not support restoring them directly.
3126 */
3127 return -EINVAL;
3128 case MSR_IA32_VMX_EPT_VPID_CAP:
3129 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3130 case MSR_IA32_VMX_VMCS_ENUM:
3131 vmx->nested.nested_vmx_vmcs_enum = data;
3132 return 0;
3133 default:
3134 /*
3135 * The rest of the VMX capability MSRs do not support restore.
3136 */
3137 return -EINVAL;
3138 }
3139 }
3140
3141 /* Returns 0 on success, non-0 otherwise. */
3142 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3143 {
3144 struct vcpu_vmx *vmx = to_vmx(vcpu);
3145
3146 switch (msr_index) {
3147 case MSR_IA32_VMX_BASIC:
3148 *pdata = vmx->nested.nested_vmx_basic;
3149 break;
3150 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3151 case MSR_IA32_VMX_PINBASED_CTLS:
3152 *pdata = vmx_control_msr(
3153 vmx->nested.nested_vmx_pinbased_ctls_low,
3154 vmx->nested.nested_vmx_pinbased_ctls_high);
3155 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3156 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3157 break;
3158 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3159 case MSR_IA32_VMX_PROCBASED_CTLS:
3160 *pdata = vmx_control_msr(
3161 vmx->nested.nested_vmx_procbased_ctls_low,
3162 vmx->nested.nested_vmx_procbased_ctls_high);
3163 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3164 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3165 break;
3166 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3167 case MSR_IA32_VMX_EXIT_CTLS:
3168 *pdata = vmx_control_msr(
3169 vmx->nested.nested_vmx_exit_ctls_low,
3170 vmx->nested.nested_vmx_exit_ctls_high);
3171 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3172 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3173 break;
3174 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3175 case MSR_IA32_VMX_ENTRY_CTLS:
3176 *pdata = vmx_control_msr(
3177 vmx->nested.nested_vmx_entry_ctls_low,
3178 vmx->nested.nested_vmx_entry_ctls_high);
3179 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3180 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3181 break;
3182 case MSR_IA32_VMX_MISC:
3183 *pdata = vmx_control_msr(
3184 vmx->nested.nested_vmx_misc_low,
3185 vmx->nested.nested_vmx_misc_high);
3186 break;
3187 case MSR_IA32_VMX_CR0_FIXED0:
3188 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3189 break;
3190 case MSR_IA32_VMX_CR0_FIXED1:
3191 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3192 break;
3193 case MSR_IA32_VMX_CR4_FIXED0:
3194 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3195 break;
3196 case MSR_IA32_VMX_CR4_FIXED1:
3197 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3198 break;
3199 case MSR_IA32_VMX_VMCS_ENUM:
3200 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3201 break;
3202 case MSR_IA32_VMX_PROCBASED_CTLS2:
3203 *pdata = vmx_control_msr(
3204 vmx->nested.nested_vmx_secondary_ctls_low,
3205 vmx->nested.nested_vmx_secondary_ctls_high);
3206 break;
3207 case MSR_IA32_VMX_EPT_VPID_CAP:
3208 *pdata = vmx->nested.nested_vmx_ept_caps |
3209 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3210 break;
3211 case MSR_IA32_VMX_VMFUNC:
3212 *pdata = vmx->nested.nested_vmx_vmfunc_controls;
3213 break;
3214 default:
3215 return 1;
3216 }
3217
3218 return 0;
3219 }
3220
3221 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3222 uint64_t val)
3223 {
3224 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3225
3226 return !(val & ~valid_bits);
3227 }
3228
3229 /*
3230 * Reads an msr value (of 'msr_index') into 'pdata'.
3231 * Returns 0 on success, non-0 otherwise.
3232 * Assumes vcpu_load() was already called.
3233 */
3234 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3235 {
3236 struct vcpu_vmx *vmx = to_vmx(vcpu);
3237 struct shared_msr_entry *msr;
3238
3239 switch (msr_info->index) {
3240 #ifdef CONFIG_X86_64
3241 case MSR_FS_BASE:
3242 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3243 break;
3244 case MSR_GS_BASE:
3245 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3246 break;
3247 case MSR_KERNEL_GS_BASE:
3248 vmx_load_host_state(vmx);
3249 msr_info->data = vmx->msr_guest_kernel_gs_base;
3250 break;
3251 #endif
3252 case MSR_EFER:
3253 return kvm_get_msr_common(vcpu, msr_info);
3254 case MSR_IA32_TSC:
3255 msr_info->data = guest_read_tsc(vcpu);
3256 break;
3257 case MSR_IA32_SPEC_CTRL:
3258 if (!msr_info->host_initiated &&
3259 !guest_cpuid_has(vcpu, X86_FEATURE_IBRS) &&
3260 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3261 return 1;
3262
3263 msr_info->data = to_vmx(vcpu)->spec_ctrl;
3264 break;
3265 case MSR_IA32_ARCH_CAPABILITIES:
3266 if (!msr_info->host_initiated &&
3267 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3268 return 1;
3269 msr_info->data = to_vmx(vcpu)->arch_capabilities;
3270 break;
3271 case MSR_IA32_SYSENTER_CS:
3272 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3273 break;
3274 case MSR_IA32_SYSENTER_EIP:
3275 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3276 break;
3277 case MSR_IA32_SYSENTER_ESP:
3278 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3279 break;
3280 case MSR_IA32_BNDCFGS:
3281 if (!kvm_mpx_supported() ||
3282 (!msr_info->host_initiated &&
3283 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3284 return 1;
3285 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3286 break;
3287 case MSR_IA32_MCG_EXT_CTL:
3288 if (!msr_info->host_initiated &&
3289 !(vmx->msr_ia32_feature_control &
3290 FEATURE_CONTROL_LMCE))
3291 return 1;
3292 msr_info->data = vcpu->arch.mcg_ext_ctl;
3293 break;
3294 case MSR_IA32_FEATURE_CONTROL:
3295 msr_info->data = vmx->msr_ia32_feature_control;
3296 break;
3297 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3298 if (!nested_vmx_allowed(vcpu))
3299 return 1;
3300 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3301 case MSR_IA32_XSS:
3302 if (!vmx_xsaves_supported())
3303 return 1;
3304 msr_info->data = vcpu->arch.ia32_xss;
3305 break;
3306 case MSR_TSC_AUX:
3307 if (!msr_info->host_initiated &&
3308 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3309 return 1;
3310 /* Otherwise falls through */
3311 default:
3312 msr = find_msr_entry(vmx, msr_info->index);
3313 if (msr) {
3314 msr_info->data = msr->data;
3315 break;
3316 }
3317 return kvm_get_msr_common(vcpu, msr_info);
3318 }
3319
3320 return 0;
3321 }
3322
3323 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3324
3325 /*
3326 * Writes msr value into into the appropriate "register".
3327 * Returns 0 on success, non-0 otherwise.
3328 * Assumes vcpu_load() was already called.
3329 */
3330 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3331 {
3332 struct vcpu_vmx *vmx = to_vmx(vcpu);
3333 struct shared_msr_entry *msr;
3334 int ret = 0;
3335 u32 msr_index = msr_info->index;
3336 u64 data = msr_info->data;
3337
3338 switch (msr_index) {
3339 case MSR_EFER:
3340 ret = kvm_set_msr_common(vcpu, msr_info);
3341 break;
3342 #ifdef CONFIG_X86_64
3343 case MSR_FS_BASE:
3344 vmx_segment_cache_clear(vmx);
3345 vmcs_writel(GUEST_FS_BASE, data);
3346 break;
3347 case MSR_GS_BASE:
3348 vmx_segment_cache_clear(vmx);
3349 vmcs_writel(GUEST_GS_BASE, data);
3350 break;
3351 case MSR_KERNEL_GS_BASE:
3352 vmx_load_host_state(vmx);
3353 vmx->msr_guest_kernel_gs_base = data;
3354 break;
3355 #endif
3356 case MSR_IA32_SYSENTER_CS:
3357 vmcs_write32(GUEST_SYSENTER_CS, data);
3358 break;
3359 case MSR_IA32_SYSENTER_EIP:
3360 vmcs_writel(GUEST_SYSENTER_EIP, data);
3361 break;
3362 case MSR_IA32_SYSENTER_ESP:
3363 vmcs_writel(GUEST_SYSENTER_ESP, data);
3364 break;
3365 case MSR_IA32_BNDCFGS:
3366 if (!kvm_mpx_supported() ||
3367 (!msr_info->host_initiated &&
3368 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3369 return 1;
3370 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
3371 (data & MSR_IA32_BNDCFGS_RSVD))
3372 return 1;
3373 vmcs_write64(GUEST_BNDCFGS, data);
3374 break;
3375 case MSR_IA32_TSC:
3376 kvm_write_tsc(vcpu, msr_info);
3377 break;
3378 case MSR_IA32_SPEC_CTRL:
3379 if (!msr_info->host_initiated &&
3380 !guest_cpuid_has(vcpu, X86_FEATURE_IBRS) &&
3381 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3382 return 1;
3383
3384 /* The STIBP bit doesn't fault even if it's not advertised */
3385 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP))
3386 return 1;
3387
3388 vmx->spec_ctrl = data;
3389
3390 if (!data)
3391 break;
3392
3393 /*
3394 * For non-nested:
3395 * When it's written (to non-zero) for the first time, pass
3396 * it through.
3397 *
3398 * For nested:
3399 * The handling of the MSR bitmap for L2 guests is done in
3400 * nested_vmx_merge_msr_bitmap. We should not touch the
3401 * vmcs02.msr_bitmap here since it gets completely overwritten
3402 * in the merging. We update the vmcs01 here for L1 as well
3403 * since it will end up touching the MSR anyway now.
3404 */
3405 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
3406 MSR_IA32_SPEC_CTRL,
3407 MSR_TYPE_RW);
3408 break;
3409 case MSR_IA32_PRED_CMD:
3410 if (!msr_info->host_initiated &&
3411 !guest_cpuid_has(vcpu, X86_FEATURE_IBPB) &&
3412 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3413 return 1;
3414
3415 if (data & ~PRED_CMD_IBPB)
3416 return 1;
3417
3418 if (!data)
3419 break;
3420
3421 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
3422
3423 /*
3424 * For non-nested:
3425 * When it's written (to non-zero) for the first time, pass
3426 * it through.
3427 *
3428 * For nested:
3429 * The handling of the MSR bitmap for L2 guests is done in
3430 * nested_vmx_merge_msr_bitmap. We should not touch the
3431 * vmcs02.msr_bitmap here since it gets completely overwritten
3432 * in the merging.
3433 */
3434 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
3435 MSR_TYPE_W);
3436 break;
3437 case MSR_IA32_ARCH_CAPABILITIES:
3438 if (!msr_info->host_initiated)
3439 return 1;
3440 vmx->arch_capabilities = data;
3441 break;
3442 case MSR_IA32_CR_PAT:
3443 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3444 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3445 return 1;
3446 vmcs_write64(GUEST_IA32_PAT, data);
3447 vcpu->arch.pat = data;
3448 break;
3449 }
3450 ret = kvm_set_msr_common(vcpu, msr_info);
3451 break;
3452 case MSR_IA32_TSC_ADJUST:
3453 ret = kvm_set_msr_common(vcpu, msr_info);
3454 break;
3455 case MSR_IA32_MCG_EXT_CTL:
3456 if ((!msr_info->host_initiated &&
3457 !(to_vmx(vcpu)->msr_ia32_feature_control &
3458 FEATURE_CONTROL_LMCE)) ||
3459 (data & ~MCG_EXT_CTL_LMCE_EN))
3460 return 1;
3461 vcpu->arch.mcg_ext_ctl = data;
3462 break;
3463 case MSR_IA32_FEATURE_CONTROL:
3464 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3465 (to_vmx(vcpu)->msr_ia32_feature_control &
3466 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3467 return 1;
3468 vmx->msr_ia32_feature_control = data;
3469 if (msr_info->host_initiated && data == 0)
3470 vmx_leave_nested(vcpu);
3471 break;
3472 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3473 if (!msr_info->host_initiated)
3474 return 1; /* they are read-only */
3475 if (!nested_vmx_allowed(vcpu))
3476 return 1;
3477 return vmx_set_vmx_msr(vcpu, msr_index, data);
3478 case MSR_IA32_XSS:
3479 if (!vmx_xsaves_supported())
3480 return 1;
3481 /*
3482 * The only supported bit as of Skylake is bit 8, but
3483 * it is not supported on KVM.
3484 */
3485 if (data != 0)
3486 return 1;
3487 vcpu->arch.ia32_xss = data;
3488 if (vcpu->arch.ia32_xss != host_xss)
3489 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3490 vcpu->arch.ia32_xss, host_xss);
3491 else
3492 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3493 break;
3494 case MSR_TSC_AUX:
3495 if (!msr_info->host_initiated &&
3496 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3497 return 1;
3498 /* Check reserved bit, higher 32 bits should be zero */
3499 if ((data >> 32) != 0)
3500 return 1;
3501 /* Otherwise falls through */
3502 default:
3503 msr = find_msr_entry(vmx, msr_index);
3504 if (msr) {
3505 u64 old_msr_data = msr->data;
3506 msr->data = data;
3507 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3508 preempt_disable();
3509 ret = kvm_set_shared_msr(msr->index, msr->data,
3510 msr->mask);
3511 preempt_enable();
3512 if (ret)
3513 msr->data = old_msr_data;
3514 }
3515 break;
3516 }
3517 ret = kvm_set_msr_common(vcpu, msr_info);
3518 }
3519
3520 return ret;
3521 }
3522
3523 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3524 {
3525 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3526 switch (reg) {
3527 case VCPU_REGS_RSP:
3528 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3529 break;
3530 case VCPU_REGS_RIP:
3531 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3532 break;
3533 case VCPU_EXREG_PDPTR:
3534 if (enable_ept)
3535 ept_save_pdptrs(vcpu);
3536 break;
3537 default:
3538 break;
3539 }
3540 }
3541
3542 static __init int cpu_has_kvm_support(void)
3543 {
3544 return cpu_has_vmx();
3545 }
3546
3547 static __init int vmx_disabled_by_bios(void)
3548 {
3549 u64 msr;
3550
3551 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3552 if (msr & FEATURE_CONTROL_LOCKED) {
3553 /* launched w/ TXT and VMX disabled */
3554 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3555 && tboot_enabled())
3556 return 1;
3557 /* launched w/o TXT and VMX only enabled w/ TXT */
3558 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3559 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3560 && !tboot_enabled()) {
3561 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3562 "activate TXT before enabling KVM\n");
3563 return 1;
3564 }
3565 /* launched w/o TXT and VMX disabled */
3566 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3567 && !tboot_enabled())
3568 return 1;
3569 }
3570
3571 return 0;
3572 }
3573
3574 static void kvm_cpu_vmxon(u64 addr)
3575 {
3576 cr4_set_bits(X86_CR4_VMXE);
3577 intel_pt_handle_vmx(1);
3578
3579 asm volatile (ASM_VMX_VMXON_RAX
3580 : : "a"(&addr), "m"(addr)
3581 : "memory", "cc");
3582 }
3583
3584 static int hardware_enable(void)
3585 {
3586 int cpu = raw_smp_processor_id();
3587 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3588 u64 old, test_bits;
3589
3590 if (cr4_read_shadow() & X86_CR4_VMXE)
3591 return -EBUSY;
3592
3593 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3594 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3595 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3596
3597 /*
3598 * Now we can enable the vmclear operation in kdump
3599 * since the loaded_vmcss_on_cpu list on this cpu
3600 * has been initialized.
3601 *
3602 * Though the cpu is not in VMX operation now, there
3603 * is no problem to enable the vmclear operation
3604 * for the loaded_vmcss_on_cpu list is empty!
3605 */
3606 crash_enable_local_vmclear(cpu);
3607
3608 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3609
3610 test_bits = FEATURE_CONTROL_LOCKED;
3611 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3612 if (tboot_enabled())
3613 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3614
3615 if ((old & test_bits) != test_bits) {
3616 /* enable and lock */
3617 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3618 }
3619 kvm_cpu_vmxon(phys_addr);
3620 if (enable_ept)
3621 ept_sync_global();
3622
3623 return 0;
3624 }
3625
3626 static void vmclear_local_loaded_vmcss(void)
3627 {
3628 int cpu = raw_smp_processor_id();
3629 struct loaded_vmcs *v, *n;
3630
3631 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3632 loaded_vmcss_on_cpu_link)
3633 __loaded_vmcs_clear(v);
3634 }
3635
3636
3637 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3638 * tricks.
3639 */
3640 static void kvm_cpu_vmxoff(void)
3641 {
3642 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3643
3644 intel_pt_handle_vmx(0);
3645 cr4_clear_bits(X86_CR4_VMXE);
3646 }
3647
3648 static void hardware_disable(void)
3649 {
3650 vmclear_local_loaded_vmcss();
3651 kvm_cpu_vmxoff();
3652 }
3653
3654 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3655 u32 msr, u32 *result)
3656 {
3657 u32 vmx_msr_low, vmx_msr_high;
3658 u32 ctl = ctl_min | ctl_opt;
3659
3660 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3661
3662 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3663 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3664
3665 /* Ensure minimum (required) set of control bits are supported. */
3666 if (ctl_min & ~ctl)
3667 return -EIO;
3668
3669 *result = ctl;
3670 return 0;
3671 }
3672
3673 static __init bool allow_1_setting(u32 msr, u32 ctl)
3674 {
3675 u32 vmx_msr_low, vmx_msr_high;
3676
3677 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3678 return vmx_msr_high & ctl;
3679 }
3680
3681 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3682 {
3683 u32 vmx_msr_low, vmx_msr_high;
3684 u32 min, opt, min2, opt2;
3685 u32 _pin_based_exec_control = 0;
3686 u32 _cpu_based_exec_control = 0;
3687 u32 _cpu_based_2nd_exec_control = 0;
3688 u32 _vmexit_control = 0;
3689 u32 _vmentry_control = 0;
3690
3691 min = CPU_BASED_HLT_EXITING |
3692 #ifdef CONFIG_X86_64
3693 CPU_BASED_CR8_LOAD_EXITING |
3694 CPU_BASED_CR8_STORE_EXITING |
3695 #endif
3696 CPU_BASED_CR3_LOAD_EXITING |
3697 CPU_BASED_CR3_STORE_EXITING |
3698 CPU_BASED_UNCOND_IO_EXITING |
3699 CPU_BASED_MOV_DR_EXITING |
3700 CPU_BASED_USE_TSC_OFFSETING |
3701 CPU_BASED_INVLPG_EXITING |
3702 CPU_BASED_RDPMC_EXITING;
3703
3704 if (!kvm_mwait_in_guest())
3705 min |= CPU_BASED_MWAIT_EXITING |
3706 CPU_BASED_MONITOR_EXITING;
3707
3708 opt = CPU_BASED_TPR_SHADOW |
3709 CPU_BASED_USE_MSR_BITMAPS |
3710 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3711 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3712 &_cpu_based_exec_control) < 0)
3713 return -EIO;
3714 #ifdef CONFIG_X86_64
3715 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3716 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3717 ~CPU_BASED_CR8_STORE_EXITING;
3718 #endif
3719 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3720 min2 = 0;
3721 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3722 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3723 SECONDARY_EXEC_WBINVD_EXITING |
3724 SECONDARY_EXEC_ENABLE_VPID |
3725 SECONDARY_EXEC_ENABLE_EPT |
3726 SECONDARY_EXEC_UNRESTRICTED_GUEST |
3727 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3728 SECONDARY_EXEC_DESC |
3729 SECONDARY_EXEC_RDTSCP |
3730 SECONDARY_EXEC_ENABLE_INVPCID |
3731 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3732 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3733 SECONDARY_EXEC_SHADOW_VMCS |
3734 SECONDARY_EXEC_XSAVES |
3735 SECONDARY_EXEC_RDSEED_EXITING |
3736 SECONDARY_EXEC_RDRAND_EXITING |
3737 SECONDARY_EXEC_ENABLE_PML |
3738 SECONDARY_EXEC_TSC_SCALING |
3739 SECONDARY_EXEC_ENABLE_VMFUNC;
3740 if (adjust_vmx_controls(min2, opt2,
3741 MSR_IA32_VMX_PROCBASED_CTLS2,
3742 &_cpu_based_2nd_exec_control) < 0)
3743 return -EIO;
3744 }
3745 #ifndef CONFIG_X86_64
3746 if (!(_cpu_based_2nd_exec_control &
3747 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3748 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3749 #endif
3750
3751 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3752 _cpu_based_2nd_exec_control &= ~(
3753 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3754 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3755 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3756
3757 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
3758 &vmx_capability.ept, &vmx_capability.vpid);
3759
3760 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3761 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3762 enabled */
3763 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3764 CPU_BASED_CR3_STORE_EXITING |
3765 CPU_BASED_INVLPG_EXITING);
3766 } else if (vmx_capability.ept) {
3767 vmx_capability.ept = 0;
3768 pr_warn_once("EPT CAP should not exist if not support "
3769 "1-setting enable EPT VM-execution control\n");
3770 }
3771 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
3772 vmx_capability.vpid) {
3773 vmx_capability.vpid = 0;
3774 pr_warn_once("VPID CAP should not exist if not support "
3775 "1-setting enable VPID VM-execution control\n");
3776 }
3777
3778 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3779 #ifdef CONFIG_X86_64
3780 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3781 #endif
3782 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3783 VM_EXIT_CLEAR_BNDCFGS;
3784 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3785 &_vmexit_control) < 0)
3786 return -EIO;
3787
3788 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3789 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3790 PIN_BASED_VMX_PREEMPTION_TIMER;
3791 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3792 &_pin_based_exec_control) < 0)
3793 return -EIO;
3794
3795 if (cpu_has_broken_vmx_preemption_timer())
3796 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3797 if (!(_cpu_based_2nd_exec_control &
3798 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3799 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3800
3801 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3802 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3803 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3804 &_vmentry_control) < 0)
3805 return -EIO;
3806
3807 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3808
3809 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3810 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3811 return -EIO;
3812
3813 #ifdef CONFIG_X86_64
3814 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3815 if (vmx_msr_high & (1u<<16))
3816 return -EIO;
3817 #endif
3818
3819 /* Require Write-Back (WB) memory type for VMCS accesses. */
3820 if (((vmx_msr_high >> 18) & 15) != 6)
3821 return -EIO;
3822
3823 vmcs_conf->size = vmx_msr_high & 0x1fff;
3824 vmcs_conf->order = get_order(vmcs_conf->size);
3825 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3826 vmcs_conf->revision_id = vmx_msr_low;
3827
3828 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3829 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3830 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3831 vmcs_conf->vmexit_ctrl = _vmexit_control;
3832 vmcs_conf->vmentry_ctrl = _vmentry_control;
3833
3834 cpu_has_load_ia32_efer =
3835 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3836 VM_ENTRY_LOAD_IA32_EFER)
3837 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3838 VM_EXIT_LOAD_IA32_EFER);
3839
3840 cpu_has_load_perf_global_ctrl =
3841 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3842 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3843 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3844 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3845
3846 /*
3847 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3848 * but due to errata below it can't be used. Workaround is to use
3849 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3850 *
3851 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3852 *
3853 * AAK155 (model 26)
3854 * AAP115 (model 30)
3855 * AAT100 (model 37)
3856 * BC86,AAY89,BD102 (model 44)
3857 * BA97 (model 46)
3858 *
3859 */
3860 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3861 switch (boot_cpu_data.x86_model) {
3862 case 26:
3863 case 30:
3864 case 37:
3865 case 44:
3866 case 46:
3867 cpu_has_load_perf_global_ctrl = false;
3868 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3869 "does not work properly. Using workaround\n");
3870 break;
3871 default:
3872 break;
3873 }
3874 }
3875
3876 if (boot_cpu_has(X86_FEATURE_XSAVES))
3877 rdmsrl(MSR_IA32_XSS, host_xss);
3878
3879 return 0;
3880 }
3881
3882 static struct vmcs *alloc_vmcs_cpu(int cpu)
3883 {
3884 int node = cpu_to_node(cpu);
3885 struct page *pages;
3886 struct vmcs *vmcs;
3887
3888 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3889 if (!pages)
3890 return NULL;
3891 vmcs = page_address(pages);
3892 memset(vmcs, 0, vmcs_config.size);
3893 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3894 return vmcs;
3895 }
3896
3897 static void free_vmcs(struct vmcs *vmcs)
3898 {
3899 free_pages((unsigned long)vmcs, vmcs_config.order);
3900 }
3901
3902 /*
3903 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3904 */
3905 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3906 {
3907 if (!loaded_vmcs->vmcs)
3908 return;
3909 loaded_vmcs_clear(loaded_vmcs);
3910 free_vmcs(loaded_vmcs->vmcs);
3911 loaded_vmcs->vmcs = NULL;
3912 if (loaded_vmcs->msr_bitmap)
3913 free_page((unsigned long)loaded_vmcs->msr_bitmap);
3914 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3915 }
3916
3917 static struct vmcs *alloc_vmcs(void)
3918 {
3919 return alloc_vmcs_cpu(raw_smp_processor_id());
3920 }
3921
3922 static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3923 {
3924 loaded_vmcs->vmcs = alloc_vmcs();
3925 if (!loaded_vmcs->vmcs)
3926 return -ENOMEM;
3927
3928 loaded_vmcs->shadow_vmcs = NULL;
3929 loaded_vmcs_init(loaded_vmcs);
3930
3931 if (cpu_has_vmx_msr_bitmap()) {
3932 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
3933 if (!loaded_vmcs->msr_bitmap)
3934 goto out_vmcs;
3935 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
3936 }
3937 return 0;
3938
3939 out_vmcs:
3940 free_loaded_vmcs(loaded_vmcs);
3941 return -ENOMEM;
3942 }
3943
3944 static void free_kvm_area(void)
3945 {
3946 int cpu;
3947
3948 for_each_possible_cpu(cpu) {
3949 free_vmcs(per_cpu(vmxarea, cpu));
3950 per_cpu(vmxarea, cpu) = NULL;
3951 }
3952 }
3953
3954 enum vmcs_field_width {
3955 VMCS_FIELD_WIDTH_U16 = 0,
3956 VMCS_FIELD_WIDTH_U64 = 1,
3957 VMCS_FIELD_WIDTH_U32 = 2,
3958 VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3
3959 };
3960
3961 static inline int vmcs_field_width(unsigned long field)
3962 {
3963 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
3964 return VMCS_FIELD_WIDTH_U32;
3965 return (field >> 13) & 0x3 ;
3966 }
3967
3968 static inline int vmcs_field_readonly(unsigned long field)
3969 {
3970 return (((field >> 10) & 0x3) == 1);
3971 }
3972
3973 static void init_vmcs_shadow_fields(void)
3974 {
3975 int i, j;
3976
3977 for (i = j = 0; i < max_shadow_read_only_fields; i++) {
3978 u16 field = shadow_read_only_fields[i];
3979 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
3980 (i + 1 == max_shadow_read_only_fields ||
3981 shadow_read_only_fields[i + 1] != field + 1))
3982 pr_err("Missing field from shadow_read_only_field %x\n",
3983 field + 1);
3984
3985 clear_bit(field, vmx_vmread_bitmap);
3986 #ifdef CONFIG_X86_64
3987 if (field & 1)
3988 continue;
3989 #endif
3990 if (j < i)
3991 shadow_read_only_fields[j] = field;
3992 j++;
3993 }
3994 max_shadow_read_only_fields = j;
3995
3996 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3997 u16 field = shadow_read_write_fields[i];
3998 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
3999 (i + 1 == max_shadow_read_write_fields ||
4000 shadow_read_write_fields[i + 1] != field + 1))
4001 pr_err("Missing field from shadow_read_write_field %x\n",
4002 field + 1);
4003
4004 /*
4005 * PML and the preemption timer can be emulated, but the
4006 * processor cannot vmwrite to fields that don't exist
4007 * on bare metal.
4008 */
4009 switch (field) {
4010 case GUEST_PML_INDEX:
4011 if (!cpu_has_vmx_pml())
4012 continue;
4013 break;
4014 case VMX_PREEMPTION_TIMER_VALUE:
4015 if (!cpu_has_vmx_preemption_timer())
4016 continue;
4017 break;
4018 case GUEST_INTR_STATUS:
4019 if (!cpu_has_vmx_apicv())
4020 continue;
4021 break;
4022 default:
4023 break;
4024 }
4025
4026 clear_bit(field, vmx_vmwrite_bitmap);
4027 clear_bit(field, vmx_vmread_bitmap);
4028 #ifdef CONFIG_X86_64
4029 if (field & 1)
4030 continue;
4031 #endif
4032 if (j < i)
4033 shadow_read_write_fields[j] = field;
4034 j++;
4035 }
4036 max_shadow_read_write_fields = j;
4037 }
4038
4039 static __init int alloc_kvm_area(void)
4040 {
4041 int cpu;
4042
4043 for_each_possible_cpu(cpu) {
4044 struct vmcs *vmcs;
4045
4046 vmcs = alloc_vmcs_cpu(cpu);
4047 if (!vmcs) {
4048 free_kvm_area();
4049 return -ENOMEM;
4050 }
4051
4052 per_cpu(vmxarea, cpu) = vmcs;
4053 }
4054 return 0;
4055 }
4056
4057 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
4058 struct kvm_segment *save)
4059 {
4060 if (!emulate_invalid_guest_state) {
4061 /*
4062 * CS and SS RPL should be equal during guest entry according
4063 * to VMX spec, but in reality it is not always so. Since vcpu
4064 * is in the middle of the transition from real mode to
4065 * protected mode it is safe to assume that RPL 0 is a good
4066 * default value.
4067 */
4068 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4069 save->selector &= ~SEGMENT_RPL_MASK;
4070 save->dpl = save->selector & SEGMENT_RPL_MASK;
4071 save->s = 1;
4072 }
4073 vmx_set_segment(vcpu, save, seg);
4074 }
4075
4076 static void enter_pmode(struct kvm_vcpu *vcpu)
4077 {
4078 unsigned long flags;
4079 struct vcpu_vmx *vmx = to_vmx(vcpu);
4080
4081 /*
4082 * Update real mode segment cache. It may be not up-to-date if sement
4083 * register was written while vcpu was in a guest mode.
4084 */
4085 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4086 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4087 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4088 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4089 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4090 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4091
4092 vmx->rmode.vm86_active = 0;
4093
4094 vmx_segment_cache_clear(vmx);
4095
4096 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4097
4098 flags = vmcs_readl(GUEST_RFLAGS);
4099 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
4100 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
4101 vmcs_writel(GUEST_RFLAGS, flags);
4102
4103 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
4104 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
4105
4106 update_exception_bitmap(vcpu);
4107
4108 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4109 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4110 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4111 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4112 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4113 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4114 }
4115
4116 static void fix_rmode_seg(int seg, struct kvm_segment *save)
4117 {
4118 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4119 struct kvm_segment var = *save;
4120
4121 var.dpl = 0x3;
4122 if (seg == VCPU_SREG_CS)
4123 var.type = 0x3;
4124
4125 if (!emulate_invalid_guest_state) {
4126 var.selector = var.base >> 4;
4127 var.base = var.base & 0xffff0;
4128 var.limit = 0xffff;
4129 var.g = 0;
4130 var.db = 0;
4131 var.present = 1;
4132 var.s = 1;
4133 var.l = 0;
4134 var.unusable = 0;
4135 var.type = 0x3;
4136 var.avl = 0;
4137 if (save->base & 0xf)
4138 printk_once(KERN_WARNING "kvm: segment base is not "
4139 "paragraph aligned when entering "
4140 "protected mode (seg=%d)", seg);
4141 }
4142
4143 vmcs_write16(sf->selector, var.selector);
4144 vmcs_writel(sf->base, var.base);
4145 vmcs_write32(sf->limit, var.limit);
4146 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
4147 }
4148
4149 static void enter_rmode(struct kvm_vcpu *vcpu)
4150 {
4151 unsigned long flags;
4152 struct vcpu_vmx *vmx = to_vmx(vcpu);
4153
4154 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4155 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4156 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4157 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4158 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4159 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4160 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4161
4162 vmx->rmode.vm86_active = 1;
4163
4164 /*
4165 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4166 * vcpu. Warn the user that an update is overdue.
4167 */
4168 if (!vcpu->kvm->arch.tss_addr)
4169 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4170 "called before entering vcpu\n");
4171
4172 vmx_segment_cache_clear(vmx);
4173
4174 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
4175 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
4176 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4177
4178 flags = vmcs_readl(GUEST_RFLAGS);
4179 vmx->rmode.save_rflags = flags;
4180
4181 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4182
4183 vmcs_writel(GUEST_RFLAGS, flags);
4184 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4185 update_exception_bitmap(vcpu);
4186
4187 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4188 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4189 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4190 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4191 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4192 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4193
4194 kvm_mmu_reset_context(vcpu);
4195 }
4196
4197 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4198 {
4199 struct vcpu_vmx *vmx = to_vmx(vcpu);
4200 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4201
4202 if (!msr)
4203 return;
4204
4205 /*
4206 * Force kernel_gs_base reloading before EFER changes, as control
4207 * of this msr depends on is_long_mode().
4208 */
4209 vmx_load_host_state(to_vmx(vcpu));
4210 vcpu->arch.efer = efer;
4211 if (efer & EFER_LMA) {
4212 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4213 msr->data = efer;
4214 } else {
4215 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4216
4217 msr->data = efer & ~EFER_LME;
4218 }
4219 setup_msrs(vmx);
4220 }
4221
4222 #ifdef CONFIG_X86_64
4223
4224 static void enter_lmode(struct kvm_vcpu *vcpu)
4225 {
4226 u32 guest_tr_ar;
4227
4228 vmx_segment_cache_clear(to_vmx(vcpu));
4229
4230 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4231 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4232 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4233 __func__);
4234 vmcs_write32(GUEST_TR_AR_BYTES,
4235 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4236 | VMX_AR_TYPE_BUSY_64_TSS);
4237 }
4238 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4239 }
4240
4241 static void exit_lmode(struct kvm_vcpu *vcpu)
4242 {
4243 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4244 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4245 }
4246
4247 #endif
4248
4249 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
4250 bool invalidate_gpa)
4251 {
4252 if (enable_ept && (invalidate_gpa || !enable_vpid)) {
4253 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4254 return;
4255 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4256 } else {
4257 vpid_sync_context(vpid);
4258 }
4259 }
4260
4261 static void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
4262 {
4263 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
4264 }
4265
4266 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4267 {
4268 if (enable_ept)
4269 vmx_flush_tlb(vcpu, true);
4270 }
4271
4272 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4273 {
4274 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4275
4276 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4277 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4278 }
4279
4280 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4281 {
4282 if (enable_ept && is_paging(vcpu))
4283 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4284 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4285 }
4286
4287 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4288 {
4289 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4290
4291 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4292 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4293 }
4294
4295 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4296 {
4297 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4298
4299 if (!test_bit(VCPU_EXREG_PDPTR,
4300 (unsigned long *)&vcpu->arch.regs_dirty))
4301 return;
4302
4303 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4304 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4305 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4306 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4307 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4308 }
4309 }
4310
4311 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4312 {
4313 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4314
4315 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4316 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4317 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4318 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4319 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4320 }
4321
4322 __set_bit(VCPU_EXREG_PDPTR,
4323 (unsigned long *)&vcpu->arch.regs_avail);
4324 __set_bit(VCPU_EXREG_PDPTR,
4325 (unsigned long *)&vcpu->arch.regs_dirty);
4326 }
4327
4328 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4329 {
4330 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4331 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4332 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4333
4334 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4335 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4336 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4337 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4338
4339 return fixed_bits_valid(val, fixed0, fixed1);
4340 }
4341
4342 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4343 {
4344 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4345 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4346
4347 return fixed_bits_valid(val, fixed0, fixed1);
4348 }
4349
4350 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4351 {
4352 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4353 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4354
4355 return fixed_bits_valid(val, fixed0, fixed1);
4356 }
4357
4358 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4359 #define nested_guest_cr4_valid nested_cr4_valid
4360 #define nested_host_cr4_valid nested_cr4_valid
4361
4362 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4363
4364 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4365 unsigned long cr0,
4366 struct kvm_vcpu *vcpu)
4367 {
4368 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4369 vmx_decache_cr3(vcpu);
4370 if (!(cr0 & X86_CR0_PG)) {
4371 /* From paging/starting to nonpaging */
4372 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4373 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4374 (CPU_BASED_CR3_LOAD_EXITING |
4375 CPU_BASED_CR3_STORE_EXITING));
4376 vcpu->arch.cr0 = cr0;
4377 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4378 } else if (!is_paging(vcpu)) {
4379 /* From nonpaging to paging */
4380 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4381 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4382 ~(CPU_BASED_CR3_LOAD_EXITING |
4383 CPU_BASED_CR3_STORE_EXITING));
4384 vcpu->arch.cr0 = cr0;
4385 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4386 }
4387
4388 if (!(cr0 & X86_CR0_WP))
4389 *hw_cr0 &= ~X86_CR0_WP;
4390 }
4391
4392 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4393 {
4394 struct vcpu_vmx *vmx = to_vmx(vcpu);
4395 unsigned long hw_cr0;
4396
4397 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4398 if (enable_unrestricted_guest)
4399 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4400 else {
4401 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4402
4403 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4404 enter_pmode(vcpu);
4405
4406 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4407 enter_rmode(vcpu);
4408 }
4409
4410 #ifdef CONFIG_X86_64
4411 if (vcpu->arch.efer & EFER_LME) {
4412 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4413 enter_lmode(vcpu);
4414 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4415 exit_lmode(vcpu);
4416 }
4417 #endif
4418
4419 if (enable_ept)
4420 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4421
4422 vmcs_writel(CR0_READ_SHADOW, cr0);
4423 vmcs_writel(GUEST_CR0, hw_cr0);
4424 vcpu->arch.cr0 = cr0;
4425
4426 /* depends on vcpu->arch.cr0 to be set to a new value */
4427 vmx->emulation_required = emulation_required(vcpu);
4428 }
4429
4430 static int get_ept_level(struct kvm_vcpu *vcpu)
4431 {
4432 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
4433 return 5;
4434 return 4;
4435 }
4436
4437 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4438 {
4439 u64 eptp = VMX_EPTP_MT_WB;
4440
4441 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
4442
4443 if (enable_ept_ad_bits &&
4444 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4445 eptp |= VMX_EPTP_AD_ENABLE_BIT;
4446 eptp |= (root_hpa & PAGE_MASK);
4447
4448 return eptp;
4449 }
4450
4451 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4452 {
4453 unsigned long guest_cr3;
4454 u64 eptp;
4455
4456 guest_cr3 = cr3;
4457 if (enable_ept) {
4458 eptp = construct_eptp(vcpu, cr3);
4459 vmcs_write64(EPT_POINTER, eptp);
4460 if (is_paging(vcpu) || is_guest_mode(vcpu))
4461 guest_cr3 = kvm_read_cr3(vcpu);
4462 else
4463 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4464 ept_load_pdptrs(vcpu);
4465 }
4466
4467 vmx_flush_tlb(vcpu, true);
4468 vmcs_writel(GUEST_CR3, guest_cr3);
4469 }
4470
4471 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4472 {
4473 /*
4474 * Pass through host's Machine Check Enable value to hw_cr4, which
4475 * is in force while we are in guest mode. Do not let guests control
4476 * this bit, even if host CR4.MCE == 0.
4477 */
4478 unsigned long hw_cr4 =
4479 (cr4_read_shadow() & X86_CR4_MCE) |
4480 (cr4 & ~X86_CR4_MCE) |
4481 (to_vmx(vcpu)->rmode.vm86_active ?
4482 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4483
4484 if ((cr4 & X86_CR4_UMIP) && !boot_cpu_has(X86_FEATURE_UMIP)) {
4485 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
4486 SECONDARY_EXEC_DESC);
4487 hw_cr4 &= ~X86_CR4_UMIP;
4488 } else
4489 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
4490 SECONDARY_EXEC_DESC);
4491
4492 if (cr4 & X86_CR4_VMXE) {
4493 /*
4494 * To use VMXON (and later other VMX instructions), a guest
4495 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4496 * So basically the check on whether to allow nested VMX
4497 * is here.
4498 */
4499 if (!nested_vmx_allowed(vcpu))
4500 return 1;
4501 }
4502
4503 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4504 return 1;
4505
4506 vcpu->arch.cr4 = cr4;
4507 if (enable_ept) {
4508 if (!is_paging(vcpu)) {
4509 hw_cr4 &= ~X86_CR4_PAE;
4510 hw_cr4 |= X86_CR4_PSE;
4511 } else if (!(cr4 & X86_CR4_PAE)) {
4512 hw_cr4 &= ~X86_CR4_PAE;
4513 }
4514 }
4515
4516 if (!enable_unrestricted_guest && !is_paging(vcpu))
4517 /*
4518 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4519 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4520 * to be manually disabled when guest switches to non-paging
4521 * mode.
4522 *
4523 * If !enable_unrestricted_guest, the CPU is always running
4524 * with CR0.PG=1 and CR4 needs to be modified.
4525 * If enable_unrestricted_guest, the CPU automatically
4526 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4527 */
4528 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4529
4530 vmcs_writel(CR4_READ_SHADOW, cr4);
4531 vmcs_writel(GUEST_CR4, hw_cr4);
4532 return 0;
4533 }
4534
4535 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4536 struct kvm_segment *var, int seg)
4537 {
4538 struct vcpu_vmx *vmx = to_vmx(vcpu);
4539 u32 ar;
4540
4541 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4542 *var = vmx->rmode.segs[seg];
4543 if (seg == VCPU_SREG_TR
4544 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4545 return;
4546 var->base = vmx_read_guest_seg_base(vmx, seg);
4547 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4548 return;
4549 }
4550 var->base = vmx_read_guest_seg_base(vmx, seg);
4551 var->limit = vmx_read_guest_seg_limit(vmx, seg);
4552 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4553 ar = vmx_read_guest_seg_ar(vmx, seg);
4554 var->unusable = (ar >> 16) & 1;
4555 var->type = ar & 15;
4556 var->s = (ar >> 4) & 1;
4557 var->dpl = (ar >> 5) & 3;
4558 /*
4559 * Some userspaces do not preserve unusable property. Since usable
4560 * segment has to be present according to VMX spec we can use present
4561 * property to amend userspace bug by making unusable segment always
4562 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4563 * segment as unusable.
4564 */
4565 var->present = !var->unusable;
4566 var->avl = (ar >> 12) & 1;
4567 var->l = (ar >> 13) & 1;
4568 var->db = (ar >> 14) & 1;
4569 var->g = (ar >> 15) & 1;
4570 }
4571
4572 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4573 {
4574 struct kvm_segment s;
4575
4576 if (to_vmx(vcpu)->rmode.vm86_active) {
4577 vmx_get_segment(vcpu, &s, seg);
4578 return s.base;
4579 }
4580 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4581 }
4582
4583 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4584 {
4585 struct vcpu_vmx *vmx = to_vmx(vcpu);
4586
4587 if (unlikely(vmx->rmode.vm86_active))
4588 return 0;
4589 else {
4590 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4591 return VMX_AR_DPL(ar);
4592 }
4593 }
4594
4595 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4596 {
4597 u32 ar;
4598
4599 if (var->unusable || !var->present)
4600 ar = 1 << 16;
4601 else {
4602 ar = var->type & 15;
4603 ar |= (var->s & 1) << 4;
4604 ar |= (var->dpl & 3) << 5;
4605 ar |= (var->present & 1) << 7;
4606 ar |= (var->avl & 1) << 12;
4607 ar |= (var->l & 1) << 13;
4608 ar |= (var->db & 1) << 14;
4609 ar |= (var->g & 1) << 15;
4610 }
4611
4612 return ar;
4613 }
4614
4615 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4616 struct kvm_segment *var, int seg)
4617 {
4618 struct vcpu_vmx *vmx = to_vmx(vcpu);
4619 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4620
4621 vmx_segment_cache_clear(vmx);
4622
4623 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4624 vmx->rmode.segs[seg] = *var;
4625 if (seg == VCPU_SREG_TR)
4626 vmcs_write16(sf->selector, var->selector);
4627 else if (var->s)
4628 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4629 goto out;
4630 }
4631
4632 vmcs_writel(sf->base, var->base);
4633 vmcs_write32(sf->limit, var->limit);
4634 vmcs_write16(sf->selector, var->selector);
4635
4636 /*
4637 * Fix the "Accessed" bit in AR field of segment registers for older
4638 * qemu binaries.
4639 * IA32 arch specifies that at the time of processor reset the
4640 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4641 * is setting it to 0 in the userland code. This causes invalid guest
4642 * state vmexit when "unrestricted guest" mode is turned on.
4643 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4644 * tree. Newer qemu binaries with that qemu fix would not need this
4645 * kvm hack.
4646 */
4647 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4648 var->type |= 0x1; /* Accessed */
4649
4650 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4651
4652 out:
4653 vmx->emulation_required = emulation_required(vcpu);
4654 }
4655
4656 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4657 {
4658 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4659
4660 *db = (ar >> 14) & 1;
4661 *l = (ar >> 13) & 1;
4662 }
4663
4664 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4665 {
4666 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4667 dt->address = vmcs_readl(GUEST_IDTR_BASE);
4668 }
4669
4670 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4671 {
4672 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4673 vmcs_writel(GUEST_IDTR_BASE, dt->address);
4674 }
4675
4676 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4677 {
4678 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4679 dt->address = vmcs_readl(GUEST_GDTR_BASE);
4680 }
4681
4682 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4683 {
4684 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4685 vmcs_writel(GUEST_GDTR_BASE, dt->address);
4686 }
4687
4688 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4689 {
4690 struct kvm_segment var;
4691 u32 ar;
4692
4693 vmx_get_segment(vcpu, &var, seg);
4694 var.dpl = 0x3;
4695 if (seg == VCPU_SREG_CS)
4696 var.type = 0x3;
4697 ar = vmx_segment_access_rights(&var);
4698
4699 if (var.base != (var.selector << 4))
4700 return false;
4701 if (var.limit != 0xffff)
4702 return false;
4703 if (ar != 0xf3)
4704 return false;
4705
4706 return true;
4707 }
4708
4709 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4710 {
4711 struct kvm_segment cs;
4712 unsigned int cs_rpl;
4713
4714 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4715 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4716
4717 if (cs.unusable)
4718 return false;
4719 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4720 return false;
4721 if (!cs.s)
4722 return false;
4723 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4724 if (cs.dpl > cs_rpl)
4725 return false;
4726 } else {
4727 if (cs.dpl != cs_rpl)
4728 return false;
4729 }
4730 if (!cs.present)
4731 return false;
4732
4733 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4734 return true;
4735 }
4736
4737 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4738 {
4739 struct kvm_segment ss;
4740 unsigned int ss_rpl;
4741
4742 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4743 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4744
4745 if (ss.unusable)
4746 return true;
4747 if (ss.type != 3 && ss.type != 7)
4748 return false;
4749 if (!ss.s)
4750 return false;
4751 if (ss.dpl != ss_rpl) /* DPL != RPL */
4752 return false;
4753 if (!ss.present)
4754 return false;
4755
4756 return true;
4757 }
4758
4759 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4760 {
4761 struct kvm_segment var;
4762 unsigned int rpl;
4763
4764 vmx_get_segment(vcpu, &var, seg);
4765 rpl = var.selector & SEGMENT_RPL_MASK;
4766
4767 if (var.unusable)
4768 return true;
4769 if (!var.s)
4770 return false;
4771 if (!var.present)
4772 return false;
4773 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4774 if (var.dpl < rpl) /* DPL < RPL */
4775 return false;
4776 }
4777
4778 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4779 * rights flags
4780 */
4781 return true;
4782 }
4783
4784 static bool tr_valid(struct kvm_vcpu *vcpu)
4785 {
4786 struct kvm_segment tr;
4787
4788 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4789
4790 if (tr.unusable)
4791 return false;
4792 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4793 return false;
4794 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4795 return false;
4796 if (!tr.present)
4797 return false;
4798
4799 return true;
4800 }
4801
4802 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4803 {
4804 struct kvm_segment ldtr;
4805
4806 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4807
4808 if (ldtr.unusable)
4809 return true;
4810 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4811 return false;
4812 if (ldtr.type != 2)
4813 return false;
4814 if (!ldtr.present)
4815 return false;
4816
4817 return true;
4818 }
4819
4820 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4821 {
4822 struct kvm_segment cs, ss;
4823
4824 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4825 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4826
4827 return ((cs.selector & SEGMENT_RPL_MASK) ==
4828 (ss.selector & SEGMENT_RPL_MASK));
4829 }
4830
4831 /*
4832 * Check if guest state is valid. Returns true if valid, false if
4833 * not.
4834 * We assume that registers are always usable
4835 */
4836 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4837 {
4838 if (enable_unrestricted_guest)
4839 return true;
4840
4841 /* real mode guest state checks */
4842 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4843 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4844 return false;
4845 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4846 return false;
4847 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4848 return false;
4849 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4850 return false;
4851 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4852 return false;
4853 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4854 return false;
4855 } else {
4856 /* protected mode guest state checks */
4857 if (!cs_ss_rpl_check(vcpu))
4858 return false;
4859 if (!code_segment_valid(vcpu))
4860 return false;
4861 if (!stack_segment_valid(vcpu))
4862 return false;
4863 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4864 return false;
4865 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4866 return false;
4867 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4868 return false;
4869 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4870 return false;
4871 if (!tr_valid(vcpu))
4872 return false;
4873 if (!ldtr_valid(vcpu))
4874 return false;
4875 }
4876 /* TODO:
4877 * - Add checks on RIP
4878 * - Add checks on RFLAGS
4879 */
4880
4881 return true;
4882 }
4883
4884 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
4885 {
4886 return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
4887 }
4888
4889 static int init_rmode_tss(struct kvm *kvm)
4890 {
4891 gfn_t fn;
4892 u16 data = 0;
4893 int idx, r;
4894
4895 idx = srcu_read_lock(&kvm->srcu);
4896 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4897 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4898 if (r < 0)
4899 goto out;
4900 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4901 r = kvm_write_guest_page(kvm, fn++, &data,
4902 TSS_IOPB_BASE_OFFSET, sizeof(u16));
4903 if (r < 0)
4904 goto out;
4905 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4906 if (r < 0)
4907 goto out;
4908 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4909 if (r < 0)
4910 goto out;
4911 data = ~0;
4912 r = kvm_write_guest_page(kvm, fn, &data,
4913 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4914 sizeof(u8));
4915 out:
4916 srcu_read_unlock(&kvm->srcu, idx);
4917 return r;
4918 }
4919
4920 static int init_rmode_identity_map(struct kvm *kvm)
4921 {
4922 int i, idx, r = 0;
4923 kvm_pfn_t identity_map_pfn;
4924 u32 tmp;
4925
4926 /* Protect kvm->arch.ept_identity_pagetable_done. */
4927 mutex_lock(&kvm->slots_lock);
4928
4929 if (likely(kvm->arch.ept_identity_pagetable_done))
4930 goto out2;
4931
4932 if (!kvm->arch.ept_identity_map_addr)
4933 kvm->arch.ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4934 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4935
4936 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4937 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4938 if (r < 0)
4939 goto out2;
4940
4941 idx = srcu_read_lock(&kvm->srcu);
4942 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4943 if (r < 0)
4944 goto out;
4945 /* Set up identity-mapping pagetable for EPT in real mode */
4946 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4947 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4948 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4949 r = kvm_write_guest_page(kvm, identity_map_pfn,
4950 &tmp, i * sizeof(tmp), sizeof(tmp));
4951 if (r < 0)
4952 goto out;
4953 }
4954 kvm->arch.ept_identity_pagetable_done = true;
4955
4956 out:
4957 srcu_read_unlock(&kvm->srcu, idx);
4958
4959 out2:
4960 mutex_unlock(&kvm->slots_lock);
4961 return r;
4962 }
4963
4964 static void seg_setup(int seg)
4965 {
4966 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4967 unsigned int ar;
4968
4969 vmcs_write16(sf->selector, 0);
4970 vmcs_writel(sf->base, 0);
4971 vmcs_write32(sf->limit, 0xffff);
4972 ar = 0x93;
4973 if (seg == VCPU_SREG_CS)
4974 ar |= 0x08; /* code segment */
4975
4976 vmcs_write32(sf->ar_bytes, ar);
4977 }
4978
4979 static int alloc_apic_access_page(struct kvm *kvm)
4980 {
4981 struct page *page;
4982 int r = 0;
4983
4984 mutex_lock(&kvm->slots_lock);
4985 if (kvm->arch.apic_access_page_done)
4986 goto out;
4987 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4988 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4989 if (r)
4990 goto out;
4991
4992 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4993 if (is_error_page(page)) {
4994 r = -EFAULT;
4995 goto out;
4996 }
4997
4998 /*
4999 * Do not pin the page in memory, so that memory hot-unplug
5000 * is able to migrate it.
5001 */
5002 put_page(page);
5003 kvm->arch.apic_access_page_done = true;
5004 out:
5005 mutex_unlock(&kvm->slots_lock);
5006 return r;
5007 }
5008
5009 static int allocate_vpid(void)
5010 {
5011 int vpid;
5012
5013 if (!enable_vpid)
5014 return 0;
5015 spin_lock(&vmx_vpid_lock);
5016 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
5017 if (vpid < VMX_NR_VPIDS)
5018 __set_bit(vpid, vmx_vpid_bitmap);
5019 else
5020 vpid = 0;
5021 spin_unlock(&vmx_vpid_lock);
5022 return vpid;
5023 }
5024
5025 static void free_vpid(int vpid)
5026 {
5027 if (!enable_vpid || vpid == 0)
5028 return;
5029 spin_lock(&vmx_vpid_lock);
5030 __clear_bit(vpid, vmx_vpid_bitmap);
5031 spin_unlock(&vmx_vpid_lock);
5032 }
5033
5034 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
5035 u32 msr, int type)
5036 {
5037 int f = sizeof(unsigned long);
5038
5039 if (!cpu_has_vmx_msr_bitmap())
5040 return;
5041
5042 /*
5043 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5044 * have the write-low and read-high bitmap offsets the wrong way round.
5045 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5046 */
5047 if (msr <= 0x1fff) {
5048 if (type & MSR_TYPE_R)
5049 /* read-low */
5050 __clear_bit(msr, msr_bitmap + 0x000 / f);
5051
5052 if (type & MSR_TYPE_W)
5053 /* write-low */
5054 __clear_bit(msr, msr_bitmap + 0x800 / f);
5055
5056 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5057 msr &= 0x1fff;
5058 if (type & MSR_TYPE_R)
5059 /* read-high */
5060 __clear_bit(msr, msr_bitmap + 0x400 / f);
5061
5062 if (type & MSR_TYPE_W)
5063 /* write-high */
5064 __clear_bit(msr, msr_bitmap + 0xc00 / f);
5065
5066 }
5067 }
5068
5069 static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
5070 u32 msr, int type)
5071 {
5072 int f = sizeof(unsigned long);
5073
5074 if (!cpu_has_vmx_msr_bitmap())
5075 return;
5076
5077 /*
5078 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5079 * have the write-low and read-high bitmap offsets the wrong way round.
5080 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5081 */
5082 if (msr <= 0x1fff) {
5083 if (type & MSR_TYPE_R)
5084 /* read-low */
5085 __set_bit(msr, msr_bitmap + 0x000 / f);
5086
5087 if (type & MSR_TYPE_W)
5088 /* write-low */
5089 __set_bit(msr, msr_bitmap + 0x800 / f);
5090
5091 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5092 msr &= 0x1fff;
5093 if (type & MSR_TYPE_R)
5094 /* read-high */
5095 __set_bit(msr, msr_bitmap + 0x400 / f);
5096
5097 if (type & MSR_TYPE_W)
5098 /* write-high */
5099 __set_bit(msr, msr_bitmap + 0xc00 / f);
5100
5101 }
5102 }
5103
5104 static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
5105 u32 msr, int type, bool value)
5106 {
5107 if (value)
5108 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
5109 else
5110 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
5111 }
5112
5113 /*
5114 * If a msr is allowed by L0, we should check whether it is allowed by L1.
5115 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
5116 */
5117 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
5118 unsigned long *msr_bitmap_nested,
5119 u32 msr, int type)
5120 {
5121 int f = sizeof(unsigned long);
5122
5123 /*
5124 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5125 * have the write-low and read-high bitmap offsets the wrong way round.
5126 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5127 */
5128 if (msr <= 0x1fff) {
5129 if (type & MSR_TYPE_R &&
5130 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
5131 /* read-low */
5132 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
5133
5134 if (type & MSR_TYPE_W &&
5135 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
5136 /* write-low */
5137 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
5138
5139 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5140 msr &= 0x1fff;
5141 if (type & MSR_TYPE_R &&
5142 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
5143 /* read-high */
5144 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
5145
5146 if (type & MSR_TYPE_W &&
5147 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
5148 /* write-high */
5149 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
5150
5151 }
5152 }
5153
5154 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5155 {
5156 u8 mode = 0;
5157
5158 if (cpu_has_secondary_exec_ctrls() &&
5159 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
5160 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
5161 mode |= MSR_BITMAP_MODE_X2APIC;
5162 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
5163 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
5164 }
5165
5166 if (is_long_mode(vcpu))
5167 mode |= MSR_BITMAP_MODE_LM;
5168
5169 return mode;
5170 }
5171
5172 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
5173
5174 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
5175 u8 mode)
5176 {
5177 int msr;
5178
5179 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
5180 unsigned word = msr / BITS_PER_LONG;
5181 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
5182 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
5183 }
5184
5185 if (mode & MSR_BITMAP_MODE_X2APIC) {
5186 /*
5187 * TPR reads and writes can be virtualized even if virtual interrupt
5188 * delivery is not in use.
5189 */
5190 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
5191 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
5192 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
5193 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
5194 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
5195 }
5196 }
5197 }
5198
5199 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
5200 {
5201 struct vcpu_vmx *vmx = to_vmx(vcpu);
5202 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
5203 u8 mode = vmx_msr_bitmap_mode(vcpu);
5204 u8 changed = mode ^ vmx->msr_bitmap_mode;
5205
5206 if (!changed)
5207 return;
5208
5209 vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW,
5210 !(mode & MSR_BITMAP_MODE_LM));
5211
5212 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
5213 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
5214
5215 vmx->msr_bitmap_mode = mode;
5216 }
5217
5218 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
5219 {
5220 return enable_apicv;
5221 }
5222
5223 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
5224 {
5225 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5226 gfn_t gfn;
5227
5228 /*
5229 * Don't need to mark the APIC access page dirty; it is never
5230 * written to by the CPU during APIC virtualization.
5231 */
5232
5233 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5234 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5235 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5236 }
5237
5238 if (nested_cpu_has_posted_intr(vmcs12)) {
5239 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5240 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5241 }
5242 }
5243
5244
5245 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
5246 {
5247 struct vcpu_vmx *vmx = to_vmx(vcpu);
5248 int max_irr;
5249 void *vapic_page;
5250 u16 status;
5251
5252 if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5253 return;
5254
5255 vmx->nested.pi_pending = false;
5256 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5257 return;
5258
5259 max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5260 if (max_irr != 256) {
5261 vapic_page = kmap(vmx->nested.virtual_apic_page);
5262 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
5263 vapic_page, &max_irr);
5264 kunmap(vmx->nested.virtual_apic_page);
5265
5266 status = vmcs_read16(GUEST_INTR_STATUS);
5267 if ((u8)max_irr > ((u8)status & 0xff)) {
5268 status &= ~0xff;
5269 status |= (u8)max_irr;
5270 vmcs_write16(GUEST_INTR_STATUS, status);
5271 }
5272 }
5273
5274 nested_mark_vmcs12_pages_dirty(vcpu);
5275 }
5276
5277 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5278 bool nested)
5279 {
5280 #ifdef CONFIG_SMP
5281 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5282
5283 if (vcpu->mode == IN_GUEST_MODE) {
5284 /*
5285 * The vector of interrupt to be delivered to vcpu had
5286 * been set in PIR before this function.
5287 *
5288 * Following cases will be reached in this block, and
5289 * we always send a notification event in all cases as
5290 * explained below.
5291 *
5292 * Case 1: vcpu keeps in non-root mode. Sending a
5293 * notification event posts the interrupt to vcpu.
5294 *
5295 * Case 2: vcpu exits to root mode and is still
5296 * runnable. PIR will be synced to vIRR before the
5297 * next vcpu entry. Sending a notification event in
5298 * this case has no effect, as vcpu is not in root
5299 * mode.
5300 *
5301 * Case 3: vcpu exits to root mode and is blocked.
5302 * vcpu_block() has already synced PIR to vIRR and
5303 * never blocks vcpu if vIRR is not cleared. Therefore,
5304 * a blocked vcpu here does not wait for any requested
5305 * interrupts in PIR, and sending a notification event
5306 * which has no effect is safe here.
5307 */
5308
5309 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5310 return true;
5311 }
5312 #endif
5313 return false;
5314 }
5315
5316 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5317 int vector)
5318 {
5319 struct vcpu_vmx *vmx = to_vmx(vcpu);
5320
5321 if (is_guest_mode(vcpu) &&
5322 vector == vmx->nested.posted_intr_nv) {
5323 /*
5324 * If a posted intr is not recognized by hardware,
5325 * we will accomplish it in the next vmentry.
5326 */
5327 vmx->nested.pi_pending = true;
5328 kvm_make_request(KVM_REQ_EVENT, vcpu);
5329 /* the PIR and ON have been set by L1. */
5330 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
5331 kvm_vcpu_kick(vcpu);
5332 return 0;
5333 }
5334 return -1;
5335 }
5336 /*
5337 * Send interrupt to vcpu via posted interrupt way.
5338 * 1. If target vcpu is running(non-root mode), send posted interrupt
5339 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5340 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5341 * interrupt from PIR in next vmentry.
5342 */
5343 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5344 {
5345 struct vcpu_vmx *vmx = to_vmx(vcpu);
5346 int r;
5347
5348 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5349 if (!r)
5350 return;
5351
5352 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5353 return;
5354
5355 /* If a previous notification has sent the IPI, nothing to do. */
5356 if (pi_test_and_set_on(&vmx->pi_desc))
5357 return;
5358
5359 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5360 kvm_vcpu_kick(vcpu);
5361 }
5362
5363 /*
5364 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5365 * will not change in the lifetime of the guest.
5366 * Note that host-state that does change is set elsewhere. E.g., host-state
5367 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5368 */
5369 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5370 {
5371 u32 low32, high32;
5372 unsigned long tmpl;
5373 struct desc_ptr dt;
5374 unsigned long cr0, cr3, cr4;
5375
5376 cr0 = read_cr0();
5377 WARN_ON(cr0 & X86_CR0_TS);
5378 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
5379
5380 /*
5381 * Save the most likely value for this task's CR3 in the VMCS.
5382 * We can't use __get_current_cr3_fast() because we're not atomic.
5383 */
5384 cr3 = __read_cr3();
5385 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
5386 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
5387
5388 /* Save the most likely value for this task's CR4 in the VMCS. */
5389 cr4 = cr4_read_shadow();
5390 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
5391 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
5392
5393 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
5394 #ifdef CONFIG_X86_64
5395 /*
5396 * Load null selectors, so we can avoid reloading them in
5397 * __vmx_load_host_state(), in case userspace uses the null selectors
5398 * too (the expected case).
5399 */
5400 vmcs_write16(HOST_DS_SELECTOR, 0);
5401 vmcs_write16(HOST_ES_SELECTOR, 0);
5402 #else
5403 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5404 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5405 #endif
5406 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5407 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
5408
5409 store_idt(&dt);
5410 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
5411 vmx->host_idt_base = dt.address;
5412
5413 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5414
5415 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5416 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5417 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5418 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
5419
5420 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5421 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5422 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5423 }
5424 }
5425
5426 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5427 {
5428 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5429 if (enable_ept)
5430 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5431 if (is_guest_mode(&vmx->vcpu))
5432 vmx->vcpu.arch.cr4_guest_owned_bits &=
5433 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5434 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5435 }
5436
5437 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5438 {
5439 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5440
5441 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5442 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5443
5444 if (!enable_vnmi)
5445 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
5446
5447 /* Enable the preemption timer dynamically */
5448 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5449 return pin_based_exec_ctrl;
5450 }
5451
5452 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5453 {
5454 struct vcpu_vmx *vmx = to_vmx(vcpu);
5455
5456 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5457 if (cpu_has_secondary_exec_ctrls()) {
5458 if (kvm_vcpu_apicv_active(vcpu))
5459 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5460 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5461 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5462 else
5463 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5464 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5465 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5466 }
5467
5468 if (cpu_has_vmx_msr_bitmap())
5469 vmx_update_msr_bitmap(vcpu);
5470 }
5471
5472 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5473 {
5474 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5475
5476 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5477 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5478
5479 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5480 exec_control &= ~CPU_BASED_TPR_SHADOW;
5481 #ifdef CONFIG_X86_64
5482 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5483 CPU_BASED_CR8_LOAD_EXITING;
5484 #endif
5485 }
5486 if (!enable_ept)
5487 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5488 CPU_BASED_CR3_LOAD_EXITING |
5489 CPU_BASED_INVLPG_EXITING;
5490 return exec_control;
5491 }
5492
5493 static bool vmx_rdrand_supported(void)
5494 {
5495 return vmcs_config.cpu_based_2nd_exec_ctrl &
5496 SECONDARY_EXEC_RDRAND_EXITING;
5497 }
5498
5499 static bool vmx_rdseed_supported(void)
5500 {
5501 return vmcs_config.cpu_based_2nd_exec_ctrl &
5502 SECONDARY_EXEC_RDSEED_EXITING;
5503 }
5504
5505 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
5506 {
5507 struct kvm_vcpu *vcpu = &vmx->vcpu;
5508
5509 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5510
5511 if (!cpu_need_virtualize_apic_accesses(vcpu))
5512 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5513 if (vmx->vpid == 0)
5514 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5515 if (!enable_ept) {
5516 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5517 enable_unrestricted_guest = 0;
5518 /* Enable INVPCID for non-ept guests may cause performance regression. */
5519 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5520 }
5521 if (!enable_unrestricted_guest)
5522 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5523 if (!ple_gap)
5524 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5525 if (!kvm_vcpu_apicv_active(vcpu))
5526 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5527 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5528 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5529
5530 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
5531 * in vmx_set_cr4. */
5532 exec_control &= ~SECONDARY_EXEC_DESC;
5533
5534 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5535 (handle_vmptrld).
5536 We can NOT enable shadow_vmcs here because we don't have yet
5537 a current VMCS12
5538 */
5539 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5540
5541 if (!enable_pml)
5542 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5543
5544 if (vmx_xsaves_supported()) {
5545 /* Exposing XSAVES only when XSAVE is exposed */
5546 bool xsaves_enabled =
5547 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
5548 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
5549
5550 if (!xsaves_enabled)
5551 exec_control &= ~SECONDARY_EXEC_XSAVES;
5552
5553 if (nested) {
5554 if (xsaves_enabled)
5555 vmx->nested.nested_vmx_secondary_ctls_high |=
5556 SECONDARY_EXEC_XSAVES;
5557 else
5558 vmx->nested.nested_vmx_secondary_ctls_high &=
5559 ~SECONDARY_EXEC_XSAVES;
5560 }
5561 }
5562
5563 if (vmx_rdtscp_supported()) {
5564 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
5565 if (!rdtscp_enabled)
5566 exec_control &= ~SECONDARY_EXEC_RDTSCP;
5567
5568 if (nested) {
5569 if (rdtscp_enabled)
5570 vmx->nested.nested_vmx_secondary_ctls_high |=
5571 SECONDARY_EXEC_RDTSCP;
5572 else
5573 vmx->nested.nested_vmx_secondary_ctls_high &=
5574 ~SECONDARY_EXEC_RDTSCP;
5575 }
5576 }
5577
5578 if (vmx_invpcid_supported()) {
5579 /* Exposing INVPCID only when PCID is exposed */
5580 bool invpcid_enabled =
5581 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
5582 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
5583
5584 if (!invpcid_enabled) {
5585 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5586 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
5587 }
5588
5589 if (nested) {
5590 if (invpcid_enabled)
5591 vmx->nested.nested_vmx_secondary_ctls_high |=
5592 SECONDARY_EXEC_ENABLE_INVPCID;
5593 else
5594 vmx->nested.nested_vmx_secondary_ctls_high &=
5595 ~SECONDARY_EXEC_ENABLE_INVPCID;
5596 }
5597 }
5598
5599 if (vmx_rdrand_supported()) {
5600 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
5601 if (rdrand_enabled)
5602 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
5603
5604 if (nested) {
5605 if (rdrand_enabled)
5606 vmx->nested.nested_vmx_secondary_ctls_high |=
5607 SECONDARY_EXEC_RDRAND_EXITING;
5608 else
5609 vmx->nested.nested_vmx_secondary_ctls_high &=
5610 ~SECONDARY_EXEC_RDRAND_EXITING;
5611 }
5612 }
5613
5614 if (vmx_rdseed_supported()) {
5615 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
5616 if (rdseed_enabled)
5617 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
5618
5619 if (nested) {
5620 if (rdseed_enabled)
5621 vmx->nested.nested_vmx_secondary_ctls_high |=
5622 SECONDARY_EXEC_RDSEED_EXITING;
5623 else
5624 vmx->nested.nested_vmx_secondary_ctls_high &=
5625 ~SECONDARY_EXEC_RDSEED_EXITING;
5626 }
5627 }
5628
5629 vmx->secondary_exec_control = exec_control;
5630 }
5631
5632 static void ept_set_mmio_spte_mask(void)
5633 {
5634 /*
5635 * EPT Misconfigurations can be generated if the value of bits 2:0
5636 * of an EPT paging-structure entry is 110b (write/execute).
5637 */
5638 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5639 VMX_EPT_MISCONFIG_WX_VALUE);
5640 }
5641
5642 #define VMX_XSS_EXIT_BITMAP 0
5643 /*
5644 * Sets up the vmcs for emulated real mode.
5645 */
5646 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
5647 {
5648 #ifdef CONFIG_X86_64
5649 unsigned long a;
5650 #endif
5651 int i;
5652
5653 if (enable_shadow_vmcs) {
5654 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5655 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5656 }
5657 if (cpu_has_vmx_msr_bitmap())
5658 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
5659
5660 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5661
5662 /* Control */
5663 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5664 vmx->hv_deadline_tsc = -1;
5665
5666 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5667
5668 if (cpu_has_secondary_exec_ctrls()) {
5669 vmx_compute_secondary_exec_control(vmx);
5670 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5671 vmx->secondary_exec_control);
5672 }
5673
5674 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5675 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5676 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5677 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5678 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5679
5680 vmcs_write16(GUEST_INTR_STATUS, 0);
5681
5682 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5683 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5684 }
5685
5686 if (ple_gap) {
5687 vmcs_write32(PLE_GAP, ple_gap);
5688 vmx->ple_window = ple_window;
5689 vmx->ple_window_dirty = true;
5690 }
5691
5692 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5693 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5694 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
5695
5696 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
5697 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
5698 vmx_set_constant_host_state(vmx);
5699 #ifdef CONFIG_X86_64
5700 rdmsrl(MSR_FS_BASE, a);
5701 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5702 rdmsrl(MSR_GS_BASE, a);
5703 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5704 #else
5705 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5706 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5707 #endif
5708
5709 if (cpu_has_vmx_vmfunc())
5710 vmcs_write64(VM_FUNCTION_CONTROL, 0);
5711
5712 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5713 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5714 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5715 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5716 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5717
5718 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5719 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5720
5721 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5722 u32 index = vmx_msr_index[i];
5723 u32 data_low, data_high;
5724 int j = vmx->nmsrs;
5725
5726 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5727 continue;
5728 if (wrmsr_safe(index, data_low, data_high) < 0)
5729 continue;
5730 vmx->guest_msrs[j].index = i;
5731 vmx->guest_msrs[j].data = 0;
5732 vmx->guest_msrs[j].mask = -1ull;
5733 ++vmx->nmsrs;
5734 }
5735
5736 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
5737 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, vmx->arch_capabilities);
5738
5739 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5740
5741 /* 22.2.1, 20.8.1 */
5742 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5743
5744 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5745 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5746
5747 set_cr4_guest_host_mask(vmx);
5748
5749 if (vmx_xsaves_supported())
5750 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5751
5752 if (enable_pml) {
5753 ASSERT(vmx->pml_pg);
5754 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5755 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5756 }
5757 }
5758
5759 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5760 {
5761 struct vcpu_vmx *vmx = to_vmx(vcpu);
5762 struct msr_data apic_base_msr;
5763 u64 cr0;
5764
5765 vmx->rmode.vm86_active = 0;
5766 vmx->spec_ctrl = 0;
5767
5768 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5769 kvm_set_cr8(vcpu, 0);
5770
5771 if (!init_event) {
5772 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5773 MSR_IA32_APICBASE_ENABLE;
5774 if (kvm_vcpu_is_reset_bsp(vcpu))
5775 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5776 apic_base_msr.host_initiated = true;
5777 kvm_set_apic_base(vcpu, &apic_base_msr);
5778 }
5779
5780 vmx_segment_cache_clear(vmx);
5781
5782 seg_setup(VCPU_SREG_CS);
5783 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5784 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5785
5786 seg_setup(VCPU_SREG_DS);
5787 seg_setup(VCPU_SREG_ES);
5788 seg_setup(VCPU_SREG_FS);
5789 seg_setup(VCPU_SREG_GS);
5790 seg_setup(VCPU_SREG_SS);
5791
5792 vmcs_write16(GUEST_TR_SELECTOR, 0);
5793 vmcs_writel(GUEST_TR_BASE, 0);
5794 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5795 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5796
5797 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5798 vmcs_writel(GUEST_LDTR_BASE, 0);
5799 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5800 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5801
5802 if (!init_event) {
5803 vmcs_write32(GUEST_SYSENTER_CS, 0);
5804 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5805 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5806 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5807 }
5808
5809 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
5810 kvm_rip_write(vcpu, 0xfff0);
5811
5812 vmcs_writel(GUEST_GDTR_BASE, 0);
5813 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5814
5815 vmcs_writel(GUEST_IDTR_BASE, 0);
5816 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5817
5818 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5819 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5820 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5821 if (kvm_mpx_supported())
5822 vmcs_write64(GUEST_BNDCFGS, 0);
5823
5824 setup_msrs(vmx);
5825
5826 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
5827
5828 if (cpu_has_vmx_tpr_shadow() && !init_event) {
5829 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5830 if (cpu_need_tpr_shadow(vcpu))
5831 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5832 __pa(vcpu->arch.apic->regs));
5833 vmcs_write32(TPR_THRESHOLD, 0);
5834 }
5835
5836 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5837
5838 if (vmx->vpid != 0)
5839 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5840
5841 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5842 vmx->vcpu.arch.cr0 = cr0;
5843 vmx_set_cr0(vcpu, cr0); /* enter rmode */
5844 vmx_set_cr4(vcpu, 0);
5845 vmx_set_efer(vcpu, 0);
5846
5847 update_exception_bitmap(vcpu);
5848
5849 vpid_sync_context(vmx->vpid);
5850 }
5851
5852 /*
5853 * In nested virtualization, check if L1 asked to exit on external interrupts.
5854 * For most existing hypervisors, this will always return true.
5855 */
5856 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5857 {
5858 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5859 PIN_BASED_EXT_INTR_MASK;
5860 }
5861
5862 /*
5863 * In nested virtualization, check if L1 has set
5864 * VM_EXIT_ACK_INTR_ON_EXIT
5865 */
5866 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5867 {
5868 return get_vmcs12(vcpu)->vm_exit_controls &
5869 VM_EXIT_ACK_INTR_ON_EXIT;
5870 }
5871
5872 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5873 {
5874 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5875 PIN_BASED_NMI_EXITING;
5876 }
5877
5878 static void enable_irq_window(struct kvm_vcpu *vcpu)
5879 {
5880 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5881 CPU_BASED_VIRTUAL_INTR_PENDING);
5882 }
5883
5884 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5885 {
5886 if (!enable_vnmi ||
5887 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5888 enable_irq_window(vcpu);
5889 return;
5890 }
5891
5892 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5893 CPU_BASED_VIRTUAL_NMI_PENDING);
5894 }
5895
5896 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5897 {
5898 struct vcpu_vmx *vmx = to_vmx(vcpu);
5899 uint32_t intr;
5900 int irq = vcpu->arch.interrupt.nr;
5901
5902 trace_kvm_inj_virq(irq);
5903
5904 ++vcpu->stat.irq_injections;
5905 if (vmx->rmode.vm86_active) {
5906 int inc_eip = 0;
5907 if (vcpu->arch.interrupt.soft)
5908 inc_eip = vcpu->arch.event_exit_inst_len;
5909 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5910 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5911 return;
5912 }
5913 intr = irq | INTR_INFO_VALID_MASK;
5914 if (vcpu->arch.interrupt.soft) {
5915 intr |= INTR_TYPE_SOFT_INTR;
5916 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5917 vmx->vcpu.arch.event_exit_inst_len);
5918 } else
5919 intr |= INTR_TYPE_EXT_INTR;
5920 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5921 }
5922
5923 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5924 {
5925 struct vcpu_vmx *vmx = to_vmx(vcpu);
5926
5927 if (!enable_vnmi) {
5928 /*
5929 * Tracking the NMI-blocked state in software is built upon
5930 * finding the next open IRQ window. This, in turn, depends on
5931 * well-behaving guests: They have to keep IRQs disabled at
5932 * least as long as the NMI handler runs. Otherwise we may
5933 * cause NMI nesting, maybe breaking the guest. But as this is
5934 * highly unlikely, we can live with the residual risk.
5935 */
5936 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
5937 vmx->loaded_vmcs->vnmi_blocked_time = 0;
5938 }
5939
5940 ++vcpu->stat.nmi_injections;
5941 vmx->loaded_vmcs->nmi_known_unmasked = false;
5942
5943 if (vmx->rmode.vm86_active) {
5944 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5945 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5946 return;
5947 }
5948
5949 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5950 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5951 }
5952
5953 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5954 {
5955 struct vcpu_vmx *vmx = to_vmx(vcpu);
5956 bool masked;
5957
5958 if (!enable_vnmi)
5959 return vmx->loaded_vmcs->soft_vnmi_blocked;
5960 if (vmx->loaded_vmcs->nmi_known_unmasked)
5961 return false;
5962 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5963 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5964 return masked;
5965 }
5966
5967 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5968 {
5969 struct vcpu_vmx *vmx = to_vmx(vcpu);
5970
5971 if (!enable_vnmi) {
5972 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
5973 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
5974 vmx->loaded_vmcs->vnmi_blocked_time = 0;
5975 }
5976 } else {
5977 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5978 if (masked)
5979 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5980 GUEST_INTR_STATE_NMI);
5981 else
5982 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5983 GUEST_INTR_STATE_NMI);
5984 }
5985 }
5986
5987 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5988 {
5989 if (to_vmx(vcpu)->nested.nested_run_pending)
5990 return 0;
5991
5992 if (!enable_vnmi &&
5993 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
5994 return 0;
5995
5996 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5997 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5998 | GUEST_INTR_STATE_NMI));
5999 }
6000
6001 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
6002 {
6003 return (!to_vmx(vcpu)->nested.nested_run_pending &&
6004 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
6005 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6006 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
6007 }
6008
6009 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
6010 {
6011 int ret;
6012
6013 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
6014 PAGE_SIZE * 3);
6015 if (ret)
6016 return ret;
6017 kvm->arch.tss_addr = addr;
6018 return init_rmode_tss(kvm);
6019 }
6020
6021 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6022 {
6023 switch (vec) {
6024 case BP_VECTOR:
6025 /*
6026 * Update instruction length as we may reinject the exception
6027 * from user space while in guest debugging mode.
6028 */
6029 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
6030 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6031 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
6032 return false;
6033 /* fall through */
6034 case DB_VECTOR:
6035 if (vcpu->guest_debug &
6036 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
6037 return false;
6038 /* fall through */
6039 case DE_VECTOR:
6040 case OF_VECTOR:
6041 case BR_VECTOR:
6042 case UD_VECTOR:
6043 case DF_VECTOR:
6044 case SS_VECTOR:
6045 case GP_VECTOR:
6046 case MF_VECTOR:
6047 return true;
6048 break;
6049 }
6050 return false;
6051 }
6052
6053 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
6054 int vec, u32 err_code)
6055 {
6056 /*
6057 * Instruction with address size override prefix opcode 0x67
6058 * Cause the #SS fault with 0 error code in VM86 mode.
6059 */
6060 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
6061 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
6062 if (vcpu->arch.halt_request) {
6063 vcpu->arch.halt_request = 0;
6064 return kvm_vcpu_halt(vcpu);
6065 }
6066 return 1;
6067 }
6068 return 0;
6069 }
6070
6071 /*
6072 * Forward all other exceptions that are valid in real mode.
6073 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
6074 * the required debugging infrastructure rework.
6075 */
6076 kvm_queue_exception(vcpu, vec);
6077 return 1;
6078 }
6079
6080 /*
6081 * Trigger machine check on the host. We assume all the MSRs are already set up
6082 * by the CPU and that we still run on the same CPU as the MCE occurred on.
6083 * We pass a fake environment to the machine check handler because we want
6084 * the guest to be always treated like user space, no matter what context
6085 * it used internally.
6086 */
6087 static void kvm_machine_check(void)
6088 {
6089 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
6090 struct pt_regs regs = {
6091 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
6092 .flags = X86_EFLAGS_IF,
6093 };
6094
6095 do_machine_check(&regs, 0);
6096 #endif
6097 }
6098
6099 static int handle_machine_check(struct kvm_vcpu *vcpu)
6100 {
6101 /* already handled by vcpu_run */
6102 return 1;
6103 }
6104
6105 static int handle_exception(struct kvm_vcpu *vcpu)
6106 {
6107 struct vcpu_vmx *vmx = to_vmx(vcpu);
6108 struct kvm_run *kvm_run = vcpu->run;
6109 u32 intr_info, ex_no, error_code;
6110 unsigned long cr2, rip, dr6;
6111 u32 vect_info;
6112 enum emulation_result er;
6113
6114 vect_info = vmx->idt_vectoring_info;
6115 intr_info = vmx->exit_intr_info;
6116
6117 if (is_machine_check(intr_info))
6118 return handle_machine_check(vcpu);
6119
6120 if (is_nmi(intr_info))
6121 return 1; /* already handled by vmx_vcpu_run() */
6122
6123 if (is_invalid_opcode(intr_info)) {
6124 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
6125 if (er == EMULATE_USER_EXIT)
6126 return 0;
6127 if (er != EMULATE_DONE)
6128 kvm_queue_exception(vcpu, UD_VECTOR);
6129 return 1;
6130 }
6131
6132 error_code = 0;
6133 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6134 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6135
6136 /*
6137 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
6138 * MMIO, it is better to report an internal error.
6139 * See the comments in vmx_handle_exit.
6140 */
6141 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
6142 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
6143 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6144 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
6145 vcpu->run->internal.ndata = 3;
6146 vcpu->run->internal.data[0] = vect_info;
6147 vcpu->run->internal.data[1] = intr_info;
6148 vcpu->run->internal.data[2] = error_code;
6149 return 0;
6150 }
6151
6152 if (is_page_fault(intr_info)) {
6153 cr2 = vmcs_readl(EXIT_QUALIFICATION);
6154 /* EPT won't cause page fault directly */
6155 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
6156 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6157 }
6158
6159 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
6160
6161 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
6162 return handle_rmode_exception(vcpu, ex_no, error_code);
6163
6164 switch (ex_no) {
6165 case AC_VECTOR:
6166 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
6167 return 1;
6168 case DB_VECTOR:
6169 dr6 = vmcs_readl(EXIT_QUALIFICATION);
6170 if (!(vcpu->guest_debug &
6171 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
6172 vcpu->arch.dr6 &= ~15;
6173 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6174 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
6175 skip_emulated_instruction(vcpu);
6176
6177 kvm_queue_exception(vcpu, DB_VECTOR);
6178 return 1;
6179 }
6180 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
6181 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
6182 /* fall through */
6183 case BP_VECTOR:
6184 /*
6185 * Update instruction length as we may reinject #BP from
6186 * user space while in guest debugging mode. Reading it for
6187 * #DB as well causes no harm, it is not used in that case.
6188 */
6189 vmx->vcpu.arch.event_exit_inst_len =
6190 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6191 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6192 rip = kvm_rip_read(vcpu);
6193 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
6194 kvm_run->debug.arch.exception = ex_no;
6195 break;
6196 default:
6197 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
6198 kvm_run->ex.exception = ex_no;
6199 kvm_run->ex.error_code = error_code;
6200 break;
6201 }
6202 return 0;
6203 }
6204
6205 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6206 {
6207 ++vcpu->stat.irq_exits;
6208 return 1;
6209 }
6210
6211 static int handle_triple_fault(struct kvm_vcpu *vcpu)
6212 {
6213 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6214 vcpu->mmio_needed = 0;
6215 return 0;
6216 }
6217
6218 static int handle_io(struct kvm_vcpu *vcpu)
6219 {
6220 unsigned long exit_qualification;
6221 int size, in, string, ret;
6222 unsigned port;
6223
6224 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6225 string = (exit_qualification & 16) != 0;
6226 in = (exit_qualification & 8) != 0;
6227
6228 ++vcpu->stat.io_exits;
6229
6230 if (string || in)
6231 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6232
6233 port = exit_qualification >> 16;
6234 size = (exit_qualification & 7) + 1;
6235
6236 ret = kvm_skip_emulated_instruction(vcpu);
6237
6238 /*
6239 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6240 * KVM_EXIT_DEBUG here.
6241 */
6242 return kvm_fast_pio_out(vcpu, size, port) && ret;
6243 }
6244
6245 static void
6246 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
6247 {
6248 /*
6249 * Patch in the VMCALL instruction:
6250 */
6251 hypercall[0] = 0x0f;
6252 hypercall[1] = 0x01;
6253 hypercall[2] = 0xc1;
6254 }
6255
6256 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6257 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
6258 {
6259 if (is_guest_mode(vcpu)) {
6260 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6261 unsigned long orig_val = val;
6262
6263 /*
6264 * We get here when L2 changed cr0 in a way that did not change
6265 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6266 * but did change L0 shadowed bits. So we first calculate the
6267 * effective cr0 value that L1 would like to write into the
6268 * hardware. It consists of the L2-owned bits from the new
6269 * value combined with the L1-owned bits from L1's guest_cr0.
6270 */
6271 val = (val & ~vmcs12->cr0_guest_host_mask) |
6272 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
6273
6274 if (!nested_guest_cr0_valid(vcpu, val))
6275 return 1;
6276
6277 if (kvm_set_cr0(vcpu, val))
6278 return 1;
6279 vmcs_writel(CR0_READ_SHADOW, orig_val);
6280 return 0;
6281 } else {
6282 if (to_vmx(vcpu)->nested.vmxon &&
6283 !nested_host_cr0_valid(vcpu, val))
6284 return 1;
6285
6286 return kvm_set_cr0(vcpu, val);
6287 }
6288 }
6289
6290 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
6291 {
6292 if (is_guest_mode(vcpu)) {
6293 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6294 unsigned long orig_val = val;
6295
6296 /* analogously to handle_set_cr0 */
6297 val = (val & ~vmcs12->cr4_guest_host_mask) |
6298 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
6299 if (kvm_set_cr4(vcpu, val))
6300 return 1;
6301 vmcs_writel(CR4_READ_SHADOW, orig_val);
6302 return 0;
6303 } else
6304 return kvm_set_cr4(vcpu, val);
6305 }
6306
6307 static int handle_desc(struct kvm_vcpu *vcpu)
6308 {
6309 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
6310 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6311 }
6312
6313 static int handle_cr(struct kvm_vcpu *vcpu)
6314 {
6315 unsigned long exit_qualification, val;
6316 int cr;
6317 int reg;
6318 int err;
6319 int ret;
6320
6321 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6322 cr = exit_qualification & 15;
6323 reg = (exit_qualification >> 8) & 15;
6324 switch ((exit_qualification >> 4) & 3) {
6325 case 0: /* mov to cr */
6326 val = kvm_register_readl(vcpu, reg);
6327 trace_kvm_cr_write(cr, val);
6328 switch (cr) {
6329 case 0:
6330 err = handle_set_cr0(vcpu, val);
6331 return kvm_complete_insn_gp(vcpu, err);
6332 case 3:
6333 err = kvm_set_cr3(vcpu, val);
6334 return kvm_complete_insn_gp(vcpu, err);
6335 case 4:
6336 err = handle_set_cr4(vcpu, val);
6337 return kvm_complete_insn_gp(vcpu, err);
6338 case 8: {
6339 u8 cr8_prev = kvm_get_cr8(vcpu);
6340 u8 cr8 = (u8)val;
6341 err = kvm_set_cr8(vcpu, cr8);
6342 ret = kvm_complete_insn_gp(vcpu, err);
6343 if (lapic_in_kernel(vcpu))
6344 return ret;
6345 if (cr8_prev <= cr8)
6346 return ret;
6347 /*
6348 * TODO: we might be squashing a
6349 * KVM_GUESTDBG_SINGLESTEP-triggered
6350 * KVM_EXIT_DEBUG here.
6351 */
6352 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
6353 return 0;
6354 }
6355 }
6356 break;
6357 case 2: /* clts */
6358 WARN_ONCE(1, "Guest should always own CR0.TS");
6359 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6360 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6361 return kvm_skip_emulated_instruction(vcpu);
6362 case 1: /*mov from cr*/
6363 switch (cr) {
6364 case 3:
6365 val = kvm_read_cr3(vcpu);
6366 kvm_register_write(vcpu, reg, val);
6367 trace_kvm_cr_read(cr, val);
6368 return kvm_skip_emulated_instruction(vcpu);
6369 case 8:
6370 val = kvm_get_cr8(vcpu);
6371 kvm_register_write(vcpu, reg, val);
6372 trace_kvm_cr_read(cr, val);
6373 return kvm_skip_emulated_instruction(vcpu);
6374 }
6375 break;
6376 case 3: /* lmsw */
6377 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
6378 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
6379 kvm_lmsw(vcpu, val);
6380
6381 return kvm_skip_emulated_instruction(vcpu);
6382 default:
6383 break;
6384 }
6385 vcpu->run->exit_reason = 0;
6386 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6387 (int)(exit_qualification >> 4) & 3, cr);
6388 return 0;
6389 }
6390
6391 static int handle_dr(struct kvm_vcpu *vcpu)
6392 {
6393 unsigned long exit_qualification;
6394 int dr, dr7, reg;
6395
6396 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6397 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6398
6399 /* First, if DR does not exist, trigger UD */
6400 if (!kvm_require_dr(vcpu, dr))
6401 return 1;
6402
6403 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6404 if (!kvm_require_cpl(vcpu, 0))
6405 return 1;
6406 dr7 = vmcs_readl(GUEST_DR7);
6407 if (dr7 & DR7_GD) {
6408 /*
6409 * As the vm-exit takes precedence over the debug trap, we
6410 * need to emulate the latter, either for the host or the
6411 * guest debugging itself.
6412 */
6413 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6414 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6415 vcpu->run->debug.arch.dr7 = dr7;
6416 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6417 vcpu->run->debug.arch.exception = DB_VECTOR;
6418 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
6419 return 0;
6420 } else {
6421 vcpu->arch.dr6 &= ~15;
6422 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
6423 kvm_queue_exception(vcpu, DB_VECTOR);
6424 return 1;
6425 }
6426 }
6427
6428 if (vcpu->guest_debug == 0) {
6429 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6430 CPU_BASED_MOV_DR_EXITING);
6431
6432 /*
6433 * No more DR vmexits; force a reload of the debug registers
6434 * and reenter on this instruction. The next vmexit will
6435 * retrieve the full state of the debug registers.
6436 */
6437 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6438 return 1;
6439 }
6440
6441 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6442 if (exit_qualification & TYPE_MOV_FROM_DR) {
6443 unsigned long val;
6444
6445 if (kvm_get_dr(vcpu, dr, &val))
6446 return 1;
6447 kvm_register_write(vcpu, reg, val);
6448 } else
6449 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6450 return 1;
6451
6452 return kvm_skip_emulated_instruction(vcpu);
6453 }
6454
6455 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6456 {
6457 return vcpu->arch.dr6;
6458 }
6459
6460 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6461 {
6462 }
6463
6464 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6465 {
6466 get_debugreg(vcpu->arch.db[0], 0);
6467 get_debugreg(vcpu->arch.db[1], 1);
6468 get_debugreg(vcpu->arch.db[2], 2);
6469 get_debugreg(vcpu->arch.db[3], 3);
6470 get_debugreg(vcpu->arch.dr6, 6);
6471 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6472
6473 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6474 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6475 }
6476
6477 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6478 {
6479 vmcs_writel(GUEST_DR7, val);
6480 }
6481
6482 static int handle_cpuid(struct kvm_vcpu *vcpu)
6483 {
6484 return kvm_emulate_cpuid(vcpu);
6485 }
6486
6487 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6488 {
6489 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6490 struct msr_data msr_info;
6491
6492 msr_info.index = ecx;
6493 msr_info.host_initiated = false;
6494 if (vmx_get_msr(vcpu, &msr_info)) {
6495 trace_kvm_msr_read_ex(ecx);
6496 kvm_inject_gp(vcpu, 0);
6497 return 1;
6498 }
6499
6500 trace_kvm_msr_read(ecx, msr_info.data);
6501
6502 /* FIXME: handling of bits 32:63 of rax, rdx */
6503 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6504 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6505 return kvm_skip_emulated_instruction(vcpu);
6506 }
6507
6508 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6509 {
6510 struct msr_data msr;
6511 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6512 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6513 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6514
6515 msr.data = data;
6516 msr.index = ecx;
6517 msr.host_initiated = false;
6518 if (kvm_set_msr(vcpu, &msr) != 0) {
6519 trace_kvm_msr_write_ex(ecx, data);
6520 kvm_inject_gp(vcpu, 0);
6521 return 1;
6522 }
6523
6524 trace_kvm_msr_write(ecx, data);
6525 return kvm_skip_emulated_instruction(vcpu);
6526 }
6527
6528 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6529 {
6530 kvm_apic_update_ppr(vcpu);
6531 return 1;
6532 }
6533
6534 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6535 {
6536 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6537 CPU_BASED_VIRTUAL_INTR_PENDING);
6538
6539 kvm_make_request(KVM_REQ_EVENT, vcpu);
6540
6541 ++vcpu->stat.irq_window_exits;
6542 return 1;
6543 }
6544
6545 static int handle_halt(struct kvm_vcpu *vcpu)
6546 {
6547 return kvm_emulate_halt(vcpu);
6548 }
6549
6550 static int handle_vmcall(struct kvm_vcpu *vcpu)
6551 {
6552 return kvm_emulate_hypercall(vcpu);
6553 }
6554
6555 static int handle_invd(struct kvm_vcpu *vcpu)
6556 {
6557 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6558 }
6559
6560 static int handle_invlpg(struct kvm_vcpu *vcpu)
6561 {
6562 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6563
6564 kvm_mmu_invlpg(vcpu, exit_qualification);
6565 return kvm_skip_emulated_instruction(vcpu);
6566 }
6567
6568 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6569 {
6570 int err;
6571
6572 err = kvm_rdpmc(vcpu);
6573 return kvm_complete_insn_gp(vcpu, err);
6574 }
6575
6576 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6577 {
6578 return kvm_emulate_wbinvd(vcpu);
6579 }
6580
6581 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6582 {
6583 u64 new_bv = kvm_read_edx_eax(vcpu);
6584 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6585
6586 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6587 return kvm_skip_emulated_instruction(vcpu);
6588 return 1;
6589 }
6590
6591 static int handle_xsaves(struct kvm_vcpu *vcpu)
6592 {
6593 kvm_skip_emulated_instruction(vcpu);
6594 WARN(1, "this should never happen\n");
6595 return 1;
6596 }
6597
6598 static int handle_xrstors(struct kvm_vcpu *vcpu)
6599 {
6600 kvm_skip_emulated_instruction(vcpu);
6601 WARN(1, "this should never happen\n");
6602 return 1;
6603 }
6604
6605 static int handle_apic_access(struct kvm_vcpu *vcpu)
6606 {
6607 if (likely(fasteoi)) {
6608 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6609 int access_type, offset;
6610
6611 access_type = exit_qualification & APIC_ACCESS_TYPE;
6612 offset = exit_qualification & APIC_ACCESS_OFFSET;
6613 /*
6614 * Sane guest uses MOV to write EOI, with written value
6615 * not cared. So make a short-circuit here by avoiding
6616 * heavy instruction emulation.
6617 */
6618 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6619 (offset == APIC_EOI)) {
6620 kvm_lapic_set_eoi(vcpu);
6621 return kvm_skip_emulated_instruction(vcpu);
6622 }
6623 }
6624 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6625 }
6626
6627 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6628 {
6629 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6630 int vector = exit_qualification & 0xff;
6631
6632 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6633 kvm_apic_set_eoi_accelerated(vcpu, vector);
6634 return 1;
6635 }
6636
6637 static int handle_apic_write(struct kvm_vcpu *vcpu)
6638 {
6639 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6640 u32 offset = exit_qualification & 0xfff;
6641
6642 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6643 kvm_apic_write_nodecode(vcpu, offset);
6644 return 1;
6645 }
6646
6647 static int handle_task_switch(struct kvm_vcpu *vcpu)
6648 {
6649 struct vcpu_vmx *vmx = to_vmx(vcpu);
6650 unsigned long exit_qualification;
6651 bool has_error_code = false;
6652 u32 error_code = 0;
6653 u16 tss_selector;
6654 int reason, type, idt_v, idt_index;
6655
6656 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6657 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6658 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6659
6660 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6661
6662 reason = (u32)exit_qualification >> 30;
6663 if (reason == TASK_SWITCH_GATE && idt_v) {
6664 switch (type) {
6665 case INTR_TYPE_NMI_INTR:
6666 vcpu->arch.nmi_injected = false;
6667 vmx_set_nmi_mask(vcpu, true);
6668 break;
6669 case INTR_TYPE_EXT_INTR:
6670 case INTR_TYPE_SOFT_INTR:
6671 kvm_clear_interrupt_queue(vcpu);
6672 break;
6673 case INTR_TYPE_HARD_EXCEPTION:
6674 if (vmx->idt_vectoring_info &
6675 VECTORING_INFO_DELIVER_CODE_MASK) {
6676 has_error_code = true;
6677 error_code =
6678 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6679 }
6680 /* fall through */
6681 case INTR_TYPE_SOFT_EXCEPTION:
6682 kvm_clear_exception_queue(vcpu);
6683 break;
6684 default:
6685 break;
6686 }
6687 }
6688 tss_selector = exit_qualification;
6689
6690 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6691 type != INTR_TYPE_EXT_INTR &&
6692 type != INTR_TYPE_NMI_INTR))
6693 skip_emulated_instruction(vcpu);
6694
6695 if (kvm_task_switch(vcpu, tss_selector,
6696 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6697 has_error_code, error_code) == EMULATE_FAIL) {
6698 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6699 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6700 vcpu->run->internal.ndata = 0;
6701 return 0;
6702 }
6703
6704 /*
6705 * TODO: What about debug traps on tss switch?
6706 * Are we supposed to inject them and update dr6?
6707 */
6708
6709 return 1;
6710 }
6711
6712 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6713 {
6714 unsigned long exit_qualification;
6715 gpa_t gpa;
6716 u64 error_code;
6717
6718 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6719
6720 /*
6721 * EPT violation happened while executing iret from NMI,
6722 * "blocked by NMI" bit has to be set before next VM entry.
6723 * There are errata that may cause this bit to not be set:
6724 * AAK134, BY25.
6725 */
6726 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6727 enable_vnmi &&
6728 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6729 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6730
6731 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6732 trace_kvm_page_fault(gpa, exit_qualification);
6733
6734 /* Is it a read fault? */
6735 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6736 ? PFERR_USER_MASK : 0;
6737 /* Is it a write fault? */
6738 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6739 ? PFERR_WRITE_MASK : 0;
6740 /* Is it a fetch fault? */
6741 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6742 ? PFERR_FETCH_MASK : 0;
6743 /* ept page table entry is present? */
6744 error_code |= (exit_qualification &
6745 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6746 EPT_VIOLATION_EXECUTABLE))
6747 ? PFERR_PRESENT_MASK : 0;
6748
6749 error_code |= (exit_qualification & 0x100) != 0 ?
6750 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
6751
6752 vcpu->arch.exit_qualification = exit_qualification;
6753 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6754 }
6755
6756 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6757 {
6758 int ret;
6759 gpa_t gpa;
6760
6761 /*
6762 * A nested guest cannot optimize MMIO vmexits, because we have an
6763 * nGPA here instead of the required GPA.
6764 */
6765 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6766 if (!is_guest_mode(vcpu) &&
6767 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6768 trace_kvm_fast_mmio(gpa);
6769 /*
6770 * Doing kvm_skip_emulated_instruction() depends on undefined
6771 * behavior: Intel's manual doesn't mandate
6772 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
6773 * occurs and while on real hardware it was observed to be set,
6774 * other hypervisors (namely Hyper-V) don't set it, we end up
6775 * advancing IP with some random value. Disable fast mmio when
6776 * running nested and keep it for real hardware in hope that
6777 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
6778 */
6779 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
6780 return kvm_skip_emulated_instruction(vcpu);
6781 else
6782 return x86_emulate_instruction(vcpu, gpa, EMULTYPE_SKIP,
6783 NULL, 0) == EMULATE_DONE;
6784 }
6785
6786 ret = kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
6787 if (ret >= 0)
6788 return ret;
6789
6790 /* It is the real ept misconfig */
6791 WARN_ON(1);
6792
6793 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6794 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6795
6796 return 0;
6797 }
6798
6799 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6800 {
6801 WARN_ON_ONCE(!enable_vnmi);
6802 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6803 CPU_BASED_VIRTUAL_NMI_PENDING);
6804 ++vcpu->stat.nmi_window_exits;
6805 kvm_make_request(KVM_REQ_EVENT, vcpu);
6806
6807 return 1;
6808 }
6809
6810 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6811 {
6812 struct vcpu_vmx *vmx = to_vmx(vcpu);
6813 enum emulation_result err = EMULATE_DONE;
6814 int ret = 1;
6815 u32 cpu_exec_ctrl;
6816 bool intr_window_requested;
6817 unsigned count = 130;
6818
6819 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6820 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6821
6822 while (vmx->emulation_required && count-- != 0) {
6823 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6824 return handle_interrupt_window(&vmx->vcpu);
6825
6826 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
6827 return 1;
6828
6829 err = emulate_instruction(vcpu, 0);
6830
6831 if (err == EMULATE_USER_EXIT) {
6832 ++vcpu->stat.mmio_exits;
6833 ret = 0;
6834 goto out;
6835 }
6836
6837 if (err != EMULATE_DONE) {
6838 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6839 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6840 vcpu->run->internal.ndata = 0;
6841 return 0;
6842 }
6843
6844 if (vcpu->arch.halt_request) {
6845 vcpu->arch.halt_request = 0;
6846 ret = kvm_vcpu_halt(vcpu);
6847 goto out;
6848 }
6849
6850 if (signal_pending(current))
6851 goto out;
6852 if (need_resched())
6853 schedule();
6854 }
6855
6856 out:
6857 return ret;
6858 }
6859
6860 static int __grow_ple_window(int val)
6861 {
6862 if (ple_window_grow < 1)
6863 return ple_window;
6864
6865 val = min(val, ple_window_actual_max);
6866
6867 if (ple_window_grow < ple_window)
6868 val *= ple_window_grow;
6869 else
6870 val += ple_window_grow;
6871
6872 return val;
6873 }
6874
6875 static int __shrink_ple_window(int val, int modifier, int minimum)
6876 {
6877 if (modifier < 1)
6878 return ple_window;
6879
6880 if (modifier < ple_window)
6881 val /= modifier;
6882 else
6883 val -= modifier;
6884
6885 return max(val, minimum);
6886 }
6887
6888 static void grow_ple_window(struct kvm_vcpu *vcpu)
6889 {
6890 struct vcpu_vmx *vmx = to_vmx(vcpu);
6891 int old = vmx->ple_window;
6892
6893 vmx->ple_window = __grow_ple_window(old);
6894
6895 if (vmx->ple_window != old)
6896 vmx->ple_window_dirty = true;
6897
6898 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6899 }
6900
6901 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6902 {
6903 struct vcpu_vmx *vmx = to_vmx(vcpu);
6904 int old = vmx->ple_window;
6905
6906 vmx->ple_window = __shrink_ple_window(old,
6907 ple_window_shrink, ple_window);
6908
6909 if (vmx->ple_window != old)
6910 vmx->ple_window_dirty = true;
6911
6912 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6913 }
6914
6915 /*
6916 * ple_window_actual_max is computed to be one grow_ple_window() below
6917 * ple_window_max. (See __grow_ple_window for the reason.)
6918 * This prevents overflows, because ple_window_max is int.
6919 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6920 * this process.
6921 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6922 */
6923 static void update_ple_window_actual_max(void)
6924 {
6925 ple_window_actual_max =
6926 __shrink_ple_window(max(ple_window_max, ple_window),
6927 ple_window_grow, INT_MIN);
6928 }
6929
6930 /*
6931 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6932 */
6933 static void wakeup_handler(void)
6934 {
6935 struct kvm_vcpu *vcpu;
6936 int cpu = smp_processor_id();
6937
6938 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6939 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6940 blocked_vcpu_list) {
6941 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6942
6943 if (pi_test_on(pi_desc) == 1)
6944 kvm_vcpu_kick(vcpu);
6945 }
6946 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6947 }
6948
6949 void vmx_enable_tdp(void)
6950 {
6951 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6952 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6953 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6954 0ull, VMX_EPT_EXECUTABLE_MASK,
6955 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6956 VMX_EPT_RWX_MASK, 0ull);
6957
6958 ept_set_mmio_spte_mask();
6959 kvm_enable_tdp();
6960 }
6961
6962 static __init int hardware_setup(void)
6963 {
6964 int r = -ENOMEM, i;
6965
6966 rdmsrl_safe(MSR_EFER, &host_efer);
6967
6968 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6969 kvm_define_shared_msr(i, vmx_msr_index[i]);
6970
6971 for (i = 0; i < VMX_BITMAP_NR; i++) {
6972 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6973 if (!vmx_bitmap[i])
6974 goto out;
6975 }
6976
6977 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6978 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6979
6980 if (setup_vmcs_config(&vmcs_config) < 0) {
6981 r = -EIO;
6982 goto out;
6983 }
6984
6985 if (boot_cpu_has(X86_FEATURE_NX))
6986 kvm_enable_efer_bits(EFER_NX);
6987
6988 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6989 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6990 enable_vpid = 0;
6991
6992 if (!cpu_has_vmx_ept() ||
6993 !cpu_has_vmx_ept_4levels() ||
6994 !cpu_has_vmx_ept_mt_wb() ||
6995 !cpu_has_vmx_invept_global())
6996 enable_ept = 0;
6997
6998 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
6999 enable_ept_ad_bits = 0;
7000
7001 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7002 enable_unrestricted_guest = 0;
7003
7004 if (!cpu_has_vmx_flexpriority())
7005 flexpriority_enabled = 0;
7006
7007 if (!cpu_has_virtual_nmis())
7008 enable_vnmi = 0;
7009
7010 /*
7011 * set_apic_access_page_addr() is used to reload apic access
7012 * page upon invalidation. No need to do anything if not
7013 * using the APIC_ACCESS_ADDR VMCS field.
7014 */
7015 if (!flexpriority_enabled)
7016 kvm_x86_ops->set_apic_access_page_addr = NULL;
7017
7018 if (!cpu_has_vmx_tpr_shadow())
7019 kvm_x86_ops->update_cr8_intercept = NULL;
7020
7021 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7022 kvm_disable_largepages();
7023
7024 if (!cpu_has_vmx_ple()) {
7025 ple_gap = 0;
7026 ple_window = 0;
7027 ple_window_grow = 0;
7028 ple_window_max = 0;
7029 ple_window_shrink = 0;
7030 }
7031
7032 if (!cpu_has_vmx_apicv()) {
7033 enable_apicv = 0;
7034 kvm_x86_ops->sync_pir_to_irr = NULL;
7035 }
7036
7037 if (cpu_has_vmx_tsc_scaling()) {
7038 kvm_has_tsc_control = true;
7039 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7040 kvm_tsc_scaling_ratio_frac_bits = 48;
7041 }
7042
7043 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7044
7045 if (enable_ept)
7046 vmx_enable_tdp();
7047 else
7048 kvm_disable_tdp();
7049
7050 update_ple_window_actual_max();
7051
7052 /*
7053 * Only enable PML when hardware supports PML feature, and both EPT
7054 * and EPT A/D bit features are enabled -- PML depends on them to work.
7055 */
7056 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7057 enable_pml = 0;
7058
7059 if (!enable_pml) {
7060 kvm_x86_ops->slot_enable_log_dirty = NULL;
7061 kvm_x86_ops->slot_disable_log_dirty = NULL;
7062 kvm_x86_ops->flush_log_dirty = NULL;
7063 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7064 }
7065
7066 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7067 u64 vmx_msr;
7068
7069 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7070 cpu_preemption_timer_multi =
7071 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7072 } else {
7073 kvm_x86_ops->set_hv_timer = NULL;
7074 kvm_x86_ops->cancel_hv_timer = NULL;
7075 }
7076
7077 if (!cpu_has_vmx_shadow_vmcs())
7078 enable_shadow_vmcs = 0;
7079 if (enable_shadow_vmcs)
7080 init_vmcs_shadow_fields();
7081
7082 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7083
7084 kvm_mce_cap_supported |= MCG_LMCE_P;
7085
7086 return alloc_kvm_area();
7087
7088 out:
7089 for (i = 0; i < VMX_BITMAP_NR; i++)
7090 free_page((unsigned long)vmx_bitmap[i]);
7091
7092 return r;
7093 }
7094
7095 static __exit void hardware_unsetup(void)
7096 {
7097 int i;
7098
7099 for (i = 0; i < VMX_BITMAP_NR; i++)
7100 free_page((unsigned long)vmx_bitmap[i]);
7101
7102 free_kvm_area();
7103 }
7104
7105 /*
7106 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
7107 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
7108 */
7109 static int handle_pause(struct kvm_vcpu *vcpu)
7110 {
7111 if (ple_gap)
7112 grow_ple_window(vcpu);
7113
7114 /*
7115 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
7116 * VM-execution control is ignored if CPL > 0. OTOH, KVM
7117 * never set PAUSE_EXITING and just set PLE if supported,
7118 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
7119 */
7120 kvm_vcpu_on_spin(vcpu, true);
7121 return kvm_skip_emulated_instruction(vcpu);
7122 }
7123
7124 static int handle_nop(struct kvm_vcpu *vcpu)
7125 {
7126 return kvm_skip_emulated_instruction(vcpu);
7127 }
7128
7129 static int handle_mwait(struct kvm_vcpu *vcpu)
7130 {
7131 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
7132 return handle_nop(vcpu);
7133 }
7134
7135 static int handle_invalid_op(struct kvm_vcpu *vcpu)
7136 {
7137 kvm_queue_exception(vcpu, UD_VECTOR);
7138 return 1;
7139 }
7140
7141 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
7142 {
7143 return 1;
7144 }
7145
7146 static int handle_monitor(struct kvm_vcpu *vcpu)
7147 {
7148 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
7149 return handle_nop(vcpu);
7150 }
7151
7152 /*
7153 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7154 * set the success or error code of an emulated VMX instruction, as specified
7155 * by Vol 2B, VMX Instruction Reference, "Conventions".
7156 */
7157 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
7158 {
7159 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
7160 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7161 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
7162 }
7163
7164 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
7165 {
7166 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7167 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
7168 X86_EFLAGS_SF | X86_EFLAGS_OF))
7169 | X86_EFLAGS_CF);
7170 }
7171
7172 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
7173 u32 vm_instruction_error)
7174 {
7175 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
7176 /*
7177 * failValid writes the error number to the current VMCS, which
7178 * can't be done there isn't a current VMCS.
7179 */
7180 nested_vmx_failInvalid(vcpu);
7181 return;
7182 }
7183 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7184 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7185 X86_EFLAGS_SF | X86_EFLAGS_OF))
7186 | X86_EFLAGS_ZF);
7187 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
7188 /*
7189 * We don't need to force a shadow sync because
7190 * VM_INSTRUCTION_ERROR is not shadowed
7191 */
7192 }
7193
7194 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
7195 {
7196 /* TODO: not to reset guest simply here. */
7197 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7198 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
7199 }
7200
7201 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
7202 {
7203 struct vcpu_vmx *vmx =
7204 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
7205
7206 vmx->nested.preemption_timer_expired = true;
7207 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
7208 kvm_vcpu_kick(&vmx->vcpu);
7209
7210 return HRTIMER_NORESTART;
7211 }
7212
7213 /*
7214 * Decode the memory-address operand of a vmx instruction, as recorded on an
7215 * exit caused by such an instruction (run by a guest hypervisor).
7216 * On success, returns 0. When the operand is invalid, returns 1 and throws
7217 * #UD or #GP.
7218 */
7219 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
7220 unsigned long exit_qualification,
7221 u32 vmx_instruction_info, bool wr, gva_t *ret)
7222 {
7223 gva_t off;
7224 bool exn;
7225 struct kvm_segment s;
7226
7227 /*
7228 * According to Vol. 3B, "Information for VM Exits Due to Instruction
7229 * Execution", on an exit, vmx_instruction_info holds most of the
7230 * addressing components of the operand. Only the displacement part
7231 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7232 * For how an actual address is calculated from all these components,
7233 * refer to Vol. 1, "Operand Addressing".
7234 */
7235 int scaling = vmx_instruction_info & 3;
7236 int addr_size = (vmx_instruction_info >> 7) & 7;
7237 bool is_reg = vmx_instruction_info & (1u << 10);
7238 int seg_reg = (vmx_instruction_info >> 15) & 7;
7239 int index_reg = (vmx_instruction_info >> 18) & 0xf;
7240 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
7241 int base_reg = (vmx_instruction_info >> 23) & 0xf;
7242 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
7243
7244 if (is_reg) {
7245 kvm_queue_exception(vcpu, UD_VECTOR);
7246 return 1;
7247 }
7248
7249 /* Addr = segment_base + offset */
7250 /* offset = base + [index * scale] + displacement */
7251 off = exit_qualification; /* holds the displacement */
7252 if (base_is_valid)
7253 off += kvm_register_read(vcpu, base_reg);
7254 if (index_is_valid)
7255 off += kvm_register_read(vcpu, index_reg)<<scaling;
7256 vmx_get_segment(vcpu, &s, seg_reg);
7257 *ret = s.base + off;
7258
7259 if (addr_size == 1) /* 32 bit */
7260 *ret &= 0xffffffff;
7261
7262 /* Checks for #GP/#SS exceptions. */
7263 exn = false;
7264 if (is_long_mode(vcpu)) {
7265 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7266 * non-canonical form. This is the only check on the memory
7267 * destination for long mode!
7268 */
7269 exn = is_noncanonical_address(*ret, vcpu);
7270 } else if (is_protmode(vcpu)) {
7271 /* Protected mode: apply checks for segment validity in the
7272 * following order:
7273 * - segment type check (#GP(0) may be thrown)
7274 * - usability check (#GP(0)/#SS(0))
7275 * - limit check (#GP(0)/#SS(0))
7276 */
7277 if (wr)
7278 /* #GP(0) if the destination operand is located in a
7279 * read-only data segment or any code segment.
7280 */
7281 exn = ((s.type & 0xa) == 0 || (s.type & 8));
7282 else
7283 /* #GP(0) if the source operand is located in an
7284 * execute-only code segment
7285 */
7286 exn = ((s.type & 0xa) == 8);
7287 if (exn) {
7288 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7289 return 1;
7290 }
7291 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7292 */
7293 exn = (s.unusable != 0);
7294 /* Protected mode: #GP(0)/#SS(0) if the memory
7295 * operand is outside the segment limit.
7296 */
7297 exn = exn || (off + sizeof(u64) > s.limit);
7298 }
7299 if (exn) {
7300 kvm_queue_exception_e(vcpu,
7301 seg_reg == VCPU_SREG_SS ?
7302 SS_VECTOR : GP_VECTOR,
7303 0);
7304 return 1;
7305 }
7306
7307 return 0;
7308 }
7309
7310 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
7311 {
7312 gva_t gva;
7313 struct x86_exception e;
7314
7315 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7316 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7317 return 1;
7318
7319 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
7320 sizeof(*vmpointer), &e)) {
7321 kvm_inject_page_fault(vcpu, &e);
7322 return 1;
7323 }
7324
7325 return 0;
7326 }
7327
7328 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7329 {
7330 struct vcpu_vmx *vmx = to_vmx(vcpu);
7331 struct vmcs *shadow_vmcs;
7332 int r;
7333
7334 r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
7335 if (r < 0)
7336 goto out_vmcs02;
7337
7338 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7339 if (!vmx->nested.cached_vmcs12)
7340 goto out_cached_vmcs12;
7341
7342 if (enable_shadow_vmcs) {
7343 shadow_vmcs = alloc_vmcs();
7344 if (!shadow_vmcs)
7345 goto out_shadow_vmcs;
7346 /* mark vmcs as shadow */
7347 shadow_vmcs->revision_id |= (1u << 31);
7348 /* init shadow vmcs */
7349 vmcs_clear(shadow_vmcs);
7350 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7351 }
7352
7353 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7354 HRTIMER_MODE_REL_PINNED);
7355 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7356
7357 vmx->nested.vmxon = true;
7358 return 0;
7359
7360 out_shadow_vmcs:
7361 kfree(vmx->nested.cached_vmcs12);
7362
7363 out_cached_vmcs12:
7364 free_loaded_vmcs(&vmx->nested.vmcs02);
7365
7366 out_vmcs02:
7367 return -ENOMEM;
7368 }
7369
7370 /*
7371 * Emulate the VMXON instruction.
7372 * Currently, we just remember that VMX is active, and do not save or even
7373 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7374 * do not currently need to store anything in that guest-allocated memory
7375 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7376 * argument is different from the VMXON pointer (which the spec says they do).
7377 */
7378 static int handle_vmon(struct kvm_vcpu *vcpu)
7379 {
7380 int ret;
7381 gpa_t vmptr;
7382 struct page *page;
7383 struct vcpu_vmx *vmx = to_vmx(vcpu);
7384 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7385 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7386
7387 /*
7388 * The Intel VMX Instruction Reference lists a bunch of bits that are
7389 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7390 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7391 * Otherwise, we should fail with #UD. But most faulting conditions
7392 * have already been checked by hardware, prior to the VM-exit for
7393 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7394 * that bit set to 1 in non-root mode.
7395 */
7396 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7397 kvm_queue_exception(vcpu, UD_VECTOR);
7398 return 1;
7399 }
7400
7401 if (vmx->nested.vmxon) {
7402 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7403 return kvm_skip_emulated_instruction(vcpu);
7404 }
7405
7406 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7407 != VMXON_NEEDED_FEATURES) {
7408 kvm_inject_gp(vcpu, 0);
7409 return 1;
7410 }
7411
7412 if (nested_vmx_get_vmptr(vcpu, &vmptr))
7413 return 1;
7414
7415 /*
7416 * SDM 3: 24.11.5
7417 * The first 4 bytes of VMXON region contain the supported
7418 * VMCS revision identifier
7419 *
7420 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7421 * which replaces physical address width with 32
7422 */
7423 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7424 nested_vmx_failInvalid(vcpu);
7425 return kvm_skip_emulated_instruction(vcpu);
7426 }
7427
7428 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7429 if (is_error_page(page)) {
7430 nested_vmx_failInvalid(vcpu);
7431 return kvm_skip_emulated_instruction(vcpu);
7432 }
7433 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7434 kunmap(page);
7435 kvm_release_page_clean(page);
7436 nested_vmx_failInvalid(vcpu);
7437 return kvm_skip_emulated_instruction(vcpu);
7438 }
7439 kunmap(page);
7440 kvm_release_page_clean(page);
7441
7442 vmx->nested.vmxon_ptr = vmptr;
7443 ret = enter_vmx_operation(vcpu);
7444 if (ret)
7445 return ret;
7446
7447 nested_vmx_succeed(vcpu);
7448 return kvm_skip_emulated_instruction(vcpu);
7449 }
7450
7451 /*
7452 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7453 * for running VMX instructions (except VMXON, whose prerequisites are
7454 * slightly different). It also specifies what exception to inject otherwise.
7455 * Note that many of these exceptions have priority over VM exits, so they
7456 * don't have to be checked again here.
7457 */
7458 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7459 {
7460 if (!to_vmx(vcpu)->nested.vmxon) {
7461 kvm_queue_exception(vcpu, UD_VECTOR);
7462 return 0;
7463 }
7464 return 1;
7465 }
7466
7467 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
7468 {
7469 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
7470 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7471 }
7472
7473 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7474 {
7475 if (vmx->nested.current_vmptr == -1ull)
7476 return;
7477
7478 if (enable_shadow_vmcs) {
7479 /* copy to memory all shadowed fields in case
7480 they were modified */
7481 copy_shadow_to_vmcs12(vmx);
7482 vmx->nested.sync_shadow_vmcs = false;
7483 vmx_disable_shadow_vmcs(vmx);
7484 }
7485 vmx->nested.posted_intr_nv = -1;
7486
7487 /* Flush VMCS12 to guest memory */
7488 kvm_vcpu_write_guest_page(&vmx->vcpu,
7489 vmx->nested.current_vmptr >> PAGE_SHIFT,
7490 vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
7491
7492 vmx->nested.current_vmptr = -1ull;
7493 }
7494
7495 /*
7496 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7497 * just stops using VMX.
7498 */
7499 static void free_nested(struct vcpu_vmx *vmx)
7500 {
7501 if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
7502 return;
7503
7504 vmx->nested.vmxon = false;
7505 vmx->nested.smm.vmxon = false;
7506 free_vpid(vmx->nested.vpid02);
7507 vmx->nested.posted_intr_nv = -1;
7508 vmx->nested.current_vmptr = -1ull;
7509 if (enable_shadow_vmcs) {
7510 vmx_disable_shadow_vmcs(vmx);
7511 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7512 free_vmcs(vmx->vmcs01.shadow_vmcs);
7513 vmx->vmcs01.shadow_vmcs = NULL;
7514 }
7515 kfree(vmx->nested.cached_vmcs12);
7516 /* Unpin physical memory we referred to in the vmcs02 */
7517 if (vmx->nested.apic_access_page) {
7518 kvm_release_page_dirty(vmx->nested.apic_access_page);
7519 vmx->nested.apic_access_page = NULL;
7520 }
7521 if (vmx->nested.virtual_apic_page) {
7522 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
7523 vmx->nested.virtual_apic_page = NULL;
7524 }
7525 if (vmx->nested.pi_desc_page) {
7526 kunmap(vmx->nested.pi_desc_page);
7527 kvm_release_page_dirty(vmx->nested.pi_desc_page);
7528 vmx->nested.pi_desc_page = NULL;
7529 vmx->nested.pi_desc = NULL;
7530 }
7531
7532 free_loaded_vmcs(&vmx->nested.vmcs02);
7533 }
7534
7535 /* Emulate the VMXOFF instruction */
7536 static int handle_vmoff(struct kvm_vcpu *vcpu)
7537 {
7538 if (!nested_vmx_check_permission(vcpu))
7539 return 1;
7540 free_nested(to_vmx(vcpu));
7541 nested_vmx_succeed(vcpu);
7542 return kvm_skip_emulated_instruction(vcpu);
7543 }
7544
7545 /* Emulate the VMCLEAR instruction */
7546 static int handle_vmclear(struct kvm_vcpu *vcpu)
7547 {
7548 struct vcpu_vmx *vmx = to_vmx(vcpu);
7549 u32 zero = 0;
7550 gpa_t vmptr;
7551
7552 if (!nested_vmx_check_permission(vcpu))
7553 return 1;
7554
7555 if (nested_vmx_get_vmptr(vcpu, &vmptr))
7556 return 1;
7557
7558 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7559 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7560 return kvm_skip_emulated_instruction(vcpu);
7561 }
7562
7563 if (vmptr == vmx->nested.vmxon_ptr) {
7564 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7565 return kvm_skip_emulated_instruction(vcpu);
7566 }
7567
7568 if (vmptr == vmx->nested.current_vmptr)
7569 nested_release_vmcs12(vmx);
7570
7571 kvm_vcpu_write_guest(vcpu,
7572 vmptr + offsetof(struct vmcs12, launch_state),
7573 &zero, sizeof(zero));
7574
7575 nested_vmx_succeed(vcpu);
7576 return kvm_skip_emulated_instruction(vcpu);
7577 }
7578
7579 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7580
7581 /* Emulate the VMLAUNCH instruction */
7582 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7583 {
7584 return nested_vmx_run(vcpu, true);
7585 }
7586
7587 /* Emulate the VMRESUME instruction */
7588 static int handle_vmresume(struct kvm_vcpu *vcpu)
7589 {
7590
7591 return nested_vmx_run(vcpu, false);
7592 }
7593
7594 /*
7595 * Read a vmcs12 field. Since these can have varying lengths and we return
7596 * one type, we chose the biggest type (u64) and zero-extend the return value
7597 * to that size. Note that the caller, handle_vmread, might need to use only
7598 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7599 * 64-bit fields are to be returned).
7600 */
7601 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7602 unsigned long field, u64 *ret)
7603 {
7604 short offset = vmcs_field_to_offset(field);
7605 char *p;
7606
7607 if (offset < 0)
7608 return offset;
7609
7610 p = ((char *)(get_vmcs12(vcpu))) + offset;
7611
7612 switch (vmcs_field_width(field)) {
7613 case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
7614 *ret = *((natural_width *)p);
7615 return 0;
7616 case VMCS_FIELD_WIDTH_U16:
7617 *ret = *((u16 *)p);
7618 return 0;
7619 case VMCS_FIELD_WIDTH_U32:
7620 *ret = *((u32 *)p);
7621 return 0;
7622 case VMCS_FIELD_WIDTH_U64:
7623 *ret = *((u64 *)p);
7624 return 0;
7625 default:
7626 WARN_ON(1);
7627 return -ENOENT;
7628 }
7629 }
7630
7631
7632 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7633 unsigned long field, u64 field_value){
7634 short offset = vmcs_field_to_offset(field);
7635 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7636 if (offset < 0)
7637 return offset;
7638
7639 switch (vmcs_field_width(field)) {
7640 case VMCS_FIELD_WIDTH_U16:
7641 *(u16 *)p = field_value;
7642 return 0;
7643 case VMCS_FIELD_WIDTH_U32:
7644 *(u32 *)p = field_value;
7645 return 0;
7646 case VMCS_FIELD_WIDTH_U64:
7647 *(u64 *)p = field_value;
7648 return 0;
7649 case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
7650 *(natural_width *)p = field_value;
7651 return 0;
7652 default:
7653 WARN_ON(1);
7654 return -ENOENT;
7655 }
7656
7657 }
7658
7659 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7660 {
7661 int i;
7662 unsigned long field;
7663 u64 field_value;
7664 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7665 const u16 *fields = shadow_read_write_fields;
7666 const int num_fields = max_shadow_read_write_fields;
7667
7668 preempt_disable();
7669
7670 vmcs_load(shadow_vmcs);
7671
7672 for (i = 0; i < num_fields; i++) {
7673 field = fields[i];
7674 field_value = __vmcs_readl(field);
7675 vmcs12_write_any(&vmx->vcpu, field, field_value);
7676 }
7677
7678 vmcs_clear(shadow_vmcs);
7679 vmcs_load(vmx->loaded_vmcs->vmcs);
7680
7681 preempt_enable();
7682 }
7683
7684 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7685 {
7686 const u16 *fields[] = {
7687 shadow_read_write_fields,
7688 shadow_read_only_fields
7689 };
7690 const int max_fields[] = {
7691 max_shadow_read_write_fields,
7692 max_shadow_read_only_fields
7693 };
7694 int i, q;
7695 unsigned long field;
7696 u64 field_value = 0;
7697 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7698
7699 vmcs_load(shadow_vmcs);
7700
7701 for (q = 0; q < ARRAY_SIZE(fields); q++) {
7702 for (i = 0; i < max_fields[q]; i++) {
7703 field = fields[q][i];
7704 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7705 __vmcs_writel(field, field_value);
7706 }
7707 }
7708
7709 vmcs_clear(shadow_vmcs);
7710 vmcs_load(vmx->loaded_vmcs->vmcs);
7711 }
7712
7713 /*
7714 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7715 * used before) all generate the same failure when it is missing.
7716 */
7717 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7718 {
7719 struct vcpu_vmx *vmx = to_vmx(vcpu);
7720 if (vmx->nested.current_vmptr == -1ull) {
7721 nested_vmx_failInvalid(vcpu);
7722 return 0;
7723 }
7724 return 1;
7725 }
7726
7727 static int handle_vmread(struct kvm_vcpu *vcpu)
7728 {
7729 unsigned long field;
7730 u64 field_value;
7731 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7732 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7733 gva_t gva = 0;
7734
7735 if (!nested_vmx_check_permission(vcpu))
7736 return 1;
7737
7738 if (!nested_vmx_check_vmcs12(vcpu))
7739 return kvm_skip_emulated_instruction(vcpu);
7740
7741 /* Decode instruction info and find the field to read */
7742 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7743 /* Read the field, zero-extended to a u64 field_value */
7744 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7745 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7746 return kvm_skip_emulated_instruction(vcpu);
7747 }
7748 /*
7749 * Now copy part of this value to register or memory, as requested.
7750 * Note that the number of bits actually copied is 32 or 64 depending
7751 * on the guest's mode (32 or 64 bit), not on the given field's length.
7752 */
7753 if (vmx_instruction_info & (1u << 10)) {
7754 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7755 field_value);
7756 } else {
7757 if (get_vmx_mem_address(vcpu, exit_qualification,
7758 vmx_instruction_info, true, &gva))
7759 return 1;
7760 /* _system ok, as hardware has verified cpl=0 */
7761 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7762 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7763 }
7764
7765 nested_vmx_succeed(vcpu);
7766 return kvm_skip_emulated_instruction(vcpu);
7767 }
7768
7769
7770 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7771 {
7772 unsigned long field;
7773 gva_t gva;
7774 struct vcpu_vmx *vmx = to_vmx(vcpu);
7775 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7776 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7777
7778 /* The value to write might be 32 or 64 bits, depending on L1's long
7779 * mode, and eventually we need to write that into a field of several
7780 * possible lengths. The code below first zero-extends the value to 64
7781 * bit (field_value), and then copies only the appropriate number of
7782 * bits into the vmcs12 field.
7783 */
7784 u64 field_value = 0;
7785 struct x86_exception e;
7786
7787 if (!nested_vmx_check_permission(vcpu))
7788 return 1;
7789
7790 if (!nested_vmx_check_vmcs12(vcpu))
7791 return kvm_skip_emulated_instruction(vcpu);
7792
7793 if (vmx_instruction_info & (1u << 10))
7794 field_value = kvm_register_readl(vcpu,
7795 (((vmx_instruction_info) >> 3) & 0xf));
7796 else {
7797 if (get_vmx_mem_address(vcpu, exit_qualification,
7798 vmx_instruction_info, false, &gva))
7799 return 1;
7800 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7801 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7802 kvm_inject_page_fault(vcpu, &e);
7803 return 1;
7804 }
7805 }
7806
7807
7808 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7809 if (vmcs_field_readonly(field)) {
7810 nested_vmx_failValid(vcpu,
7811 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7812 return kvm_skip_emulated_instruction(vcpu);
7813 }
7814
7815 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7816 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7817 return kvm_skip_emulated_instruction(vcpu);
7818 }
7819
7820 switch (field) {
7821 #define SHADOW_FIELD_RW(x) case x:
7822 #include "vmx_shadow_fields.h"
7823 /*
7824 * The fields that can be updated by L1 without a vmexit are
7825 * always updated in the vmcs02, the others go down the slow
7826 * path of prepare_vmcs02.
7827 */
7828 break;
7829 default:
7830 vmx->nested.dirty_vmcs12 = true;
7831 break;
7832 }
7833
7834 nested_vmx_succeed(vcpu);
7835 return kvm_skip_emulated_instruction(vcpu);
7836 }
7837
7838 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7839 {
7840 vmx->nested.current_vmptr = vmptr;
7841 if (enable_shadow_vmcs) {
7842 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7843 SECONDARY_EXEC_SHADOW_VMCS);
7844 vmcs_write64(VMCS_LINK_POINTER,
7845 __pa(vmx->vmcs01.shadow_vmcs));
7846 vmx->nested.sync_shadow_vmcs = true;
7847 }
7848 vmx->nested.dirty_vmcs12 = true;
7849 }
7850
7851 /* Emulate the VMPTRLD instruction */
7852 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7853 {
7854 struct vcpu_vmx *vmx = to_vmx(vcpu);
7855 gpa_t vmptr;
7856
7857 if (!nested_vmx_check_permission(vcpu))
7858 return 1;
7859
7860 if (nested_vmx_get_vmptr(vcpu, &vmptr))
7861 return 1;
7862
7863 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7864 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7865 return kvm_skip_emulated_instruction(vcpu);
7866 }
7867
7868 if (vmptr == vmx->nested.vmxon_ptr) {
7869 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7870 return kvm_skip_emulated_instruction(vcpu);
7871 }
7872
7873 if (vmx->nested.current_vmptr != vmptr) {
7874 struct vmcs12 *new_vmcs12;
7875 struct page *page;
7876 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7877 if (is_error_page(page)) {
7878 nested_vmx_failInvalid(vcpu);
7879 return kvm_skip_emulated_instruction(vcpu);
7880 }
7881 new_vmcs12 = kmap(page);
7882 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7883 kunmap(page);
7884 kvm_release_page_clean(page);
7885 nested_vmx_failValid(vcpu,
7886 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7887 return kvm_skip_emulated_instruction(vcpu);
7888 }
7889
7890 nested_release_vmcs12(vmx);
7891 /*
7892 * Load VMCS12 from guest memory since it is not already
7893 * cached.
7894 */
7895 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
7896 kunmap(page);
7897 kvm_release_page_clean(page);
7898
7899 set_current_vmptr(vmx, vmptr);
7900 }
7901
7902 nested_vmx_succeed(vcpu);
7903 return kvm_skip_emulated_instruction(vcpu);
7904 }
7905
7906 /* Emulate the VMPTRST instruction */
7907 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7908 {
7909 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7910 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7911 gva_t vmcs_gva;
7912 struct x86_exception e;
7913
7914 if (!nested_vmx_check_permission(vcpu))
7915 return 1;
7916
7917 if (get_vmx_mem_address(vcpu, exit_qualification,
7918 vmx_instruction_info, true, &vmcs_gva))
7919 return 1;
7920 /* ok to use *_system, as hardware has verified cpl=0 */
7921 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7922 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7923 sizeof(u64), &e)) {
7924 kvm_inject_page_fault(vcpu, &e);
7925 return 1;
7926 }
7927 nested_vmx_succeed(vcpu);
7928 return kvm_skip_emulated_instruction(vcpu);
7929 }
7930
7931 /* Emulate the INVEPT instruction */
7932 static int handle_invept(struct kvm_vcpu *vcpu)
7933 {
7934 struct vcpu_vmx *vmx = to_vmx(vcpu);
7935 u32 vmx_instruction_info, types;
7936 unsigned long type;
7937 gva_t gva;
7938 struct x86_exception e;
7939 struct {
7940 u64 eptp, gpa;
7941 } operand;
7942
7943 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7944 SECONDARY_EXEC_ENABLE_EPT) ||
7945 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7946 kvm_queue_exception(vcpu, UD_VECTOR);
7947 return 1;
7948 }
7949
7950 if (!nested_vmx_check_permission(vcpu))
7951 return 1;
7952
7953 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7954 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7955
7956 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7957
7958 if (type >= 32 || !(types & (1 << type))) {
7959 nested_vmx_failValid(vcpu,
7960 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7961 return kvm_skip_emulated_instruction(vcpu);
7962 }
7963
7964 /* According to the Intel VMX instruction reference, the memory
7965 * operand is read even if it isn't needed (e.g., for type==global)
7966 */
7967 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7968 vmx_instruction_info, false, &gva))
7969 return 1;
7970 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7971 sizeof(operand), &e)) {
7972 kvm_inject_page_fault(vcpu, &e);
7973 return 1;
7974 }
7975
7976 switch (type) {
7977 case VMX_EPT_EXTENT_GLOBAL:
7978 /*
7979 * TODO: track mappings and invalidate
7980 * single context requests appropriately
7981 */
7982 case VMX_EPT_EXTENT_CONTEXT:
7983 kvm_mmu_sync_roots(vcpu);
7984 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7985 nested_vmx_succeed(vcpu);
7986 break;
7987 default:
7988 BUG_ON(1);
7989 break;
7990 }
7991
7992 return kvm_skip_emulated_instruction(vcpu);
7993 }
7994
7995 static int handle_invvpid(struct kvm_vcpu *vcpu)
7996 {
7997 struct vcpu_vmx *vmx = to_vmx(vcpu);
7998 u32 vmx_instruction_info;
7999 unsigned long type, types;
8000 gva_t gva;
8001 struct x86_exception e;
8002 struct {
8003 u64 vpid;
8004 u64 gla;
8005 } operand;
8006
8007 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
8008 SECONDARY_EXEC_ENABLE_VPID) ||
8009 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
8010 kvm_queue_exception(vcpu, UD_VECTOR);
8011 return 1;
8012 }
8013
8014 if (!nested_vmx_check_permission(vcpu))
8015 return 1;
8016
8017 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8018 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8019
8020 types = (vmx->nested.nested_vmx_vpid_caps &
8021 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
8022
8023 if (type >= 32 || !(types & (1 << type))) {
8024 nested_vmx_failValid(vcpu,
8025 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8026 return kvm_skip_emulated_instruction(vcpu);
8027 }
8028
8029 /* according to the intel vmx instruction reference, the memory
8030 * operand is read even if it isn't needed (e.g., for type==global)
8031 */
8032 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8033 vmx_instruction_info, false, &gva))
8034 return 1;
8035 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
8036 sizeof(operand), &e)) {
8037 kvm_inject_page_fault(vcpu, &e);
8038 return 1;
8039 }
8040 if (operand.vpid >> 16) {
8041 nested_vmx_failValid(vcpu,
8042 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8043 return kvm_skip_emulated_instruction(vcpu);
8044 }
8045
8046 switch (type) {
8047 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
8048 if (is_noncanonical_address(operand.gla, vcpu)) {
8049 nested_vmx_failValid(vcpu,
8050 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8051 return kvm_skip_emulated_instruction(vcpu);
8052 }
8053 /* fall through */
8054 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
8055 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
8056 if (!operand.vpid) {
8057 nested_vmx_failValid(vcpu,
8058 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8059 return kvm_skip_emulated_instruction(vcpu);
8060 }
8061 break;
8062 case VMX_VPID_EXTENT_ALL_CONTEXT:
8063 break;
8064 default:
8065 WARN_ON_ONCE(1);
8066 return kvm_skip_emulated_instruction(vcpu);
8067 }
8068
8069 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8070 nested_vmx_succeed(vcpu);
8071
8072 return kvm_skip_emulated_instruction(vcpu);
8073 }
8074
8075 static int handle_pml_full(struct kvm_vcpu *vcpu)
8076 {
8077 unsigned long exit_qualification;
8078
8079 trace_kvm_pml_full(vcpu->vcpu_id);
8080
8081 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8082
8083 /*
8084 * PML buffer FULL happened while executing iret from NMI,
8085 * "blocked by NMI" bit has to be set before next VM entry.
8086 */
8087 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
8088 enable_vnmi &&
8089 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
8090 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8091 GUEST_INTR_STATE_NMI);
8092
8093 /*
8094 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
8095 * here.., and there's no userspace involvement needed for PML.
8096 */
8097 return 1;
8098 }
8099
8100 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8101 {
8102 kvm_lapic_expired_hv_timer(vcpu);
8103 return 1;
8104 }
8105
8106 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
8107 {
8108 struct vcpu_vmx *vmx = to_vmx(vcpu);
8109 int maxphyaddr = cpuid_maxphyaddr(vcpu);
8110
8111 /* Check for memory type validity */
8112 switch (address & VMX_EPTP_MT_MASK) {
8113 case VMX_EPTP_MT_UC:
8114 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_UC_BIT))
8115 return false;
8116 break;
8117 case VMX_EPTP_MT_WB:
8118 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_WB_BIT))
8119 return false;
8120 break;
8121 default:
8122 return false;
8123 }
8124
8125 /* only 4 levels page-walk length are valid */
8126 if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
8127 return false;
8128
8129 /* Reserved bits should not be set */
8130 if (address >> maxphyaddr || ((address >> 7) & 0x1f))
8131 return false;
8132
8133 /* AD, if set, should be supported */
8134 if (address & VMX_EPTP_AD_ENABLE_BIT) {
8135 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPT_AD_BIT))
8136 return false;
8137 }
8138
8139 return true;
8140 }
8141
8142 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
8143 struct vmcs12 *vmcs12)
8144 {
8145 u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
8146 u64 address;
8147 bool accessed_dirty;
8148 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
8149
8150 if (!nested_cpu_has_eptp_switching(vmcs12) ||
8151 !nested_cpu_has_ept(vmcs12))
8152 return 1;
8153
8154 if (index >= VMFUNC_EPTP_ENTRIES)
8155 return 1;
8156
8157
8158 if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
8159 &address, index * 8, 8))
8160 return 1;
8161
8162 accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
8163
8164 /*
8165 * If the (L2) guest does a vmfunc to the currently
8166 * active ept pointer, we don't have to do anything else
8167 */
8168 if (vmcs12->ept_pointer != address) {
8169 if (!valid_ept_address(vcpu, address))
8170 return 1;
8171
8172 kvm_mmu_unload(vcpu);
8173 mmu->ept_ad = accessed_dirty;
8174 mmu->base_role.ad_disabled = !accessed_dirty;
8175 vmcs12->ept_pointer = address;
8176 /*
8177 * TODO: Check what's the correct approach in case
8178 * mmu reload fails. Currently, we just let the next
8179 * reload potentially fail
8180 */
8181 kvm_mmu_reload(vcpu);
8182 }
8183
8184 return 0;
8185 }
8186
8187 static int handle_vmfunc(struct kvm_vcpu *vcpu)
8188 {
8189 struct vcpu_vmx *vmx = to_vmx(vcpu);
8190 struct vmcs12 *vmcs12;
8191 u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
8192
8193 /*
8194 * VMFUNC is only supported for nested guests, but we always enable the
8195 * secondary control for simplicity; for non-nested mode, fake that we
8196 * didn't by injecting #UD.
8197 */
8198 if (!is_guest_mode(vcpu)) {
8199 kvm_queue_exception(vcpu, UD_VECTOR);
8200 return 1;
8201 }
8202
8203 vmcs12 = get_vmcs12(vcpu);
8204 if ((vmcs12->vm_function_control & (1 << function)) == 0)
8205 goto fail;
8206
8207 switch (function) {
8208 case 0:
8209 if (nested_vmx_eptp_switching(vcpu, vmcs12))
8210 goto fail;
8211 break;
8212 default:
8213 goto fail;
8214 }
8215 return kvm_skip_emulated_instruction(vcpu);
8216
8217 fail:
8218 nested_vmx_vmexit(vcpu, vmx->exit_reason,
8219 vmcs_read32(VM_EXIT_INTR_INFO),
8220 vmcs_readl(EXIT_QUALIFICATION));
8221 return 1;
8222 }
8223
8224 /*
8225 * The exit handlers return 1 if the exit was handled fully and guest execution
8226 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
8227 * to be done to userspace and return 0.
8228 */
8229 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
8230 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
8231 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
8232 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
8233 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
8234 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
8235 [EXIT_REASON_CR_ACCESS] = handle_cr,
8236 [EXIT_REASON_DR_ACCESS] = handle_dr,
8237 [EXIT_REASON_CPUID] = handle_cpuid,
8238 [EXIT_REASON_MSR_READ] = handle_rdmsr,
8239 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
8240 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
8241 [EXIT_REASON_HLT] = handle_halt,
8242 [EXIT_REASON_INVD] = handle_invd,
8243 [EXIT_REASON_INVLPG] = handle_invlpg,
8244 [EXIT_REASON_RDPMC] = handle_rdpmc,
8245 [EXIT_REASON_VMCALL] = handle_vmcall,
8246 [EXIT_REASON_VMCLEAR] = handle_vmclear,
8247 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
8248 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
8249 [EXIT_REASON_VMPTRST] = handle_vmptrst,
8250 [EXIT_REASON_VMREAD] = handle_vmread,
8251 [EXIT_REASON_VMRESUME] = handle_vmresume,
8252 [EXIT_REASON_VMWRITE] = handle_vmwrite,
8253 [EXIT_REASON_VMOFF] = handle_vmoff,
8254 [EXIT_REASON_VMON] = handle_vmon,
8255 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
8256 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
8257 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
8258 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
8259 [EXIT_REASON_WBINVD] = handle_wbinvd,
8260 [EXIT_REASON_XSETBV] = handle_xsetbv,
8261 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
8262 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
8263 [EXIT_REASON_GDTR_IDTR] = handle_desc,
8264 [EXIT_REASON_LDTR_TR] = handle_desc,
8265 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
8266 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
8267 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
8268 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
8269 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
8270 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
8271 [EXIT_REASON_INVEPT] = handle_invept,
8272 [EXIT_REASON_INVVPID] = handle_invvpid,
8273 [EXIT_REASON_RDRAND] = handle_invalid_op,
8274 [EXIT_REASON_RDSEED] = handle_invalid_op,
8275 [EXIT_REASON_XSAVES] = handle_xsaves,
8276 [EXIT_REASON_XRSTORS] = handle_xrstors,
8277 [EXIT_REASON_PML_FULL] = handle_pml_full,
8278 [EXIT_REASON_VMFUNC] = handle_vmfunc,
8279 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
8280 };
8281
8282 static const int kvm_vmx_max_exit_handlers =
8283 ARRAY_SIZE(kvm_vmx_exit_handlers);
8284
8285 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
8286 struct vmcs12 *vmcs12)
8287 {
8288 unsigned long exit_qualification;
8289 gpa_t bitmap, last_bitmap;
8290 unsigned int port;
8291 int size;
8292 u8 b;
8293
8294 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
8295 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
8296
8297 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8298
8299 port = exit_qualification >> 16;
8300 size = (exit_qualification & 7) + 1;
8301
8302 last_bitmap = (gpa_t)-1;
8303 b = -1;
8304
8305 while (size > 0) {
8306 if (port < 0x8000)
8307 bitmap = vmcs12->io_bitmap_a;
8308 else if (port < 0x10000)
8309 bitmap = vmcs12->io_bitmap_b;
8310 else
8311 return true;
8312 bitmap += (port & 0x7fff) / 8;
8313
8314 if (last_bitmap != bitmap)
8315 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
8316 return true;
8317 if (b & (1 << (port & 7)))
8318 return true;
8319
8320 port++;
8321 size--;
8322 last_bitmap = bitmap;
8323 }
8324
8325 return false;
8326 }
8327
8328 /*
8329 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8330 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8331 * disinterest in the current event (read or write a specific MSR) by using an
8332 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8333 */
8334 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8335 struct vmcs12 *vmcs12, u32 exit_reason)
8336 {
8337 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8338 gpa_t bitmap;
8339
8340 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8341 return true;
8342
8343 /*
8344 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8345 * for the four combinations of read/write and low/high MSR numbers.
8346 * First we need to figure out which of the four to use:
8347 */
8348 bitmap = vmcs12->msr_bitmap;
8349 if (exit_reason == EXIT_REASON_MSR_WRITE)
8350 bitmap += 2048;
8351 if (msr_index >= 0xc0000000) {
8352 msr_index -= 0xc0000000;
8353 bitmap += 1024;
8354 }
8355
8356 /* Then read the msr_index'th bit from this bitmap: */
8357 if (msr_index < 1024*8) {
8358 unsigned char b;
8359 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
8360 return true;
8361 return 1 & (b >> (msr_index & 7));
8362 } else
8363 return true; /* let L1 handle the wrong parameter */
8364 }
8365
8366 /*
8367 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8368 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8369 * intercept (via guest_host_mask etc.) the current event.
8370 */
8371 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8372 struct vmcs12 *vmcs12)
8373 {
8374 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8375 int cr = exit_qualification & 15;
8376 int reg;
8377 unsigned long val;
8378
8379 switch ((exit_qualification >> 4) & 3) {
8380 case 0: /* mov to cr */
8381 reg = (exit_qualification >> 8) & 15;
8382 val = kvm_register_readl(vcpu, reg);
8383 switch (cr) {
8384 case 0:
8385 if (vmcs12->cr0_guest_host_mask &
8386 (val ^ vmcs12->cr0_read_shadow))
8387 return true;
8388 break;
8389 case 3:
8390 if ((vmcs12->cr3_target_count >= 1 &&
8391 vmcs12->cr3_target_value0 == val) ||
8392 (vmcs12->cr3_target_count >= 2 &&
8393 vmcs12->cr3_target_value1 == val) ||
8394 (vmcs12->cr3_target_count >= 3 &&
8395 vmcs12->cr3_target_value2 == val) ||
8396 (vmcs12->cr3_target_count >= 4 &&
8397 vmcs12->cr3_target_value3 == val))
8398 return false;
8399 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8400 return true;
8401 break;
8402 case 4:
8403 if (vmcs12->cr4_guest_host_mask &
8404 (vmcs12->cr4_read_shadow ^ val))
8405 return true;
8406 break;
8407 case 8:
8408 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8409 return true;
8410 break;
8411 }
8412 break;
8413 case 2: /* clts */
8414 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8415 (vmcs12->cr0_read_shadow & X86_CR0_TS))
8416 return true;
8417 break;
8418 case 1: /* mov from cr */
8419 switch (cr) {
8420 case 3:
8421 if (vmcs12->cpu_based_vm_exec_control &
8422 CPU_BASED_CR3_STORE_EXITING)
8423 return true;
8424 break;
8425 case 8:
8426 if (vmcs12->cpu_based_vm_exec_control &
8427 CPU_BASED_CR8_STORE_EXITING)
8428 return true;
8429 break;
8430 }
8431 break;
8432 case 3: /* lmsw */
8433 /*
8434 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8435 * cr0. Other attempted changes are ignored, with no exit.
8436 */
8437 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
8438 if (vmcs12->cr0_guest_host_mask & 0xe &
8439 (val ^ vmcs12->cr0_read_shadow))
8440 return true;
8441 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8442 !(vmcs12->cr0_read_shadow & 0x1) &&
8443 (val & 0x1))
8444 return true;
8445 break;
8446 }
8447 return false;
8448 }
8449
8450 /*
8451 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8452 * should handle it ourselves in L0 (and then continue L2). Only call this
8453 * when in is_guest_mode (L2).
8454 */
8455 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
8456 {
8457 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8458 struct vcpu_vmx *vmx = to_vmx(vcpu);
8459 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8460
8461 if (vmx->nested.nested_run_pending)
8462 return false;
8463
8464 if (unlikely(vmx->fail)) {
8465 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8466 vmcs_read32(VM_INSTRUCTION_ERROR));
8467 return true;
8468 }
8469
8470 /*
8471 * The host physical addresses of some pages of guest memory
8472 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
8473 * Page). The CPU may write to these pages via their host
8474 * physical address while L2 is running, bypassing any
8475 * address-translation-based dirty tracking (e.g. EPT write
8476 * protection).
8477 *
8478 * Mark them dirty on every exit from L2 to prevent them from
8479 * getting out of sync with dirty tracking.
8480 */
8481 nested_mark_vmcs12_pages_dirty(vcpu);
8482
8483 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8484 vmcs_readl(EXIT_QUALIFICATION),
8485 vmx->idt_vectoring_info,
8486 intr_info,
8487 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8488 KVM_ISA_VMX);
8489
8490 switch (exit_reason) {
8491 case EXIT_REASON_EXCEPTION_NMI:
8492 if (is_nmi(intr_info))
8493 return false;
8494 else if (is_page_fault(intr_info))
8495 return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
8496 else if (is_no_device(intr_info) &&
8497 !(vmcs12->guest_cr0 & X86_CR0_TS))
8498 return false;
8499 else if (is_debug(intr_info) &&
8500 vcpu->guest_debug &
8501 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8502 return false;
8503 else if (is_breakpoint(intr_info) &&
8504 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8505 return false;
8506 return vmcs12->exception_bitmap &
8507 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8508 case EXIT_REASON_EXTERNAL_INTERRUPT:
8509 return false;
8510 case EXIT_REASON_TRIPLE_FAULT:
8511 return true;
8512 case EXIT_REASON_PENDING_INTERRUPT:
8513 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8514 case EXIT_REASON_NMI_WINDOW:
8515 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8516 case EXIT_REASON_TASK_SWITCH:
8517 return true;
8518 case EXIT_REASON_CPUID:
8519 return true;
8520 case EXIT_REASON_HLT:
8521 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8522 case EXIT_REASON_INVD:
8523 return true;
8524 case EXIT_REASON_INVLPG:
8525 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8526 case EXIT_REASON_RDPMC:
8527 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8528 case EXIT_REASON_RDRAND:
8529 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
8530 case EXIT_REASON_RDSEED:
8531 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
8532 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8533 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8534 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8535 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8536 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8537 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8538 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8539 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8540 /*
8541 * VMX instructions trap unconditionally. This allows L1 to
8542 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8543 */
8544 return true;
8545 case EXIT_REASON_CR_ACCESS:
8546 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8547 case EXIT_REASON_DR_ACCESS:
8548 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8549 case EXIT_REASON_IO_INSTRUCTION:
8550 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8551 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8552 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8553 case EXIT_REASON_MSR_READ:
8554 case EXIT_REASON_MSR_WRITE:
8555 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8556 case EXIT_REASON_INVALID_STATE:
8557 return true;
8558 case EXIT_REASON_MWAIT_INSTRUCTION:
8559 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8560 case EXIT_REASON_MONITOR_TRAP_FLAG:
8561 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8562 case EXIT_REASON_MONITOR_INSTRUCTION:
8563 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8564 case EXIT_REASON_PAUSE_INSTRUCTION:
8565 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8566 nested_cpu_has2(vmcs12,
8567 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8568 case EXIT_REASON_MCE_DURING_VMENTRY:
8569 return false;
8570 case EXIT_REASON_TPR_BELOW_THRESHOLD:
8571 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8572 case EXIT_REASON_APIC_ACCESS:
8573 return nested_cpu_has2(vmcs12,
8574 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8575 case EXIT_REASON_APIC_WRITE:
8576 case EXIT_REASON_EOI_INDUCED:
8577 /* apic_write and eoi_induced should exit unconditionally. */
8578 return true;
8579 case EXIT_REASON_EPT_VIOLATION:
8580 /*
8581 * L0 always deals with the EPT violation. If nested EPT is
8582 * used, and the nested mmu code discovers that the address is
8583 * missing in the guest EPT table (EPT12), the EPT violation
8584 * will be injected with nested_ept_inject_page_fault()
8585 */
8586 return false;
8587 case EXIT_REASON_EPT_MISCONFIG:
8588 /*
8589 * L2 never uses directly L1's EPT, but rather L0's own EPT
8590 * table (shadow on EPT) or a merged EPT table that L0 built
8591 * (EPT on EPT). So any problems with the structure of the
8592 * table is L0's fault.
8593 */
8594 return false;
8595 case EXIT_REASON_INVPCID:
8596 return
8597 nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
8598 nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8599 case EXIT_REASON_WBINVD:
8600 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8601 case EXIT_REASON_XSETBV:
8602 return true;
8603 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8604 /*
8605 * This should never happen, since it is not possible to
8606 * set XSS to a non-zero value---neither in L1 nor in L2.
8607 * If if it were, XSS would have to be checked against
8608 * the XSS exit bitmap in vmcs12.
8609 */
8610 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8611 case EXIT_REASON_PREEMPTION_TIMER:
8612 return false;
8613 case EXIT_REASON_PML_FULL:
8614 /* We emulate PML support to L1. */
8615 return false;
8616 case EXIT_REASON_VMFUNC:
8617 /* VM functions are emulated through L2->L0 vmexits. */
8618 return false;
8619 default:
8620 return true;
8621 }
8622 }
8623
8624 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
8625 {
8626 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8627
8628 /*
8629 * At this point, the exit interruption info in exit_intr_info
8630 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8631 * we need to query the in-kernel LAPIC.
8632 */
8633 WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
8634 if ((exit_intr_info &
8635 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8636 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
8637 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8638 vmcs12->vm_exit_intr_error_code =
8639 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8640 }
8641
8642 nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
8643 vmcs_readl(EXIT_QUALIFICATION));
8644 return 1;
8645 }
8646
8647 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8648 {
8649 *info1 = vmcs_readl(EXIT_QUALIFICATION);
8650 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8651 }
8652
8653 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8654 {
8655 if (vmx->pml_pg) {
8656 __free_page(vmx->pml_pg);
8657 vmx->pml_pg = NULL;
8658 }
8659 }
8660
8661 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8662 {
8663 struct vcpu_vmx *vmx = to_vmx(vcpu);
8664 u64 *pml_buf;
8665 u16 pml_idx;
8666
8667 pml_idx = vmcs_read16(GUEST_PML_INDEX);
8668
8669 /* Do nothing if PML buffer is empty */
8670 if (pml_idx == (PML_ENTITY_NUM - 1))
8671 return;
8672
8673 /* PML index always points to next available PML buffer entity */
8674 if (pml_idx >= PML_ENTITY_NUM)
8675 pml_idx = 0;
8676 else
8677 pml_idx++;
8678
8679 pml_buf = page_address(vmx->pml_pg);
8680 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8681 u64 gpa;
8682
8683 gpa = pml_buf[pml_idx];
8684 WARN_ON(gpa & (PAGE_SIZE - 1));
8685 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8686 }
8687
8688 /* reset PML index */
8689 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8690 }
8691
8692 /*
8693 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8694 * Called before reporting dirty_bitmap to userspace.
8695 */
8696 static void kvm_flush_pml_buffers(struct kvm *kvm)
8697 {
8698 int i;
8699 struct kvm_vcpu *vcpu;
8700 /*
8701 * We only need to kick vcpu out of guest mode here, as PML buffer
8702 * is flushed at beginning of all VMEXITs, and it's obvious that only
8703 * vcpus running in guest are possible to have unflushed GPAs in PML
8704 * buffer.
8705 */
8706 kvm_for_each_vcpu(i, vcpu, kvm)
8707 kvm_vcpu_kick(vcpu);
8708 }
8709
8710 static void vmx_dump_sel(char *name, uint32_t sel)
8711 {
8712 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8713 name, vmcs_read16(sel),
8714 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8715 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8716 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8717 }
8718
8719 static void vmx_dump_dtsel(char *name, uint32_t limit)
8720 {
8721 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8722 name, vmcs_read32(limit),
8723 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8724 }
8725
8726 static void dump_vmcs(void)
8727 {
8728 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8729 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8730 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8731 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8732 u32 secondary_exec_control = 0;
8733 unsigned long cr4 = vmcs_readl(GUEST_CR4);
8734 u64 efer = vmcs_read64(GUEST_IA32_EFER);
8735 int i, n;
8736
8737 if (cpu_has_secondary_exec_ctrls())
8738 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8739
8740 pr_err("*** Guest State ***\n");
8741 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8742 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8743 vmcs_readl(CR0_GUEST_HOST_MASK));
8744 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8745 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8746 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8747 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8748 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8749 {
8750 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8751 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8752 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8753 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8754 }
8755 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8756 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8757 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8758 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8759 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8760 vmcs_readl(GUEST_SYSENTER_ESP),
8761 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8762 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
8763 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
8764 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
8765 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
8766 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
8767 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
8768 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8769 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8770 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8771 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
8772 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8773 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8774 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8775 efer, vmcs_read64(GUEST_IA32_PAT));
8776 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8777 vmcs_read64(GUEST_IA32_DEBUGCTL),
8778 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8779 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8780 pr_err("PerfGlobCtl = 0x%016llx\n",
8781 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8782 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8783 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8784 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8785 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8786 vmcs_read32(GUEST_ACTIVITY_STATE));
8787 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8788 pr_err("InterruptStatus = %04x\n",
8789 vmcs_read16(GUEST_INTR_STATUS));
8790
8791 pr_err("*** Host State ***\n");
8792 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8793 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8794 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8795 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8796 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8797 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8798 vmcs_read16(HOST_TR_SELECTOR));
8799 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8800 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8801 vmcs_readl(HOST_TR_BASE));
8802 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8803 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8804 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8805 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8806 vmcs_readl(HOST_CR4));
8807 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8808 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8809 vmcs_read32(HOST_IA32_SYSENTER_CS),
8810 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8811 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8812 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8813 vmcs_read64(HOST_IA32_EFER),
8814 vmcs_read64(HOST_IA32_PAT));
8815 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8816 pr_err("PerfGlobCtl = 0x%016llx\n",
8817 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8818
8819 pr_err("*** Control State ***\n");
8820 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8821 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8822 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8823 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8824 vmcs_read32(EXCEPTION_BITMAP),
8825 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8826 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8827 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8828 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8829 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8830 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8831 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8832 vmcs_read32(VM_EXIT_INTR_INFO),
8833 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8834 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8835 pr_err(" reason=%08x qualification=%016lx\n",
8836 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8837 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8838 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8839 vmcs_read32(IDT_VECTORING_ERROR_CODE));
8840 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8841 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8842 pr_err("TSC Multiplier = 0x%016llx\n",
8843 vmcs_read64(TSC_MULTIPLIER));
8844 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8845 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8846 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8847 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8848 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8849 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8850 n = vmcs_read32(CR3_TARGET_COUNT);
8851 for (i = 0; i + 1 < n; i += 4)
8852 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8853 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8854 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8855 if (i < n)
8856 pr_err("CR3 target%u=%016lx\n",
8857 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8858 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8859 pr_err("PLE Gap=%08x Window=%08x\n",
8860 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8861 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8862 pr_err("Virtual processor ID = 0x%04x\n",
8863 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8864 }
8865
8866 /*
8867 * The guest has exited. See if we can fix it or if we need userspace
8868 * assistance.
8869 */
8870 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8871 {
8872 struct vcpu_vmx *vmx = to_vmx(vcpu);
8873 u32 exit_reason = vmx->exit_reason;
8874 u32 vectoring_info = vmx->idt_vectoring_info;
8875
8876 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8877
8878 /*
8879 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8880 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8881 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8882 * mode as if vcpus is in root mode, the PML buffer must has been
8883 * flushed already.
8884 */
8885 if (enable_pml)
8886 vmx_flush_pml_buffer(vcpu);
8887
8888 /* If guest state is invalid, start emulating */
8889 if (vmx->emulation_required)
8890 return handle_invalid_guest_state(vcpu);
8891
8892 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
8893 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
8894
8895 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8896 dump_vmcs();
8897 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8898 vcpu->run->fail_entry.hardware_entry_failure_reason
8899 = exit_reason;
8900 return 0;
8901 }
8902
8903 if (unlikely(vmx->fail)) {
8904 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8905 vcpu->run->fail_entry.hardware_entry_failure_reason
8906 = vmcs_read32(VM_INSTRUCTION_ERROR);
8907 return 0;
8908 }
8909
8910 /*
8911 * Note:
8912 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8913 * delivery event since it indicates guest is accessing MMIO.
8914 * The vm-exit can be triggered again after return to guest that
8915 * will cause infinite loop.
8916 */
8917 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8918 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8919 exit_reason != EXIT_REASON_EPT_VIOLATION &&
8920 exit_reason != EXIT_REASON_PML_FULL &&
8921 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8922 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8923 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8924 vcpu->run->internal.ndata = 3;
8925 vcpu->run->internal.data[0] = vectoring_info;
8926 vcpu->run->internal.data[1] = exit_reason;
8927 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
8928 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
8929 vcpu->run->internal.ndata++;
8930 vcpu->run->internal.data[3] =
8931 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
8932 }
8933 return 0;
8934 }
8935
8936 if (unlikely(!enable_vnmi &&
8937 vmx->loaded_vmcs->soft_vnmi_blocked)) {
8938 if (vmx_interrupt_allowed(vcpu)) {
8939 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
8940 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
8941 vcpu->arch.nmi_pending) {
8942 /*
8943 * This CPU don't support us in finding the end of an
8944 * NMI-blocked window if the guest runs with IRQs
8945 * disabled. So we pull the trigger after 1 s of
8946 * futile waiting, but inform the user about this.
8947 */
8948 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8949 "state on VCPU %d after 1 s timeout\n",
8950 __func__, vcpu->vcpu_id);
8951 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
8952 }
8953 }
8954
8955 if (exit_reason < kvm_vmx_max_exit_handlers
8956 && kvm_vmx_exit_handlers[exit_reason])
8957 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8958 else {
8959 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8960 exit_reason);
8961 kvm_queue_exception(vcpu, UD_VECTOR);
8962 return 1;
8963 }
8964 }
8965
8966 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8967 {
8968 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8969
8970 if (is_guest_mode(vcpu) &&
8971 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8972 return;
8973
8974 if (irr == -1 || tpr < irr) {
8975 vmcs_write32(TPR_THRESHOLD, 0);
8976 return;
8977 }
8978
8979 vmcs_write32(TPR_THRESHOLD, irr);
8980 }
8981
8982 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8983 {
8984 u32 sec_exec_control;
8985
8986 /* Postpone execution until vmcs01 is the current VMCS. */
8987 if (is_guest_mode(vcpu)) {
8988 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8989 return;
8990 }
8991
8992 if (!cpu_has_vmx_virtualize_x2apic_mode())
8993 return;
8994
8995 if (!cpu_need_tpr_shadow(vcpu))
8996 return;
8997
8998 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8999
9000 if (set) {
9001 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9002 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
9003 } else {
9004 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
9005 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9006 vmx_flush_tlb_ept_only(vcpu);
9007 }
9008 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
9009
9010 vmx_update_msr_bitmap(vcpu);
9011 }
9012
9013 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
9014 {
9015 struct vcpu_vmx *vmx = to_vmx(vcpu);
9016
9017 /*
9018 * Currently we do not handle the nested case where L2 has an
9019 * APIC access page of its own; that page is still pinned.
9020 * Hence, we skip the case where the VCPU is in guest mode _and_
9021 * L1 prepared an APIC access page for L2.
9022 *
9023 * For the case where L1 and L2 share the same APIC access page
9024 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
9025 * in the vmcs12), this function will only update either the vmcs01
9026 * or the vmcs02. If the former, the vmcs02 will be updated by
9027 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
9028 * the next L2->L1 exit.
9029 */
9030 if (!is_guest_mode(vcpu) ||
9031 !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
9032 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9033 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9034 vmx_flush_tlb_ept_only(vcpu);
9035 }
9036 }
9037
9038 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
9039 {
9040 u16 status;
9041 u8 old;
9042
9043 if (max_isr == -1)
9044 max_isr = 0;
9045
9046 status = vmcs_read16(GUEST_INTR_STATUS);
9047 old = status >> 8;
9048 if (max_isr != old) {
9049 status &= 0xff;
9050 status |= max_isr << 8;
9051 vmcs_write16(GUEST_INTR_STATUS, status);
9052 }
9053 }
9054
9055 static void vmx_set_rvi(int vector)
9056 {
9057 u16 status;
9058 u8 old;
9059
9060 if (vector == -1)
9061 vector = 0;
9062
9063 status = vmcs_read16(GUEST_INTR_STATUS);
9064 old = (u8)status & 0xff;
9065 if ((u8)vector != old) {
9066 status &= ~0xff;
9067 status |= (u8)vector;
9068 vmcs_write16(GUEST_INTR_STATUS, status);
9069 }
9070 }
9071
9072 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
9073 {
9074 /*
9075 * When running L2, updating RVI is only relevant when
9076 * vmcs12 virtual-interrupt-delivery enabled.
9077 * However, it can be enabled only when L1 also
9078 * intercepts external-interrupts and in that case
9079 * we should not update vmcs02 RVI but instead intercept
9080 * interrupt. Therefore, do nothing when running L2.
9081 */
9082 if (!is_guest_mode(vcpu))
9083 vmx_set_rvi(max_irr);
9084 }
9085
9086 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
9087 {
9088 struct vcpu_vmx *vmx = to_vmx(vcpu);
9089 int max_irr;
9090 bool max_irr_updated;
9091
9092 WARN_ON(!vcpu->arch.apicv_active);
9093 if (pi_test_on(&vmx->pi_desc)) {
9094 pi_clear_on(&vmx->pi_desc);
9095 /*
9096 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
9097 * But on x86 this is just a compiler barrier anyway.
9098 */
9099 smp_mb__after_atomic();
9100 max_irr_updated =
9101 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
9102
9103 /*
9104 * If we are running L2 and L1 has a new pending interrupt
9105 * which can be injected, we should re-evaluate
9106 * what should be done with this new L1 interrupt.
9107 * If L1 intercepts external-interrupts, we should
9108 * exit from L2 to L1. Otherwise, interrupt should be
9109 * delivered directly to L2.
9110 */
9111 if (is_guest_mode(vcpu) && max_irr_updated) {
9112 if (nested_exit_on_intr(vcpu))
9113 kvm_vcpu_exiting_guest_mode(vcpu);
9114 else
9115 kvm_make_request(KVM_REQ_EVENT, vcpu);
9116 }
9117 } else {
9118 max_irr = kvm_lapic_find_highest_irr(vcpu);
9119 }
9120 vmx_hwapic_irr_update(vcpu, max_irr);
9121 return max_irr;
9122 }
9123
9124 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
9125 {
9126 if (!kvm_vcpu_apicv_active(vcpu))
9127 return;
9128
9129 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
9130 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
9131 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
9132 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
9133 }
9134
9135 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
9136 {
9137 struct vcpu_vmx *vmx = to_vmx(vcpu);
9138
9139 pi_clear_on(&vmx->pi_desc);
9140 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
9141 }
9142
9143 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
9144 {
9145 u32 exit_intr_info = 0;
9146 u16 basic_exit_reason = (u16)vmx->exit_reason;
9147
9148 if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
9149 || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
9150 return;
9151
9152 if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9153 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9154 vmx->exit_intr_info = exit_intr_info;
9155
9156 /* if exit due to PF check for async PF */
9157 if (is_page_fault(exit_intr_info))
9158 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
9159
9160 /* Handle machine checks before interrupts are enabled */
9161 if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
9162 is_machine_check(exit_intr_info))
9163 kvm_machine_check();
9164
9165 /* We need to handle NMIs before interrupts are enabled */
9166 if (is_nmi(exit_intr_info)) {
9167 kvm_before_handle_nmi(&vmx->vcpu);
9168 asm("int $2");
9169 kvm_after_handle_nmi(&vmx->vcpu);
9170 }
9171 }
9172
9173 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
9174 {
9175 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9176
9177 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
9178 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
9179 unsigned int vector;
9180 unsigned long entry;
9181 gate_desc *desc;
9182 struct vcpu_vmx *vmx = to_vmx(vcpu);
9183 #ifdef CONFIG_X86_64
9184 unsigned long tmp;
9185 #endif
9186
9187 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9188 desc = (gate_desc *)vmx->host_idt_base + vector;
9189 entry = gate_offset(desc);
9190 asm volatile(
9191 #ifdef CONFIG_X86_64
9192 "mov %%" _ASM_SP ", %[sp]\n\t"
9193 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
9194 "push $%c[ss]\n\t"
9195 "push %[sp]\n\t"
9196 #endif
9197 "pushf\n\t"
9198 __ASM_SIZE(push) " $%c[cs]\n\t"
9199 CALL_NOSPEC
9200 :
9201 #ifdef CONFIG_X86_64
9202 [sp]"=&r"(tmp),
9203 #endif
9204 ASM_CALL_CONSTRAINT
9205 :
9206 THUNK_TARGET(entry),
9207 [ss]"i"(__KERNEL_DS),
9208 [cs]"i"(__KERNEL_CS)
9209 );
9210 }
9211 }
9212 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
9213
9214 static bool vmx_has_high_real_mode_segbase(void)
9215 {
9216 return enable_unrestricted_guest || emulate_invalid_guest_state;
9217 }
9218
9219 static bool vmx_mpx_supported(void)
9220 {
9221 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
9222 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
9223 }
9224
9225 static bool vmx_xsaves_supported(void)
9226 {
9227 return vmcs_config.cpu_based_2nd_exec_ctrl &
9228 SECONDARY_EXEC_XSAVES;
9229 }
9230
9231 static bool vmx_umip_emulated(void)
9232 {
9233 return vmcs_config.cpu_based_2nd_exec_ctrl &
9234 SECONDARY_EXEC_DESC;
9235 }
9236
9237 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
9238 {
9239 u32 exit_intr_info;
9240 bool unblock_nmi;
9241 u8 vector;
9242 bool idtv_info_valid;
9243
9244 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9245
9246 if (enable_vnmi) {
9247 if (vmx->loaded_vmcs->nmi_known_unmasked)
9248 return;
9249 /*
9250 * Can't use vmx->exit_intr_info since we're not sure what
9251 * the exit reason is.
9252 */
9253 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9254 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
9255 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9256 /*
9257 * SDM 3: 27.7.1.2 (September 2008)
9258 * Re-set bit "block by NMI" before VM entry if vmexit caused by
9259 * a guest IRET fault.
9260 * SDM 3: 23.2.2 (September 2008)
9261 * Bit 12 is undefined in any of the following cases:
9262 * If the VM exit sets the valid bit in the IDT-vectoring
9263 * information field.
9264 * If the VM exit is due to a double fault.
9265 */
9266 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
9267 vector != DF_VECTOR && !idtv_info_valid)
9268 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9269 GUEST_INTR_STATE_NMI);
9270 else
9271 vmx->loaded_vmcs->nmi_known_unmasked =
9272 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
9273 & GUEST_INTR_STATE_NMI);
9274 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
9275 vmx->loaded_vmcs->vnmi_blocked_time +=
9276 ktime_to_ns(ktime_sub(ktime_get(),
9277 vmx->loaded_vmcs->entry_time));
9278 }
9279
9280 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
9281 u32 idt_vectoring_info,
9282 int instr_len_field,
9283 int error_code_field)
9284 {
9285 u8 vector;
9286 int type;
9287 bool idtv_info_valid;
9288
9289 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9290
9291 vcpu->arch.nmi_injected = false;
9292 kvm_clear_exception_queue(vcpu);
9293 kvm_clear_interrupt_queue(vcpu);
9294
9295 if (!idtv_info_valid)
9296 return;
9297
9298 kvm_make_request(KVM_REQ_EVENT, vcpu);
9299
9300 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
9301 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
9302
9303 switch (type) {
9304 case INTR_TYPE_NMI_INTR:
9305 vcpu->arch.nmi_injected = true;
9306 /*
9307 * SDM 3: 27.7.1.2 (September 2008)
9308 * Clear bit "block by NMI" before VM entry if a NMI
9309 * delivery faulted.
9310 */
9311 vmx_set_nmi_mask(vcpu, false);
9312 break;
9313 case INTR_TYPE_SOFT_EXCEPTION:
9314 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9315 /* fall through */
9316 case INTR_TYPE_HARD_EXCEPTION:
9317 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
9318 u32 err = vmcs_read32(error_code_field);
9319 kvm_requeue_exception_e(vcpu, vector, err);
9320 } else
9321 kvm_requeue_exception(vcpu, vector);
9322 break;
9323 case INTR_TYPE_SOFT_INTR:
9324 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9325 /* fall through */
9326 case INTR_TYPE_EXT_INTR:
9327 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
9328 break;
9329 default:
9330 break;
9331 }
9332 }
9333
9334 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
9335 {
9336 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
9337 VM_EXIT_INSTRUCTION_LEN,
9338 IDT_VECTORING_ERROR_CODE);
9339 }
9340
9341 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
9342 {
9343 __vmx_complete_interrupts(vcpu,
9344 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9345 VM_ENTRY_INSTRUCTION_LEN,
9346 VM_ENTRY_EXCEPTION_ERROR_CODE);
9347
9348 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9349 }
9350
9351 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
9352 {
9353 int i, nr_msrs;
9354 struct perf_guest_switch_msr *msrs;
9355
9356 msrs = perf_guest_get_msrs(&nr_msrs);
9357
9358 if (!msrs)
9359 return;
9360
9361 for (i = 0; i < nr_msrs; i++)
9362 if (msrs[i].host == msrs[i].guest)
9363 clear_atomic_switch_msr(vmx, msrs[i].msr);
9364 else
9365 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
9366 msrs[i].host);
9367 }
9368
9369 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
9370 {
9371 struct vcpu_vmx *vmx = to_vmx(vcpu);
9372 u64 tscl;
9373 u32 delta_tsc;
9374
9375 if (vmx->hv_deadline_tsc == -1)
9376 return;
9377
9378 tscl = rdtsc();
9379 if (vmx->hv_deadline_tsc > tscl)
9380 /* sure to be 32 bit only because checked on set_hv_timer */
9381 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
9382 cpu_preemption_timer_multi);
9383 else
9384 delta_tsc = 0;
9385
9386 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
9387 }
9388
9389 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
9390 {
9391 struct vcpu_vmx *vmx = to_vmx(vcpu);
9392 unsigned long cr3, cr4;
9393
9394 /* Record the guest's net vcpu time for enforced NMI injections. */
9395 if (unlikely(!enable_vnmi &&
9396 vmx->loaded_vmcs->soft_vnmi_blocked))
9397 vmx->loaded_vmcs->entry_time = ktime_get();
9398
9399 /* Don't enter VMX if guest state is invalid, let the exit handler
9400 start emulation until we arrive back to a valid state */
9401 if (vmx->emulation_required)
9402 return;
9403
9404 if (vmx->ple_window_dirty) {
9405 vmx->ple_window_dirty = false;
9406 vmcs_write32(PLE_WINDOW, vmx->ple_window);
9407 }
9408
9409 if (vmx->nested.sync_shadow_vmcs) {
9410 copy_vmcs12_to_shadow(vmx);
9411 vmx->nested.sync_shadow_vmcs = false;
9412 }
9413
9414 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
9415 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
9416 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
9417 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9418
9419 cr3 = __get_current_cr3_fast();
9420 if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) {
9421 vmcs_writel(HOST_CR3, cr3);
9422 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
9423 }
9424
9425 cr4 = cr4_read_shadow();
9426 if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) {
9427 vmcs_writel(HOST_CR4, cr4);
9428 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
9429 }
9430
9431 /* When single-stepping over STI and MOV SS, we must clear the
9432 * corresponding interruptibility bits in the guest state. Otherwise
9433 * vmentry fails as it then expects bit 14 (BS) in pending debug
9434 * exceptions being set, but that's not correct for the guest debugging
9435 * case. */
9436 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9437 vmx_set_interrupt_shadow(vcpu, 0);
9438
9439 if (static_cpu_has(X86_FEATURE_PKU) &&
9440 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
9441 vcpu->arch.pkru != vmx->host_pkru)
9442 __write_pkru(vcpu->arch.pkru);
9443
9444 atomic_switch_perf_msrs(vmx);
9445
9446 vmx_arm_hv_timer(vcpu);
9447
9448 /*
9449 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
9450 * it's non-zero. Since vmentry is serialising on affected CPUs, there
9451 * is no need to worry about the conditional branch over the wrmsr
9452 * being speculatively taken.
9453 */
9454 if (vmx->spec_ctrl)
9455 wrmsrl(MSR_IA32_SPEC_CTRL, vmx->spec_ctrl);
9456
9457 vmx->__launched = vmx->loaded_vmcs->launched;
9458 asm(
9459 /* Store host registers */
9460 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
9461 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
9462 "push %%" _ASM_CX " \n\t"
9463 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9464 "je 1f \n\t"
9465 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9466 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
9467 "1: \n\t"
9468 /* Reload cr2 if changed */
9469 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
9470 "mov %%cr2, %%" _ASM_DX " \n\t"
9471 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
9472 "je 2f \n\t"
9473 "mov %%" _ASM_AX", %%cr2 \n\t"
9474 "2: \n\t"
9475 /* Check if vmlaunch of vmresume is needed */
9476 "cmpl $0, %c[launched](%0) \n\t"
9477 /* Load guest registers. Don't clobber flags. */
9478 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9479 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9480 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9481 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9482 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9483 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9484 #ifdef CONFIG_X86_64
9485 "mov %c[r8](%0), %%r8 \n\t"
9486 "mov %c[r9](%0), %%r9 \n\t"
9487 "mov %c[r10](%0), %%r10 \n\t"
9488 "mov %c[r11](%0), %%r11 \n\t"
9489 "mov %c[r12](%0), %%r12 \n\t"
9490 "mov %c[r13](%0), %%r13 \n\t"
9491 "mov %c[r14](%0), %%r14 \n\t"
9492 "mov %c[r15](%0), %%r15 \n\t"
9493 #endif
9494 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9495
9496 /* Enter guest mode */
9497 "jne 1f \n\t"
9498 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9499 "jmp 2f \n\t"
9500 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9501 "2: "
9502 /* Save guest registers, load host registers, keep flags */
9503 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9504 "pop %0 \n\t"
9505 "setbe %c[fail](%0)\n\t"
9506 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9507 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9508 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9509 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9510 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9511 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9512 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9513 #ifdef CONFIG_X86_64
9514 "mov %%r8, %c[r8](%0) \n\t"
9515 "mov %%r9, %c[r9](%0) \n\t"
9516 "mov %%r10, %c[r10](%0) \n\t"
9517 "mov %%r11, %c[r11](%0) \n\t"
9518 "mov %%r12, %c[r12](%0) \n\t"
9519 "mov %%r13, %c[r13](%0) \n\t"
9520 "mov %%r14, %c[r14](%0) \n\t"
9521 "mov %%r15, %c[r15](%0) \n\t"
9522 "xor %%r8d, %%r8d \n\t"
9523 "xor %%r9d, %%r9d \n\t"
9524 "xor %%r10d, %%r10d \n\t"
9525 "xor %%r11d, %%r11d \n\t"
9526 "xor %%r12d, %%r12d \n\t"
9527 "xor %%r13d, %%r13d \n\t"
9528 "xor %%r14d, %%r14d \n\t"
9529 "xor %%r15d, %%r15d \n\t"
9530 #endif
9531 "mov %%cr2, %%" _ASM_AX " \n\t"
9532 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9533
9534 "xor %%eax, %%eax \n\t"
9535 "xor %%ebx, %%ebx \n\t"
9536 "xor %%esi, %%esi \n\t"
9537 "xor %%edi, %%edi \n\t"
9538 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
9539 ".pushsection .rodata \n\t"
9540 ".global vmx_return \n\t"
9541 "vmx_return: " _ASM_PTR " 2b \n\t"
9542 ".popsection"
9543 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9544 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9545 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9546 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9547 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9548 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9549 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9550 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9551 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9552 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9553 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9554 #ifdef CONFIG_X86_64
9555 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9556 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9557 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9558 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9559 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9560 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9561 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9562 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9563 #endif
9564 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9565 [wordsize]"i"(sizeof(ulong))
9566 : "cc", "memory"
9567 #ifdef CONFIG_X86_64
9568 , "rax", "rbx", "rdi", "rsi"
9569 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9570 #else
9571 , "eax", "ebx", "edi", "esi"
9572 #endif
9573 );
9574
9575 /*
9576 * We do not use IBRS in the kernel. If this vCPU has used the
9577 * SPEC_CTRL MSR it may have left it on; save the value and
9578 * turn it off. This is much more efficient than blindly adding
9579 * it to the atomic save/restore list. Especially as the former
9580 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
9581 *
9582 * For non-nested case:
9583 * If the L01 MSR bitmap does not intercept the MSR, then we need to
9584 * save it.
9585 *
9586 * For nested case:
9587 * If the L02 MSR bitmap does not intercept the MSR, then we need to
9588 * save it.
9589 */
9590 if (!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))
9591 rdmsrl(MSR_IA32_SPEC_CTRL, vmx->spec_ctrl);
9592
9593 if (vmx->spec_ctrl)
9594 wrmsrl(MSR_IA32_SPEC_CTRL, 0);
9595
9596 /* Eliminate branch target predictions from guest mode */
9597 vmexit_fill_RSB();
9598
9599 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9600 if (vmx->host_debugctlmsr)
9601 update_debugctlmsr(vmx->host_debugctlmsr);
9602
9603 #ifndef CONFIG_X86_64
9604 /*
9605 * The sysexit path does not restore ds/es, so we must set them to
9606 * a reasonable value ourselves.
9607 *
9608 * We can't defer this to vmx_load_host_state() since that function
9609 * may be executed in interrupt context, which saves and restore segments
9610 * around it, nullifying its effect.
9611 */
9612 loadsegment(ds, __USER_DS);
9613 loadsegment(es, __USER_DS);
9614 #endif
9615
9616 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9617 | (1 << VCPU_EXREG_RFLAGS)
9618 | (1 << VCPU_EXREG_PDPTR)
9619 | (1 << VCPU_EXREG_SEGMENTS)
9620 | (1 << VCPU_EXREG_CR3));
9621 vcpu->arch.regs_dirty = 0;
9622
9623 /*
9624 * eager fpu is enabled if PKEY is supported and CR4 is switched
9625 * back on host, so it is safe to read guest PKRU from current
9626 * XSAVE.
9627 */
9628 if (static_cpu_has(X86_FEATURE_PKU) &&
9629 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
9630 vcpu->arch.pkru = __read_pkru();
9631 if (vcpu->arch.pkru != vmx->host_pkru)
9632 __write_pkru(vmx->host_pkru);
9633 }
9634
9635 /*
9636 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9637 * we did not inject a still-pending event to L1 now because of
9638 * nested_run_pending, we need to re-enable this bit.
9639 */
9640 if (vmx->nested.nested_run_pending)
9641 kvm_make_request(KVM_REQ_EVENT, vcpu);
9642
9643 vmx->nested.nested_run_pending = 0;
9644 vmx->idt_vectoring_info = 0;
9645
9646 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
9647 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9648 return;
9649
9650 vmx->loaded_vmcs->launched = 1;
9651 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9652
9653 vmx_complete_atomic_exit(vmx);
9654 vmx_recover_nmi_blocking(vmx);
9655 vmx_complete_interrupts(vmx);
9656 }
9657 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
9658
9659 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9660 {
9661 struct vcpu_vmx *vmx = to_vmx(vcpu);
9662 int cpu;
9663
9664 if (vmx->loaded_vmcs == vmcs)
9665 return;
9666
9667 cpu = get_cpu();
9668 vmx->loaded_vmcs = vmcs;
9669 vmx_vcpu_put(vcpu);
9670 vmx_vcpu_load(vcpu, cpu);
9671 put_cpu();
9672 }
9673
9674 /*
9675 * Ensure that the current vmcs of the logical processor is the
9676 * vmcs01 of the vcpu before calling free_nested().
9677 */
9678 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9679 {
9680 struct vcpu_vmx *vmx = to_vmx(vcpu);
9681
9682 vcpu_load(vcpu);
9683 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9684 free_nested(vmx);
9685 vcpu_put(vcpu);
9686 }
9687
9688 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9689 {
9690 struct vcpu_vmx *vmx = to_vmx(vcpu);
9691
9692 if (enable_pml)
9693 vmx_destroy_pml_buffer(vmx);
9694 free_vpid(vmx->vpid);
9695 leave_guest_mode(vcpu);
9696 vmx_free_vcpu_nested(vcpu);
9697 free_loaded_vmcs(vmx->loaded_vmcs);
9698 kfree(vmx->guest_msrs);
9699 kvm_vcpu_uninit(vcpu);
9700 kmem_cache_free(kvm_vcpu_cache, vmx);
9701 }
9702
9703 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9704 {
9705 int err;
9706 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9707 unsigned long *msr_bitmap;
9708 int cpu;
9709
9710 if (!vmx)
9711 return ERR_PTR(-ENOMEM);
9712
9713 vmx->vpid = allocate_vpid();
9714
9715 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9716 if (err)
9717 goto free_vcpu;
9718
9719 err = -ENOMEM;
9720
9721 /*
9722 * If PML is turned on, failure on enabling PML just results in failure
9723 * of creating the vcpu, therefore we can simplify PML logic (by
9724 * avoiding dealing with cases, such as enabling PML partially on vcpus
9725 * for the guest, etc.
9726 */
9727 if (enable_pml) {
9728 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9729 if (!vmx->pml_pg)
9730 goto uninit_vcpu;
9731 }
9732
9733 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9734 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9735 > PAGE_SIZE);
9736
9737 if (!vmx->guest_msrs)
9738 goto free_pml;
9739
9740 err = alloc_loaded_vmcs(&vmx->vmcs01);
9741 if (err < 0)
9742 goto free_msrs;
9743
9744 msr_bitmap = vmx->vmcs01.msr_bitmap;
9745 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
9746 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
9747 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
9748 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
9749 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
9750 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
9751 vmx->msr_bitmap_mode = 0;
9752
9753 vmx->loaded_vmcs = &vmx->vmcs01;
9754 cpu = get_cpu();
9755 vmx_vcpu_load(&vmx->vcpu, cpu);
9756 vmx->vcpu.cpu = cpu;
9757 vmx_vcpu_setup(vmx);
9758 vmx_vcpu_put(&vmx->vcpu);
9759 put_cpu();
9760 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9761 err = alloc_apic_access_page(kvm);
9762 if (err)
9763 goto free_vmcs;
9764 }
9765
9766 if (enable_ept) {
9767 err = init_rmode_identity_map(kvm);
9768 if (err)
9769 goto free_vmcs;
9770 }
9771
9772 if (nested) {
9773 nested_vmx_setup_ctls_msrs(vmx);
9774 vmx->nested.vpid02 = allocate_vpid();
9775 }
9776
9777 vmx->nested.posted_intr_nv = -1;
9778 vmx->nested.current_vmptr = -1ull;
9779
9780 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9781
9782 /*
9783 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9784 * or POSTED_INTR_WAKEUP_VECTOR.
9785 */
9786 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
9787 vmx->pi_desc.sn = 1;
9788
9789 return &vmx->vcpu;
9790
9791 free_vmcs:
9792 free_vpid(vmx->nested.vpid02);
9793 free_loaded_vmcs(vmx->loaded_vmcs);
9794 free_msrs:
9795 kfree(vmx->guest_msrs);
9796 free_pml:
9797 vmx_destroy_pml_buffer(vmx);
9798 uninit_vcpu:
9799 kvm_vcpu_uninit(&vmx->vcpu);
9800 free_vcpu:
9801 free_vpid(vmx->vpid);
9802 kmem_cache_free(kvm_vcpu_cache, vmx);
9803 return ERR_PTR(err);
9804 }
9805
9806 static void __init vmx_check_processor_compat(void *rtn)
9807 {
9808 struct vmcs_config vmcs_conf;
9809
9810 *(int *)rtn = 0;
9811 if (setup_vmcs_config(&vmcs_conf) < 0)
9812 *(int *)rtn = -EIO;
9813 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9814 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9815 smp_processor_id());
9816 *(int *)rtn = -EIO;
9817 }
9818 }
9819
9820 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9821 {
9822 u8 cache;
9823 u64 ipat = 0;
9824
9825 /* For VT-d and EPT combination
9826 * 1. MMIO: always map as UC
9827 * 2. EPT with VT-d:
9828 * a. VT-d without snooping control feature: can't guarantee the
9829 * result, try to trust guest.
9830 * b. VT-d with snooping control feature: snooping control feature of
9831 * VT-d engine can guarantee the cache correctness. Just set it
9832 * to WB to keep consistent with host. So the same as item 3.
9833 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9834 * consistent with host MTRR
9835 */
9836 if (is_mmio) {
9837 cache = MTRR_TYPE_UNCACHABLE;
9838 goto exit;
9839 }
9840
9841 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9842 ipat = VMX_EPT_IPAT_BIT;
9843 cache = MTRR_TYPE_WRBACK;
9844 goto exit;
9845 }
9846
9847 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9848 ipat = VMX_EPT_IPAT_BIT;
9849 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9850 cache = MTRR_TYPE_WRBACK;
9851 else
9852 cache = MTRR_TYPE_UNCACHABLE;
9853 goto exit;
9854 }
9855
9856 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9857
9858 exit:
9859 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9860 }
9861
9862 static int vmx_get_lpage_level(void)
9863 {
9864 if (enable_ept && !cpu_has_vmx_ept_1g_page())
9865 return PT_DIRECTORY_LEVEL;
9866 else
9867 /* For shadow and EPT supported 1GB page */
9868 return PT_PDPE_LEVEL;
9869 }
9870
9871 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9872 {
9873 /*
9874 * These bits in the secondary execution controls field
9875 * are dynamic, the others are mostly based on the hypervisor
9876 * architecture and the guest's CPUID. Do not touch the
9877 * dynamic bits.
9878 */
9879 u32 mask =
9880 SECONDARY_EXEC_SHADOW_VMCS |
9881 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9882 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9883 SECONDARY_EXEC_DESC;
9884
9885 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9886
9887 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9888 (new_ctl & ~mask) | (cur_ctl & mask));
9889 }
9890
9891 /*
9892 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9893 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9894 */
9895 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9896 {
9897 struct vcpu_vmx *vmx = to_vmx(vcpu);
9898 struct kvm_cpuid_entry2 *entry;
9899
9900 vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9901 vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9902
9903 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9904 if (entry && (entry->_reg & (_cpuid_mask))) \
9905 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9906 } while (0)
9907
9908 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9909 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
9910 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
9911 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
9912 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
9913 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
9914 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
9915 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
9916 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
9917 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
9918 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9919 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
9920 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
9921 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
9922 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
9923
9924 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9925 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
9926 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
9927 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
9928 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
9929 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
9930
9931 #undef cr4_fixed1_update
9932 }
9933
9934 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9935 {
9936 struct vcpu_vmx *vmx = to_vmx(vcpu);
9937
9938 if (cpu_has_secondary_exec_ctrls()) {
9939 vmx_compute_secondary_exec_control(vmx);
9940 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
9941 }
9942
9943 if (nested_vmx_allowed(vcpu))
9944 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9945 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9946 else
9947 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9948 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9949
9950 if (nested_vmx_allowed(vcpu))
9951 nested_vmx_cr_fixed1_bits_update(vcpu);
9952 }
9953
9954 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9955 {
9956 if (func == 1 && nested)
9957 entry->ecx |= bit(X86_FEATURE_VMX);
9958 }
9959
9960 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9961 struct x86_exception *fault)
9962 {
9963 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9964 struct vcpu_vmx *vmx = to_vmx(vcpu);
9965 u32 exit_reason;
9966 unsigned long exit_qualification = vcpu->arch.exit_qualification;
9967
9968 if (vmx->nested.pml_full) {
9969 exit_reason = EXIT_REASON_PML_FULL;
9970 vmx->nested.pml_full = false;
9971 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9972 } else if (fault->error_code & PFERR_RSVD_MASK)
9973 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9974 else
9975 exit_reason = EXIT_REASON_EPT_VIOLATION;
9976
9977 nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
9978 vmcs12->guest_physical_address = fault->address;
9979 }
9980
9981 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
9982 {
9983 return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
9984 }
9985
9986 /* Callbacks for nested_ept_init_mmu_context: */
9987
9988 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9989 {
9990 /* return the page table to be shadowed - in our case, EPT12 */
9991 return get_vmcs12(vcpu)->ept_pointer;
9992 }
9993
9994 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9995 {
9996 WARN_ON(mmu_is_nested(vcpu));
9997 if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu)))
9998 return 1;
9999
10000 kvm_mmu_unload(vcpu);
10001 kvm_init_shadow_ept_mmu(vcpu,
10002 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
10003 VMX_EPT_EXECUTE_ONLY_BIT,
10004 nested_ept_ad_enabled(vcpu));
10005 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
10006 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
10007 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
10008
10009 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
10010 return 0;
10011 }
10012
10013 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
10014 {
10015 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
10016 }
10017
10018 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
10019 u16 error_code)
10020 {
10021 bool inequality, bit;
10022
10023 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
10024 inequality =
10025 (error_code & vmcs12->page_fault_error_code_mask) !=
10026 vmcs12->page_fault_error_code_match;
10027 return inequality ^ bit;
10028 }
10029
10030 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
10031 struct x86_exception *fault)
10032 {
10033 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10034
10035 WARN_ON(!is_guest_mode(vcpu));
10036
10037 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
10038 !to_vmx(vcpu)->nested.nested_run_pending) {
10039 vmcs12->vm_exit_intr_error_code = fault->error_code;
10040 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10041 PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
10042 INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
10043 fault->address);
10044 } else {
10045 kvm_inject_page_fault(vcpu, fault);
10046 }
10047 }
10048
10049 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
10050 struct vmcs12 *vmcs12);
10051
10052 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
10053 struct vmcs12 *vmcs12)
10054 {
10055 struct vcpu_vmx *vmx = to_vmx(vcpu);
10056 struct page *page;
10057 u64 hpa;
10058
10059 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10060 /*
10061 * Translate L1 physical address to host physical
10062 * address for vmcs02. Keep the page pinned, so this
10063 * physical address remains valid. We keep a reference
10064 * to it so we can release it later.
10065 */
10066 if (vmx->nested.apic_access_page) { /* shouldn't happen */
10067 kvm_release_page_dirty(vmx->nested.apic_access_page);
10068 vmx->nested.apic_access_page = NULL;
10069 }
10070 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
10071 /*
10072 * If translation failed, no matter: This feature asks
10073 * to exit when accessing the given address, and if it
10074 * can never be accessed, this feature won't do
10075 * anything anyway.
10076 */
10077 if (!is_error_page(page)) {
10078 vmx->nested.apic_access_page = page;
10079 hpa = page_to_phys(vmx->nested.apic_access_page);
10080 vmcs_write64(APIC_ACCESS_ADDR, hpa);
10081 } else {
10082 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
10083 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
10084 }
10085 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
10086 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
10087 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
10088 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
10089 kvm_vcpu_reload_apic_access_page(vcpu);
10090 }
10091
10092 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
10093 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
10094 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
10095 vmx->nested.virtual_apic_page = NULL;
10096 }
10097 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
10098
10099 /*
10100 * If translation failed, VM entry will fail because
10101 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
10102 * Failing the vm entry is _not_ what the processor
10103 * does but it's basically the only possibility we
10104 * have. We could still enter the guest if CR8 load
10105 * exits are enabled, CR8 store exits are enabled, and
10106 * virtualize APIC access is disabled; in this case
10107 * the processor would never use the TPR shadow and we
10108 * could simply clear the bit from the execution
10109 * control. But such a configuration is useless, so
10110 * let's keep the code simple.
10111 */
10112 if (!is_error_page(page)) {
10113 vmx->nested.virtual_apic_page = page;
10114 hpa = page_to_phys(vmx->nested.virtual_apic_page);
10115 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
10116 }
10117 }
10118
10119 if (nested_cpu_has_posted_intr(vmcs12)) {
10120 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
10121 kunmap(vmx->nested.pi_desc_page);
10122 kvm_release_page_dirty(vmx->nested.pi_desc_page);
10123 vmx->nested.pi_desc_page = NULL;
10124 }
10125 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
10126 if (is_error_page(page))
10127 return;
10128 vmx->nested.pi_desc_page = page;
10129 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
10130 vmx->nested.pi_desc =
10131 (struct pi_desc *)((void *)vmx->nested.pi_desc +
10132 (unsigned long)(vmcs12->posted_intr_desc_addr &
10133 (PAGE_SIZE - 1)));
10134 vmcs_write64(POSTED_INTR_DESC_ADDR,
10135 page_to_phys(vmx->nested.pi_desc_page) +
10136 (unsigned long)(vmcs12->posted_intr_desc_addr &
10137 (PAGE_SIZE - 1)));
10138 }
10139 if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
10140 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
10141 CPU_BASED_USE_MSR_BITMAPS);
10142 else
10143 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
10144 CPU_BASED_USE_MSR_BITMAPS);
10145 }
10146
10147 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
10148 {
10149 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
10150 struct vcpu_vmx *vmx = to_vmx(vcpu);
10151
10152 if (vcpu->arch.virtual_tsc_khz == 0)
10153 return;
10154
10155 /* Make sure short timeouts reliably trigger an immediate vmexit.
10156 * hrtimer_start does not guarantee this. */
10157 if (preemption_timeout <= 1) {
10158 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
10159 return;
10160 }
10161
10162 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10163 preemption_timeout *= 1000000;
10164 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
10165 hrtimer_start(&vmx->nested.preemption_timer,
10166 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
10167 }
10168
10169 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
10170 struct vmcs12 *vmcs12)
10171 {
10172 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
10173 return 0;
10174
10175 if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
10176 !page_address_valid(vcpu, vmcs12->io_bitmap_b))
10177 return -EINVAL;
10178
10179 return 0;
10180 }
10181
10182 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
10183 struct vmcs12 *vmcs12)
10184 {
10185 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10186 return 0;
10187
10188 if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
10189 return -EINVAL;
10190
10191 return 0;
10192 }
10193
10194 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
10195 struct vmcs12 *vmcs12)
10196 {
10197 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10198 return 0;
10199
10200 if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
10201 return -EINVAL;
10202
10203 return 0;
10204 }
10205
10206 /*
10207 * Merge L0's and L1's MSR bitmap, return false to indicate that
10208 * we do not use the hardware.
10209 */
10210 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
10211 struct vmcs12 *vmcs12)
10212 {
10213 int msr;
10214 struct page *page;
10215 unsigned long *msr_bitmap_l1;
10216 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
10217 /*
10218 * pred_cmd & spec_ctrl are trying to verify two things:
10219 *
10220 * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
10221 * ensures that we do not accidentally generate an L02 MSR bitmap
10222 * from the L12 MSR bitmap that is too permissive.
10223 * 2. That L1 or L2s have actually used the MSR. This avoids
10224 * unnecessarily merging of the bitmap if the MSR is unused. This
10225 * works properly because we only update the L01 MSR bitmap lazily.
10226 * So even if L0 should pass L1 these MSRs, the L01 bitmap is only
10227 * updated to reflect this when L1 (or its L2s) actually write to
10228 * the MSR.
10229 */
10230 bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
10231 bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
10232
10233 /* Nothing to do if the MSR bitmap is not in use. */
10234 if (!cpu_has_vmx_msr_bitmap() ||
10235 !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10236 return false;
10237
10238 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10239 !pred_cmd && !spec_ctrl)
10240 return false;
10241
10242 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
10243 if (is_error_page(page))
10244 return false;
10245
10246 msr_bitmap_l1 = (unsigned long *)kmap(page);
10247 if (nested_cpu_has_apic_reg_virt(vmcs12)) {
10248 /*
10249 * L0 need not intercept reads for MSRs between 0x800 and 0x8ff, it
10250 * just lets the processor take the value from the virtual-APIC page;
10251 * take those 256 bits directly from the L1 bitmap.
10252 */
10253 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
10254 unsigned word = msr / BITS_PER_LONG;
10255 msr_bitmap_l0[word] = msr_bitmap_l1[word];
10256 msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
10257 }
10258 } else {
10259 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
10260 unsigned word = msr / BITS_PER_LONG;
10261 msr_bitmap_l0[word] = ~0;
10262 msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
10263 }
10264 }
10265
10266 nested_vmx_disable_intercept_for_msr(
10267 msr_bitmap_l1, msr_bitmap_l0,
10268 X2APIC_MSR(APIC_TASKPRI),
10269 MSR_TYPE_W);
10270
10271 if (nested_cpu_has_vid(vmcs12)) {
10272 nested_vmx_disable_intercept_for_msr(
10273 msr_bitmap_l1, msr_bitmap_l0,
10274 X2APIC_MSR(APIC_EOI),
10275 MSR_TYPE_W);
10276 nested_vmx_disable_intercept_for_msr(
10277 msr_bitmap_l1, msr_bitmap_l0,
10278 X2APIC_MSR(APIC_SELF_IPI),
10279 MSR_TYPE_W);
10280 }
10281
10282 if (spec_ctrl)
10283 nested_vmx_disable_intercept_for_msr(
10284 msr_bitmap_l1, msr_bitmap_l0,
10285 MSR_IA32_SPEC_CTRL,
10286 MSR_TYPE_R | MSR_TYPE_W);
10287
10288 if (pred_cmd)
10289 nested_vmx_disable_intercept_for_msr(
10290 msr_bitmap_l1, msr_bitmap_l0,
10291 MSR_IA32_PRED_CMD,
10292 MSR_TYPE_W);
10293
10294 kunmap(page);
10295 kvm_release_page_clean(page);
10296
10297 return true;
10298 }
10299
10300 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
10301 struct vmcs12 *vmcs12)
10302 {
10303 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10304 !nested_cpu_has_apic_reg_virt(vmcs12) &&
10305 !nested_cpu_has_vid(vmcs12) &&
10306 !nested_cpu_has_posted_intr(vmcs12))
10307 return 0;
10308
10309 /*
10310 * If virtualize x2apic mode is enabled,
10311 * virtualize apic access must be disabled.
10312 */
10313 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10314 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
10315 return -EINVAL;
10316
10317 /*
10318 * If virtual interrupt delivery is enabled,
10319 * we must exit on external interrupts.
10320 */
10321 if (nested_cpu_has_vid(vmcs12) &&
10322 !nested_exit_on_intr(vcpu))
10323 return -EINVAL;
10324
10325 /*
10326 * bits 15:8 should be zero in posted_intr_nv,
10327 * the descriptor address has been already checked
10328 * in nested_get_vmcs12_pages.
10329 */
10330 if (nested_cpu_has_posted_intr(vmcs12) &&
10331 (!nested_cpu_has_vid(vmcs12) ||
10332 !nested_exit_intr_ack_set(vcpu) ||
10333 vmcs12->posted_intr_nv & 0xff00))
10334 return -EINVAL;
10335
10336 /* tpr shadow is needed by all apicv features. */
10337 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10338 return -EINVAL;
10339
10340 return 0;
10341 }
10342
10343 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
10344 unsigned long count_field,
10345 unsigned long addr_field)
10346 {
10347 int maxphyaddr;
10348 u64 count, addr;
10349
10350 if (vmcs12_read_any(vcpu, count_field, &count) ||
10351 vmcs12_read_any(vcpu, addr_field, &addr)) {
10352 WARN_ON(1);
10353 return -EINVAL;
10354 }
10355 if (count == 0)
10356 return 0;
10357 maxphyaddr = cpuid_maxphyaddr(vcpu);
10358 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
10359 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
10360 pr_debug_ratelimited(
10361 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10362 addr_field, maxphyaddr, count, addr);
10363 return -EINVAL;
10364 }
10365 return 0;
10366 }
10367
10368 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
10369 struct vmcs12 *vmcs12)
10370 {
10371 if (vmcs12->vm_exit_msr_load_count == 0 &&
10372 vmcs12->vm_exit_msr_store_count == 0 &&
10373 vmcs12->vm_entry_msr_load_count == 0)
10374 return 0; /* Fast path */
10375 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
10376 VM_EXIT_MSR_LOAD_ADDR) ||
10377 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
10378 VM_EXIT_MSR_STORE_ADDR) ||
10379 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
10380 VM_ENTRY_MSR_LOAD_ADDR))
10381 return -EINVAL;
10382 return 0;
10383 }
10384
10385 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
10386 struct vmcs12 *vmcs12)
10387 {
10388 u64 address = vmcs12->pml_address;
10389 int maxphyaddr = cpuid_maxphyaddr(vcpu);
10390
10391 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
10392 if (!nested_cpu_has_ept(vmcs12) ||
10393 !IS_ALIGNED(address, 4096) ||
10394 address >> maxphyaddr)
10395 return -EINVAL;
10396 }
10397
10398 return 0;
10399 }
10400
10401 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
10402 struct vmx_msr_entry *e)
10403 {
10404 /* x2APIC MSR accesses are not allowed */
10405 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
10406 return -EINVAL;
10407 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
10408 e->index == MSR_IA32_UCODE_REV)
10409 return -EINVAL;
10410 if (e->reserved != 0)
10411 return -EINVAL;
10412 return 0;
10413 }
10414
10415 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
10416 struct vmx_msr_entry *e)
10417 {
10418 if (e->index == MSR_FS_BASE ||
10419 e->index == MSR_GS_BASE ||
10420 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
10421 nested_vmx_msr_check_common(vcpu, e))
10422 return -EINVAL;
10423 return 0;
10424 }
10425
10426 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
10427 struct vmx_msr_entry *e)
10428 {
10429 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
10430 nested_vmx_msr_check_common(vcpu, e))
10431 return -EINVAL;
10432 return 0;
10433 }
10434
10435 /*
10436 * Load guest's/host's msr at nested entry/exit.
10437 * return 0 for success, entry index for failure.
10438 */
10439 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10440 {
10441 u32 i;
10442 struct vmx_msr_entry e;
10443 struct msr_data msr;
10444
10445 msr.host_initiated = false;
10446 for (i = 0; i < count; i++) {
10447 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
10448 &e, sizeof(e))) {
10449 pr_debug_ratelimited(
10450 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10451 __func__, i, gpa + i * sizeof(e));
10452 goto fail;
10453 }
10454 if (nested_vmx_load_msr_check(vcpu, &e)) {
10455 pr_debug_ratelimited(
10456 "%s check failed (%u, 0x%x, 0x%x)\n",
10457 __func__, i, e.index, e.reserved);
10458 goto fail;
10459 }
10460 msr.index = e.index;
10461 msr.data = e.value;
10462 if (kvm_set_msr(vcpu, &msr)) {
10463 pr_debug_ratelimited(
10464 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10465 __func__, i, e.index, e.value);
10466 goto fail;
10467 }
10468 }
10469 return 0;
10470 fail:
10471 return i + 1;
10472 }
10473
10474 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10475 {
10476 u32 i;
10477 struct vmx_msr_entry e;
10478
10479 for (i = 0; i < count; i++) {
10480 struct msr_data msr_info;
10481 if (kvm_vcpu_read_guest(vcpu,
10482 gpa + i * sizeof(e),
10483 &e, 2 * sizeof(u32))) {
10484 pr_debug_ratelimited(
10485 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10486 __func__, i, gpa + i * sizeof(e));
10487 return -EINVAL;
10488 }
10489 if (nested_vmx_store_msr_check(vcpu, &e)) {
10490 pr_debug_ratelimited(
10491 "%s check failed (%u, 0x%x, 0x%x)\n",
10492 __func__, i, e.index, e.reserved);
10493 return -EINVAL;
10494 }
10495 msr_info.host_initiated = false;
10496 msr_info.index = e.index;
10497 if (kvm_get_msr(vcpu, &msr_info)) {
10498 pr_debug_ratelimited(
10499 "%s cannot read MSR (%u, 0x%x)\n",
10500 __func__, i, e.index);
10501 return -EINVAL;
10502 }
10503 if (kvm_vcpu_write_guest(vcpu,
10504 gpa + i * sizeof(e) +
10505 offsetof(struct vmx_msr_entry, value),
10506 &msr_info.data, sizeof(msr_info.data))) {
10507 pr_debug_ratelimited(
10508 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10509 __func__, i, e.index, msr_info.data);
10510 return -EINVAL;
10511 }
10512 }
10513 return 0;
10514 }
10515
10516 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
10517 {
10518 unsigned long invalid_mask;
10519
10520 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
10521 return (val & invalid_mask) == 0;
10522 }
10523
10524 /*
10525 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10526 * emulating VM entry into a guest with EPT enabled.
10527 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10528 * is assigned to entry_failure_code on failure.
10529 */
10530 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
10531 u32 *entry_failure_code)
10532 {
10533 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
10534 if (!nested_cr3_valid(vcpu, cr3)) {
10535 *entry_failure_code = ENTRY_FAIL_DEFAULT;
10536 return 1;
10537 }
10538
10539 /*
10540 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10541 * must not be dereferenced.
10542 */
10543 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
10544 !nested_ept) {
10545 if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
10546 *entry_failure_code = ENTRY_FAIL_PDPTE;
10547 return 1;
10548 }
10549 }
10550
10551 vcpu->arch.cr3 = cr3;
10552 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
10553 }
10554
10555 kvm_mmu_reset_context(vcpu);
10556 return 0;
10557 }
10558
10559 static void prepare_vmcs02_full(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10560 bool from_vmentry)
10561 {
10562 struct vcpu_vmx *vmx = to_vmx(vcpu);
10563
10564 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10565 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10566 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10567 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10568 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10569 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10570 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10571 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10572 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10573 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10574 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10575 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10576 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10577 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10578 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10579 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10580 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10581 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10582 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10583 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10584 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10585 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10586 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10587 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10588 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10589 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10590 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10591 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10592 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10593 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10594 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10595
10596 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10597 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10598 vmcs12->guest_pending_dbg_exceptions);
10599 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10600 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10601
10602 if (nested_cpu_has_xsaves(vmcs12))
10603 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10604 vmcs_write64(VMCS_LINK_POINTER, -1ull);
10605
10606 if (cpu_has_vmx_posted_intr())
10607 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
10608
10609 /*
10610 * Whether page-faults are trapped is determined by a combination of
10611 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10612 * If enable_ept, L0 doesn't care about page faults and we should
10613 * set all of these to L1's desires. However, if !enable_ept, L0 does
10614 * care about (at least some) page faults, and because it is not easy
10615 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10616 * to exit on each and every L2 page fault. This is done by setting
10617 * MASK=MATCH=0 and (see below) EB.PF=1.
10618 * Note that below we don't need special code to set EB.PF beyond the
10619 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10620 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10621 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10622 */
10623 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10624 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10625 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10626 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10627
10628 /* All VMFUNCs are currently emulated through L0 vmexits. */
10629 if (cpu_has_vmx_vmfunc())
10630 vmcs_write64(VM_FUNCTION_CONTROL, 0);
10631
10632 if (cpu_has_vmx_apicv()) {
10633 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0);
10634 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1);
10635 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2);
10636 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3);
10637 }
10638
10639 /*
10640 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10641 * Some constant fields are set here by vmx_set_constant_host_state().
10642 * Other fields are different per CPU, and will be set later when
10643 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10644 */
10645 vmx_set_constant_host_state(vmx);
10646
10647 /*
10648 * Set the MSR load/store lists to match L0's settings.
10649 */
10650 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10651 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10652 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10653 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10654 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10655
10656 set_cr4_guest_host_mask(vmx);
10657
10658 if (vmx_mpx_supported())
10659 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10660
10661 if (enable_vpid) {
10662 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
10663 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10664 else
10665 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10666 }
10667
10668 /*
10669 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10670 */
10671 if (enable_ept) {
10672 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10673 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10674 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10675 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10676 }
10677
10678 if (cpu_has_vmx_msr_bitmap())
10679 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
10680 }
10681
10682 /*
10683 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10684 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10685 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10686 * guest in a way that will both be appropriate to L1's requests, and our
10687 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10688 * function also has additional necessary side-effects, like setting various
10689 * vcpu->arch fields.
10690 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10691 * is assigned to entry_failure_code on failure.
10692 */
10693 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10694 bool from_vmentry, u32 *entry_failure_code)
10695 {
10696 struct vcpu_vmx *vmx = to_vmx(vcpu);
10697 u32 exec_control, vmcs12_exec_ctrl;
10698
10699 /*
10700 * First, the fields that are shadowed. This must be kept in sync
10701 * with vmx_shadow_fields.h.
10702 */
10703
10704 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10705 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10706 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10707 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10708 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10709
10710 /*
10711 * Not in vmcs02: GUEST_PML_INDEX, HOST_FS_SELECTOR, HOST_GS_SELECTOR,
10712 * HOST_FS_BASE, HOST_GS_BASE.
10713 */
10714
10715 if (from_vmentry &&
10716 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10717 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10718 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10719 } else {
10720 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10721 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10722 }
10723 if (from_vmentry) {
10724 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10725 vmcs12->vm_entry_intr_info_field);
10726 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10727 vmcs12->vm_entry_exception_error_code);
10728 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10729 vmcs12->vm_entry_instruction_len);
10730 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10731 vmcs12->guest_interruptibility_info);
10732 vmx->loaded_vmcs->nmi_known_unmasked =
10733 !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
10734 } else {
10735 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10736 }
10737 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10738
10739 exec_control = vmcs12->pin_based_vm_exec_control;
10740
10741 /* Preemption timer setting is only taken from vmcs01. */
10742 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10743 exec_control |= vmcs_config.pin_based_exec_ctrl;
10744 if (vmx->hv_deadline_tsc == -1)
10745 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10746
10747 /* Posted interrupts setting is only taken from vmcs12. */
10748 if (nested_cpu_has_posted_intr(vmcs12)) {
10749 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10750 vmx->nested.pi_pending = false;
10751 } else {
10752 exec_control &= ~PIN_BASED_POSTED_INTR;
10753 }
10754
10755 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10756
10757 vmx->nested.preemption_timer_expired = false;
10758 if (nested_cpu_has_preemption_timer(vmcs12))
10759 vmx_start_preemption_timer(vcpu);
10760
10761 if (cpu_has_secondary_exec_ctrls()) {
10762 exec_control = vmx->secondary_exec_control;
10763
10764 /* Take the following fields only from vmcs12 */
10765 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10766 SECONDARY_EXEC_ENABLE_INVPCID |
10767 SECONDARY_EXEC_RDTSCP |
10768 SECONDARY_EXEC_XSAVES |
10769 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10770 SECONDARY_EXEC_APIC_REGISTER_VIRT |
10771 SECONDARY_EXEC_ENABLE_VMFUNC);
10772 if (nested_cpu_has(vmcs12,
10773 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10774 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10775 ~SECONDARY_EXEC_ENABLE_PML;
10776 exec_control |= vmcs12_exec_ctrl;
10777 }
10778
10779 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
10780 vmcs_write16(GUEST_INTR_STATUS,
10781 vmcs12->guest_intr_status);
10782
10783 /*
10784 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10785 * nested_get_vmcs12_pages will either fix it up or
10786 * remove the VM execution control.
10787 */
10788 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10789 vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10790
10791 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10792 }
10793
10794 /*
10795 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10796 * entry, but only if the current (host) sp changed from the value
10797 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10798 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10799 * here we just force the write to happen on entry.
10800 */
10801 vmx->host_rsp = 0;
10802
10803 exec_control = vmx_exec_control(vmx); /* L0's desires */
10804 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10805 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10806 exec_control &= ~CPU_BASED_TPR_SHADOW;
10807 exec_control |= vmcs12->cpu_based_vm_exec_control;
10808
10809 /*
10810 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10811 * nested_get_vmcs12_pages can't fix it up, the illegal value
10812 * will result in a VM entry failure.
10813 */
10814 if (exec_control & CPU_BASED_TPR_SHADOW) {
10815 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10816 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10817 } else {
10818 #ifdef CONFIG_X86_64
10819 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
10820 CPU_BASED_CR8_STORE_EXITING;
10821 #endif
10822 }
10823
10824 /*
10825 * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
10826 * for I/O port accesses.
10827 */
10828 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10829 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10830
10831 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10832
10833 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10834 * bitwise-or of what L1 wants to trap for L2, and what we want to
10835 * trap. Note that CR0.TS also needs updating - we do this later.
10836 */
10837 update_exception_bitmap(vcpu);
10838 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10839 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10840
10841 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10842 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10843 * bits are further modified by vmx_set_efer() below.
10844 */
10845 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10846
10847 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10848 * emulated by vmx_set_efer(), below.
10849 */
10850 vm_entry_controls_init(vmx,
10851 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10852 ~VM_ENTRY_IA32E_MODE) |
10853 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10854
10855 if (from_vmentry &&
10856 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10857 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10858 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10859 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10860 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10861 }
10862
10863 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10864 vmcs_write64(TSC_OFFSET,
10865 vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10866 else
10867 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10868 if (kvm_has_tsc_control)
10869 decache_tsc_multiplier(vmx);
10870
10871 if (enable_vpid) {
10872 /*
10873 * There is no direct mapping between vpid02 and vpid12, the
10874 * vpid02 is per-vCPU for L0 and reused while the value of
10875 * vpid12 is changed w/ one invvpid during nested vmentry.
10876 * The vpid12 is allocated by L1 for L2, so it will not
10877 * influence global bitmap(for vpid01 and vpid02 allocation)
10878 * even if spawn a lot of nested vCPUs.
10879 */
10880 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10881 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10882 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10883 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02, true);
10884 }
10885 } else {
10886 vmx_flush_tlb(vcpu, true);
10887 }
10888 }
10889
10890 if (enable_pml) {
10891 /*
10892 * Conceptually we want to copy the PML address and index from
10893 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10894 * since we always flush the log on each vmexit, this happens
10895 * to be equivalent to simply resetting the fields in vmcs02.
10896 */
10897 ASSERT(vmx->pml_pg);
10898 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10899 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10900 }
10901
10902 if (nested_cpu_has_ept(vmcs12)) {
10903 if (nested_ept_init_mmu_context(vcpu)) {
10904 *entry_failure_code = ENTRY_FAIL_DEFAULT;
10905 return 1;
10906 }
10907 } else if (nested_cpu_has2(vmcs12,
10908 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10909 vmx_flush_tlb_ept_only(vcpu);
10910 }
10911
10912 /*
10913 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10914 * bits which we consider mandatory enabled.
10915 * The CR0_READ_SHADOW is what L2 should have expected to read given
10916 * the specifications by L1; It's not enough to take
10917 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10918 * have more bits than L1 expected.
10919 */
10920 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10921 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10922
10923 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10924 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10925
10926 if (from_vmentry &&
10927 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10928 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10929 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10930 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10931 else
10932 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10933 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10934 vmx_set_efer(vcpu, vcpu->arch.efer);
10935
10936 if (vmx->nested.dirty_vmcs12) {
10937 prepare_vmcs02_full(vcpu, vmcs12, from_vmentry);
10938 vmx->nested.dirty_vmcs12 = false;
10939 }
10940
10941 /* Shadow page tables on either EPT or shadow page tables. */
10942 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10943 entry_failure_code))
10944 return 1;
10945
10946 if (!enable_ept)
10947 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10948
10949 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10950 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10951 return 0;
10952 }
10953
10954 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10955 {
10956 struct vcpu_vmx *vmx = to_vmx(vcpu);
10957
10958 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10959 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10960 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10961
10962 if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
10963 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10964
10965 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10966 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10967
10968 if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
10969 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10970
10971 if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10972 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10973
10974 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10975 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10976
10977 if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10978 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10979
10980 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10981 vmx->nested.nested_vmx_procbased_ctls_low,
10982 vmx->nested.nested_vmx_procbased_ctls_high) ||
10983 (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10984 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10985 vmx->nested.nested_vmx_secondary_ctls_low,
10986 vmx->nested.nested_vmx_secondary_ctls_high)) ||
10987 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10988 vmx->nested.nested_vmx_pinbased_ctls_low,
10989 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10990 !vmx_control_verify(vmcs12->vm_exit_controls,
10991 vmx->nested.nested_vmx_exit_ctls_low,
10992 vmx->nested.nested_vmx_exit_ctls_high) ||
10993 !vmx_control_verify(vmcs12->vm_entry_controls,
10994 vmx->nested.nested_vmx_entry_ctls_low,
10995 vmx->nested.nested_vmx_entry_ctls_high))
10996 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10997
10998 if (nested_cpu_has_vmfunc(vmcs12)) {
10999 if (vmcs12->vm_function_control &
11000 ~vmx->nested.nested_vmx_vmfunc_controls)
11001 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11002
11003 if (nested_cpu_has_eptp_switching(vmcs12)) {
11004 if (!nested_cpu_has_ept(vmcs12) ||
11005 !page_address_valid(vcpu, vmcs12->eptp_list_address))
11006 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11007 }
11008 }
11009
11010 if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
11011 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11012
11013 if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
11014 !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
11015 !nested_cr3_valid(vcpu, vmcs12->host_cr3))
11016 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
11017
11018 return 0;
11019 }
11020
11021 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11022 u32 *exit_qual)
11023 {
11024 bool ia32e;
11025
11026 *exit_qual = ENTRY_FAIL_DEFAULT;
11027
11028 if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
11029 !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
11030 return 1;
11031
11032 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
11033 vmcs12->vmcs_link_pointer != -1ull) {
11034 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
11035 return 1;
11036 }
11037
11038 /*
11039 * If the load IA32_EFER VM-entry control is 1, the following checks
11040 * are performed on the field for the IA32_EFER MSR:
11041 * - Bits reserved in the IA32_EFER MSR must be 0.
11042 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
11043 * the IA-32e mode guest VM-exit control. It must also be identical
11044 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
11045 * CR0.PG) is 1.
11046 */
11047 if (to_vmx(vcpu)->nested.nested_run_pending &&
11048 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
11049 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
11050 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
11051 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
11052 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
11053 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
11054 return 1;
11055 }
11056
11057 /*
11058 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
11059 * IA32_EFER MSR must be 0 in the field for that register. In addition,
11060 * the values of the LMA and LME bits in the field must each be that of
11061 * the host address-space size VM-exit control.
11062 */
11063 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
11064 ia32e = (vmcs12->vm_exit_controls &
11065 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
11066 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
11067 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
11068 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
11069 return 1;
11070 }
11071
11072 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
11073 (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) ||
11074 (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))
11075 return 1;
11076
11077 return 0;
11078 }
11079
11080 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
11081 {
11082 struct vcpu_vmx *vmx = to_vmx(vcpu);
11083 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11084 u32 msr_entry_idx;
11085 u32 exit_qual;
11086
11087 enter_guest_mode(vcpu);
11088
11089 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
11090 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11091
11092 vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
11093 vmx_segment_cache_clear(vmx);
11094
11095 if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
11096 leave_guest_mode(vcpu);
11097 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11098 nested_vmx_entry_failure(vcpu, vmcs12,
11099 EXIT_REASON_INVALID_STATE, exit_qual);
11100 return 1;
11101 }
11102
11103 nested_get_vmcs12_pages(vcpu, vmcs12);
11104
11105 msr_entry_idx = nested_vmx_load_msr(vcpu,
11106 vmcs12->vm_entry_msr_load_addr,
11107 vmcs12->vm_entry_msr_load_count);
11108 if (msr_entry_idx) {
11109 leave_guest_mode(vcpu);
11110 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11111 nested_vmx_entry_failure(vcpu, vmcs12,
11112 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
11113 return 1;
11114 }
11115
11116 /*
11117 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
11118 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
11119 * returned as far as L1 is concerned. It will only return (and set
11120 * the success flag) when L2 exits (see nested_vmx_vmexit()).
11121 */
11122 return 0;
11123 }
11124
11125 /*
11126 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
11127 * for running an L2 nested guest.
11128 */
11129 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
11130 {
11131 struct vmcs12 *vmcs12;
11132 struct vcpu_vmx *vmx = to_vmx(vcpu);
11133 u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
11134 u32 exit_qual;
11135 int ret;
11136
11137 if (!nested_vmx_check_permission(vcpu))
11138 return 1;
11139
11140 if (!nested_vmx_check_vmcs12(vcpu))
11141 goto out;
11142
11143 vmcs12 = get_vmcs12(vcpu);
11144
11145 if (enable_shadow_vmcs)
11146 copy_shadow_to_vmcs12(vmx);
11147
11148 /*
11149 * The nested entry process starts with enforcing various prerequisites
11150 * on vmcs12 as required by the Intel SDM, and act appropriately when
11151 * they fail: As the SDM explains, some conditions should cause the
11152 * instruction to fail, while others will cause the instruction to seem
11153 * to succeed, but return an EXIT_REASON_INVALID_STATE.
11154 * To speed up the normal (success) code path, we should avoid checking
11155 * for misconfigurations which will anyway be caught by the processor
11156 * when using the merged vmcs02.
11157 */
11158 if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
11159 nested_vmx_failValid(vcpu,
11160 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
11161 goto out;
11162 }
11163
11164 if (vmcs12->launch_state == launch) {
11165 nested_vmx_failValid(vcpu,
11166 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
11167 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
11168 goto out;
11169 }
11170
11171 ret = check_vmentry_prereqs(vcpu, vmcs12);
11172 if (ret) {
11173 nested_vmx_failValid(vcpu, ret);
11174 goto out;
11175 }
11176
11177 /*
11178 * After this point, the trap flag no longer triggers a singlestep trap
11179 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
11180 * This is not 100% correct; for performance reasons, we delegate most
11181 * of the checks on host state to the processor. If those fail,
11182 * the singlestep trap is missed.
11183 */
11184 skip_emulated_instruction(vcpu);
11185
11186 ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
11187 if (ret) {
11188 nested_vmx_entry_failure(vcpu, vmcs12,
11189 EXIT_REASON_INVALID_STATE, exit_qual);
11190 return 1;
11191 }
11192
11193 /*
11194 * We're finally done with prerequisite checking, and can start with
11195 * the nested entry.
11196 */
11197
11198 ret = enter_vmx_non_root_mode(vcpu, true);
11199 if (ret)
11200 return ret;
11201
11202 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
11203 return kvm_vcpu_halt(vcpu);
11204
11205 vmx->nested.nested_run_pending = 1;
11206
11207 return 1;
11208
11209 out:
11210 return kvm_skip_emulated_instruction(vcpu);
11211 }
11212
11213 /*
11214 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
11215 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
11216 * This function returns the new value we should put in vmcs12.guest_cr0.
11217 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
11218 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
11219 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
11220 * didn't trap the bit, because if L1 did, so would L0).
11221 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
11222 * been modified by L2, and L1 knows it. So just leave the old value of
11223 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
11224 * isn't relevant, because if L0 traps this bit it can set it to anything.
11225 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
11226 * changed these bits, and therefore they need to be updated, but L0
11227 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
11228 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
11229 */
11230 static inline unsigned long
11231 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11232 {
11233 return
11234 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
11235 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
11236 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
11237 vcpu->arch.cr0_guest_owned_bits));
11238 }
11239
11240 static inline unsigned long
11241 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11242 {
11243 return
11244 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
11245 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
11246 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
11247 vcpu->arch.cr4_guest_owned_bits));
11248 }
11249
11250 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
11251 struct vmcs12 *vmcs12)
11252 {
11253 u32 idt_vectoring;
11254 unsigned int nr;
11255
11256 if (vcpu->arch.exception.injected) {
11257 nr = vcpu->arch.exception.nr;
11258 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11259
11260 if (kvm_exception_is_soft(nr)) {
11261 vmcs12->vm_exit_instruction_len =
11262 vcpu->arch.event_exit_inst_len;
11263 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
11264 } else
11265 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
11266
11267 if (vcpu->arch.exception.has_error_code) {
11268 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
11269 vmcs12->idt_vectoring_error_code =
11270 vcpu->arch.exception.error_code;
11271 }
11272
11273 vmcs12->idt_vectoring_info_field = idt_vectoring;
11274 } else if (vcpu->arch.nmi_injected) {
11275 vmcs12->idt_vectoring_info_field =
11276 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
11277 } else if (vcpu->arch.interrupt.pending) {
11278 nr = vcpu->arch.interrupt.nr;
11279 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11280
11281 if (vcpu->arch.interrupt.soft) {
11282 idt_vectoring |= INTR_TYPE_SOFT_INTR;
11283 vmcs12->vm_entry_instruction_len =
11284 vcpu->arch.event_exit_inst_len;
11285 } else
11286 idt_vectoring |= INTR_TYPE_EXT_INTR;
11287
11288 vmcs12->idt_vectoring_info_field = idt_vectoring;
11289 }
11290 }
11291
11292 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
11293 {
11294 struct vcpu_vmx *vmx = to_vmx(vcpu);
11295 unsigned long exit_qual;
11296 bool block_nested_events =
11297 vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
11298
11299 if (vcpu->arch.exception.pending &&
11300 nested_vmx_check_exception(vcpu, &exit_qual)) {
11301 if (block_nested_events)
11302 return -EBUSY;
11303 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
11304 return 0;
11305 }
11306
11307 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
11308 vmx->nested.preemption_timer_expired) {
11309 if (block_nested_events)
11310 return -EBUSY;
11311 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
11312 return 0;
11313 }
11314
11315 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
11316 if (block_nested_events)
11317 return -EBUSY;
11318 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
11319 NMI_VECTOR | INTR_TYPE_NMI_INTR |
11320 INTR_INFO_VALID_MASK, 0);
11321 /*
11322 * The NMI-triggered VM exit counts as injection:
11323 * clear this one and block further NMIs.
11324 */
11325 vcpu->arch.nmi_pending = 0;
11326 vmx_set_nmi_mask(vcpu, true);
11327 return 0;
11328 }
11329
11330 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
11331 nested_exit_on_intr(vcpu)) {
11332 if (block_nested_events)
11333 return -EBUSY;
11334 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
11335 return 0;
11336 }
11337
11338 vmx_complete_nested_posted_interrupt(vcpu);
11339 return 0;
11340 }
11341
11342 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
11343 {
11344 ktime_t remaining =
11345 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
11346 u64 value;
11347
11348 if (ktime_to_ns(remaining) <= 0)
11349 return 0;
11350
11351 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
11352 do_div(value, 1000000);
11353 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
11354 }
11355
11356 /*
11357 * Update the guest state fields of vmcs12 to reflect changes that
11358 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11359 * VM-entry controls is also updated, since this is really a guest
11360 * state bit.)
11361 */
11362 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11363 {
11364 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
11365 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
11366
11367 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
11368 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
11369 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
11370
11371 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
11372 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
11373 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
11374 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
11375 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
11376 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
11377 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
11378 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
11379 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
11380 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
11381 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
11382 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
11383 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
11384 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
11385 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
11386 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
11387 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
11388 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
11389 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
11390 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
11391 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
11392 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
11393 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
11394 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
11395 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
11396 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
11397 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
11398 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
11399 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
11400 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
11401 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
11402 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
11403 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
11404 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
11405 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
11406 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
11407
11408 vmcs12->guest_interruptibility_info =
11409 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
11410 vmcs12->guest_pending_dbg_exceptions =
11411 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
11412 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
11413 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
11414 else
11415 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
11416
11417 if (nested_cpu_has_preemption_timer(vmcs12)) {
11418 if (vmcs12->vm_exit_controls &
11419 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
11420 vmcs12->vmx_preemption_timer_value =
11421 vmx_get_preemption_timer_value(vcpu);
11422 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
11423 }
11424
11425 /*
11426 * In some cases (usually, nested EPT), L2 is allowed to change its
11427 * own CR3 without exiting. If it has changed it, we must keep it.
11428 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11429 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11430 *
11431 * Additionally, restore L2's PDPTR to vmcs12.
11432 */
11433 if (enable_ept) {
11434 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
11435 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
11436 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
11437 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
11438 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
11439 }
11440
11441 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
11442
11443 if (nested_cpu_has_vid(vmcs12))
11444 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
11445
11446 vmcs12->vm_entry_controls =
11447 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
11448 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
11449
11450 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
11451 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
11452 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11453 }
11454
11455 /* TODO: These cannot have changed unless we have MSR bitmaps and
11456 * the relevant bit asks not to trap the change */
11457 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
11458 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
11459 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
11460 vmcs12->guest_ia32_efer = vcpu->arch.efer;
11461 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
11462 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
11463 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
11464 if (kvm_mpx_supported())
11465 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
11466 }
11467
11468 /*
11469 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11470 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11471 * and this function updates it to reflect the changes to the guest state while
11472 * L2 was running (and perhaps made some exits which were handled directly by L0
11473 * without going back to L1), and to reflect the exit reason.
11474 * Note that we do not have to copy here all VMCS fields, just those that
11475 * could have changed by the L2 guest or the exit - i.e., the guest-state and
11476 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11477 * which already writes to vmcs12 directly.
11478 */
11479 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11480 u32 exit_reason, u32 exit_intr_info,
11481 unsigned long exit_qualification)
11482 {
11483 /* update guest state fields: */
11484 sync_vmcs12(vcpu, vmcs12);
11485
11486 /* update exit information fields: */
11487
11488 vmcs12->vm_exit_reason = exit_reason;
11489 vmcs12->exit_qualification = exit_qualification;
11490 vmcs12->vm_exit_intr_info = exit_intr_info;
11491
11492 vmcs12->idt_vectoring_info_field = 0;
11493 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
11494 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
11495
11496 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
11497 vmcs12->launch_state = 1;
11498
11499 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11500 * instead of reading the real value. */
11501 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
11502
11503 /*
11504 * Transfer the event that L0 or L1 may wanted to inject into
11505 * L2 to IDT_VECTORING_INFO_FIELD.
11506 */
11507 vmcs12_save_pending_event(vcpu, vmcs12);
11508 }
11509
11510 /*
11511 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11512 * preserved above and would only end up incorrectly in L1.
11513 */
11514 vcpu->arch.nmi_injected = false;
11515 kvm_clear_exception_queue(vcpu);
11516 kvm_clear_interrupt_queue(vcpu);
11517 }
11518
11519 static void load_vmcs12_mmu_host_state(struct kvm_vcpu *vcpu,
11520 struct vmcs12 *vmcs12)
11521 {
11522 u32 entry_failure_code;
11523
11524 nested_ept_uninit_mmu_context(vcpu);
11525
11526 /*
11527 * Only PDPTE load can fail as the value of cr3 was checked on entry and
11528 * couldn't have changed.
11529 */
11530 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
11531 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
11532
11533 if (!enable_ept)
11534 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
11535 }
11536
11537 /*
11538 * A part of what we need to when the nested L2 guest exits and we want to
11539 * run its L1 parent, is to reset L1's guest state to the host state specified
11540 * in vmcs12.
11541 * This function is to be called not only on normal nested exit, but also on
11542 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11543 * Failures During or After Loading Guest State").
11544 * This function should be called when the active VMCS is L1's (vmcs01).
11545 */
11546 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
11547 struct vmcs12 *vmcs12)
11548 {
11549 struct kvm_segment seg;
11550
11551 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
11552 vcpu->arch.efer = vmcs12->host_ia32_efer;
11553 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11554 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11555 else
11556 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11557 vmx_set_efer(vcpu, vcpu->arch.efer);
11558
11559 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
11560 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
11561 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
11562 /*
11563 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11564 * actually changed, because vmx_set_cr0 refers to efer set above.
11565 *
11566 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11567 * (KVM doesn't change it);
11568 */
11569 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
11570 vmx_set_cr0(vcpu, vmcs12->host_cr0);
11571
11572 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
11573 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
11574 vmx_set_cr4(vcpu, vmcs12->host_cr4);
11575
11576 load_vmcs12_mmu_host_state(vcpu, vmcs12);
11577
11578 if (enable_vpid) {
11579 /*
11580 * Trivially support vpid by letting L2s share their parent
11581 * L1's vpid. TODO: move to a more elaborate solution, giving
11582 * each L2 its own vpid and exposing the vpid feature to L1.
11583 */
11584 vmx_flush_tlb(vcpu, true);
11585 }
11586
11587 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
11588 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
11589 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
11590 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
11591 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
11592 vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
11593 vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
11594
11595 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11596 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
11597 vmcs_write64(GUEST_BNDCFGS, 0);
11598
11599 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
11600 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
11601 vcpu->arch.pat = vmcs12->host_ia32_pat;
11602 }
11603 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
11604 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
11605 vmcs12->host_ia32_perf_global_ctrl);
11606
11607 /* Set L1 segment info according to Intel SDM
11608 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11609 seg = (struct kvm_segment) {
11610 .base = 0,
11611 .limit = 0xFFFFFFFF,
11612 .selector = vmcs12->host_cs_selector,
11613 .type = 11,
11614 .present = 1,
11615 .s = 1,
11616 .g = 1
11617 };
11618 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11619 seg.l = 1;
11620 else
11621 seg.db = 1;
11622 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
11623 seg = (struct kvm_segment) {
11624 .base = 0,
11625 .limit = 0xFFFFFFFF,
11626 .type = 3,
11627 .present = 1,
11628 .s = 1,
11629 .db = 1,
11630 .g = 1
11631 };
11632 seg.selector = vmcs12->host_ds_selector;
11633 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
11634 seg.selector = vmcs12->host_es_selector;
11635 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
11636 seg.selector = vmcs12->host_ss_selector;
11637 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
11638 seg.selector = vmcs12->host_fs_selector;
11639 seg.base = vmcs12->host_fs_base;
11640 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
11641 seg.selector = vmcs12->host_gs_selector;
11642 seg.base = vmcs12->host_gs_base;
11643 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11644 seg = (struct kvm_segment) {
11645 .base = vmcs12->host_tr_base,
11646 .limit = 0x67,
11647 .selector = vmcs12->host_tr_selector,
11648 .type = 11,
11649 .present = 1
11650 };
11651 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11652
11653 kvm_set_dr(vcpu, 7, 0x400);
11654 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11655
11656 if (cpu_has_vmx_msr_bitmap())
11657 vmx_update_msr_bitmap(vcpu);
11658
11659 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11660 vmcs12->vm_exit_msr_load_count))
11661 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11662 }
11663
11664 /*
11665 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11666 * and modify vmcs12 to make it see what it would expect to see there if
11667 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11668 */
11669 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11670 u32 exit_intr_info,
11671 unsigned long exit_qualification)
11672 {
11673 struct vcpu_vmx *vmx = to_vmx(vcpu);
11674 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11675
11676 /* trying to cancel vmlaunch/vmresume is a bug */
11677 WARN_ON_ONCE(vmx->nested.nested_run_pending);
11678
11679 /*
11680 * The only expected VM-instruction error is "VM entry with
11681 * invalid control field(s)." Anything else indicates a
11682 * problem with L0.
11683 */
11684 WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
11685 VMXERR_ENTRY_INVALID_CONTROL_FIELD));
11686
11687 leave_guest_mode(vcpu);
11688
11689 if (likely(!vmx->fail)) {
11690 if (exit_reason == -1)
11691 sync_vmcs12(vcpu, vmcs12);
11692 else
11693 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11694 exit_qualification);
11695
11696 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11697 vmcs12->vm_exit_msr_store_count))
11698 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11699 }
11700
11701 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11702 vm_entry_controls_reset_shadow(vmx);
11703 vm_exit_controls_reset_shadow(vmx);
11704 vmx_segment_cache_clear(vmx);
11705
11706 /* Update any VMCS fields that might have changed while L2 ran */
11707 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11708 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11709 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11710 if (vmx->hv_deadline_tsc == -1)
11711 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11712 PIN_BASED_VMX_PREEMPTION_TIMER);
11713 else
11714 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11715 PIN_BASED_VMX_PREEMPTION_TIMER);
11716 if (kvm_has_tsc_control)
11717 decache_tsc_multiplier(vmx);
11718
11719 if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11720 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11721 vmx_set_virtual_x2apic_mode(vcpu,
11722 vcpu->arch.apic_base & X2APIC_ENABLE);
11723 } else if (!nested_cpu_has_ept(vmcs12) &&
11724 nested_cpu_has2(vmcs12,
11725 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11726 vmx_flush_tlb_ept_only(vcpu);
11727 }
11728
11729 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11730 vmx->host_rsp = 0;
11731
11732 /* Unpin physical memory we referred to in vmcs02 */
11733 if (vmx->nested.apic_access_page) {
11734 kvm_release_page_dirty(vmx->nested.apic_access_page);
11735 vmx->nested.apic_access_page = NULL;
11736 }
11737 if (vmx->nested.virtual_apic_page) {
11738 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
11739 vmx->nested.virtual_apic_page = NULL;
11740 }
11741 if (vmx->nested.pi_desc_page) {
11742 kunmap(vmx->nested.pi_desc_page);
11743 kvm_release_page_dirty(vmx->nested.pi_desc_page);
11744 vmx->nested.pi_desc_page = NULL;
11745 vmx->nested.pi_desc = NULL;
11746 }
11747
11748 /*
11749 * We are now running in L2, mmu_notifier will force to reload the
11750 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11751 */
11752 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11753
11754 if (enable_shadow_vmcs && exit_reason != -1)
11755 vmx->nested.sync_shadow_vmcs = true;
11756
11757 /* in case we halted in L2 */
11758 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11759
11760 if (likely(!vmx->fail)) {
11761 /*
11762 * TODO: SDM says that with acknowledge interrupt on
11763 * exit, bit 31 of the VM-exit interrupt information
11764 * (valid interrupt) is always set to 1 on
11765 * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
11766 * need kvm_cpu_has_interrupt(). See the commit
11767 * message for details.
11768 */
11769 if (nested_exit_intr_ack_set(vcpu) &&
11770 exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
11771 kvm_cpu_has_interrupt(vcpu)) {
11772 int irq = kvm_cpu_get_interrupt(vcpu);
11773 WARN_ON(irq < 0);
11774 vmcs12->vm_exit_intr_info = irq |
11775 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11776 }
11777
11778 if (exit_reason != -1)
11779 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11780 vmcs12->exit_qualification,
11781 vmcs12->idt_vectoring_info_field,
11782 vmcs12->vm_exit_intr_info,
11783 vmcs12->vm_exit_intr_error_code,
11784 KVM_ISA_VMX);
11785
11786 load_vmcs12_host_state(vcpu, vmcs12);
11787
11788 return;
11789 }
11790
11791 /*
11792 * After an early L2 VM-entry failure, we're now back
11793 * in L1 which thinks it just finished a VMLAUNCH or
11794 * VMRESUME instruction, so we need to set the failure
11795 * flag and the VM-instruction error field of the VMCS
11796 * accordingly.
11797 */
11798 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
11799
11800 load_vmcs12_mmu_host_state(vcpu, vmcs12);
11801
11802 /*
11803 * The emulated instruction was already skipped in
11804 * nested_vmx_run, but the updated RIP was never
11805 * written back to the vmcs01.
11806 */
11807 skip_emulated_instruction(vcpu);
11808 vmx->fail = 0;
11809 }
11810
11811 /*
11812 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11813 */
11814 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11815 {
11816 if (is_guest_mode(vcpu)) {
11817 to_vmx(vcpu)->nested.nested_run_pending = 0;
11818 nested_vmx_vmexit(vcpu, -1, 0, 0);
11819 }
11820 free_nested(to_vmx(vcpu));
11821 }
11822
11823 /*
11824 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11825 * 23.7 "VM-entry failures during or after loading guest state" (this also
11826 * lists the acceptable exit-reason and exit-qualification parameters).
11827 * It should only be called before L2 actually succeeded to run, and when
11828 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11829 */
11830 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11831 struct vmcs12 *vmcs12,
11832 u32 reason, unsigned long qualification)
11833 {
11834 load_vmcs12_host_state(vcpu, vmcs12);
11835 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11836 vmcs12->exit_qualification = qualification;
11837 nested_vmx_succeed(vcpu);
11838 if (enable_shadow_vmcs)
11839 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11840 }
11841
11842 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11843 struct x86_instruction_info *info,
11844 enum x86_intercept_stage stage)
11845 {
11846 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11847 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
11848
11849 /*
11850 * RDPID causes #UD if disabled through secondary execution controls.
11851 * Because it is marked as EmulateOnUD, we need to intercept it here.
11852 */
11853 if (info->intercept == x86_intercept_rdtscp &&
11854 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
11855 ctxt->exception.vector = UD_VECTOR;
11856 ctxt->exception.error_code_valid = false;
11857 return X86EMUL_PROPAGATE_FAULT;
11858 }
11859
11860 /* TODO: check more intercepts... */
11861 return X86EMUL_CONTINUE;
11862 }
11863
11864 #ifdef CONFIG_X86_64
11865 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11866 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11867 u64 divisor, u64 *result)
11868 {
11869 u64 low = a << shift, high = a >> (64 - shift);
11870
11871 /* To avoid the overflow on divq */
11872 if (high >= divisor)
11873 return 1;
11874
11875 /* Low hold the result, high hold rem which is discarded */
11876 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11877 "rm" (divisor), "0" (low), "1" (high));
11878 *result = low;
11879
11880 return 0;
11881 }
11882
11883 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11884 {
11885 struct vcpu_vmx *vmx = to_vmx(vcpu);
11886 u64 tscl = rdtsc();
11887 u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11888 u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11889
11890 /* Convert to host delta tsc if tsc scaling is enabled */
11891 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11892 u64_shl_div_u64(delta_tsc,
11893 kvm_tsc_scaling_ratio_frac_bits,
11894 vcpu->arch.tsc_scaling_ratio,
11895 &delta_tsc))
11896 return -ERANGE;
11897
11898 /*
11899 * If the delta tsc can't fit in the 32 bit after the multi shift,
11900 * we can't use the preemption timer.
11901 * It's possible that it fits on later vmentries, but checking
11902 * on every vmentry is costly so we just use an hrtimer.
11903 */
11904 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11905 return -ERANGE;
11906
11907 vmx->hv_deadline_tsc = tscl + delta_tsc;
11908 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11909 PIN_BASED_VMX_PREEMPTION_TIMER);
11910
11911 return delta_tsc == 0;
11912 }
11913
11914 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11915 {
11916 struct vcpu_vmx *vmx = to_vmx(vcpu);
11917 vmx->hv_deadline_tsc = -1;
11918 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11919 PIN_BASED_VMX_PREEMPTION_TIMER);
11920 }
11921 #endif
11922
11923 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11924 {
11925 if (ple_gap)
11926 shrink_ple_window(vcpu);
11927 }
11928
11929 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11930 struct kvm_memory_slot *slot)
11931 {
11932 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11933 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11934 }
11935
11936 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11937 struct kvm_memory_slot *slot)
11938 {
11939 kvm_mmu_slot_set_dirty(kvm, slot);
11940 }
11941
11942 static void vmx_flush_log_dirty(struct kvm *kvm)
11943 {
11944 kvm_flush_pml_buffers(kvm);
11945 }
11946
11947 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11948 {
11949 struct vmcs12 *vmcs12;
11950 struct vcpu_vmx *vmx = to_vmx(vcpu);
11951 gpa_t gpa;
11952 struct page *page = NULL;
11953 u64 *pml_address;
11954
11955 if (is_guest_mode(vcpu)) {
11956 WARN_ON_ONCE(vmx->nested.pml_full);
11957
11958 /*
11959 * Check if PML is enabled for the nested guest.
11960 * Whether eptp bit 6 is set is already checked
11961 * as part of A/D emulation.
11962 */
11963 vmcs12 = get_vmcs12(vcpu);
11964 if (!nested_cpu_has_pml(vmcs12))
11965 return 0;
11966
11967 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
11968 vmx->nested.pml_full = true;
11969 return 1;
11970 }
11971
11972 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11973
11974 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
11975 if (is_error_page(page))
11976 return 0;
11977
11978 pml_address = kmap(page);
11979 pml_address[vmcs12->guest_pml_index--] = gpa;
11980 kunmap(page);
11981 kvm_release_page_clean(page);
11982 }
11983
11984 return 0;
11985 }
11986
11987 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11988 struct kvm_memory_slot *memslot,
11989 gfn_t offset, unsigned long mask)
11990 {
11991 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11992 }
11993
11994 static void __pi_post_block(struct kvm_vcpu *vcpu)
11995 {
11996 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11997 struct pi_desc old, new;
11998 unsigned int dest;
11999
12000 do {
12001 old.control = new.control = pi_desc->control;
12002 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
12003 "Wakeup handler not enabled while the VCPU is blocked\n");
12004
12005 dest = cpu_physical_id(vcpu->cpu);
12006
12007 if (x2apic_enabled())
12008 new.ndst = dest;
12009 else
12010 new.ndst = (dest << 8) & 0xFF00;
12011
12012 /* set 'NV' to 'notification vector' */
12013 new.nv = POSTED_INTR_VECTOR;
12014 } while (cmpxchg64(&pi_desc->control, old.control,
12015 new.control) != old.control);
12016
12017 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
12018 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12019 list_del(&vcpu->blocked_vcpu_list);
12020 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12021 vcpu->pre_pcpu = -1;
12022 }
12023 }
12024
12025 /*
12026 * This routine does the following things for vCPU which is going
12027 * to be blocked if VT-d PI is enabled.
12028 * - Store the vCPU to the wakeup list, so when interrupts happen
12029 * we can find the right vCPU to wake up.
12030 * - Change the Posted-interrupt descriptor as below:
12031 * 'NDST' <-- vcpu->pre_pcpu
12032 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
12033 * - If 'ON' is set during this process, which means at least one
12034 * interrupt is posted for this vCPU, we cannot block it, in
12035 * this case, return 1, otherwise, return 0.
12036 *
12037 */
12038 static int pi_pre_block(struct kvm_vcpu *vcpu)
12039 {
12040 unsigned int dest;
12041 struct pi_desc old, new;
12042 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
12043
12044 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
12045 !irq_remapping_cap(IRQ_POSTING_CAP) ||
12046 !kvm_vcpu_apicv_active(vcpu))
12047 return 0;
12048
12049 WARN_ON(irqs_disabled());
12050 local_irq_disable();
12051 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
12052 vcpu->pre_pcpu = vcpu->cpu;
12053 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12054 list_add_tail(&vcpu->blocked_vcpu_list,
12055 &per_cpu(blocked_vcpu_on_cpu,
12056 vcpu->pre_pcpu));
12057 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12058 }
12059
12060 do {
12061 old.control = new.control = pi_desc->control;
12062
12063 WARN((pi_desc->sn == 1),
12064 "Warning: SN field of posted-interrupts "
12065 "is set before blocking\n");
12066
12067 /*
12068 * Since vCPU can be preempted during this process,
12069 * vcpu->cpu could be different with pre_pcpu, we
12070 * need to set pre_pcpu as the destination of wakeup
12071 * notification event, then we can find the right vCPU
12072 * to wakeup in wakeup handler if interrupts happen
12073 * when the vCPU is in blocked state.
12074 */
12075 dest = cpu_physical_id(vcpu->pre_pcpu);
12076
12077 if (x2apic_enabled())
12078 new.ndst = dest;
12079 else
12080 new.ndst = (dest << 8) & 0xFF00;
12081
12082 /* set 'NV' to 'wakeup vector' */
12083 new.nv = POSTED_INTR_WAKEUP_VECTOR;
12084 } while (cmpxchg64(&pi_desc->control, old.control,
12085 new.control) != old.control);
12086
12087 /* We should not block the vCPU if an interrupt is posted for it. */
12088 if (pi_test_on(pi_desc) == 1)
12089 __pi_post_block(vcpu);
12090
12091 local_irq_enable();
12092 return (vcpu->pre_pcpu == -1);
12093 }
12094
12095 static int vmx_pre_block(struct kvm_vcpu *vcpu)
12096 {
12097 if (pi_pre_block(vcpu))
12098 return 1;
12099
12100 if (kvm_lapic_hv_timer_in_use(vcpu))
12101 kvm_lapic_switch_to_sw_timer(vcpu);
12102
12103 return 0;
12104 }
12105
12106 static void pi_post_block(struct kvm_vcpu *vcpu)
12107 {
12108 if (vcpu->pre_pcpu == -1)
12109 return;
12110
12111 WARN_ON(irqs_disabled());
12112 local_irq_disable();
12113 __pi_post_block(vcpu);
12114 local_irq_enable();
12115 }
12116
12117 static void vmx_post_block(struct kvm_vcpu *vcpu)
12118 {
12119 if (kvm_x86_ops->set_hv_timer)
12120 kvm_lapic_switch_to_hv_timer(vcpu);
12121
12122 pi_post_block(vcpu);
12123 }
12124
12125 /*
12126 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
12127 *
12128 * @kvm: kvm
12129 * @host_irq: host irq of the interrupt
12130 * @guest_irq: gsi of the interrupt
12131 * @set: set or unset PI
12132 * returns 0 on success, < 0 on failure
12133 */
12134 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
12135 uint32_t guest_irq, bool set)
12136 {
12137 struct kvm_kernel_irq_routing_entry *e;
12138 struct kvm_irq_routing_table *irq_rt;
12139 struct kvm_lapic_irq irq;
12140 struct kvm_vcpu *vcpu;
12141 struct vcpu_data vcpu_info;
12142 int idx, ret = 0;
12143
12144 if (!kvm_arch_has_assigned_device(kvm) ||
12145 !irq_remapping_cap(IRQ_POSTING_CAP) ||
12146 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
12147 return 0;
12148
12149 idx = srcu_read_lock(&kvm->irq_srcu);
12150 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
12151 if (guest_irq >= irq_rt->nr_rt_entries ||
12152 hlist_empty(&irq_rt->map[guest_irq])) {
12153 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
12154 guest_irq, irq_rt->nr_rt_entries);
12155 goto out;
12156 }
12157
12158 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
12159 if (e->type != KVM_IRQ_ROUTING_MSI)
12160 continue;
12161 /*
12162 * VT-d PI cannot support posting multicast/broadcast
12163 * interrupts to a vCPU, we still use interrupt remapping
12164 * for these kind of interrupts.
12165 *
12166 * For lowest-priority interrupts, we only support
12167 * those with single CPU as the destination, e.g. user
12168 * configures the interrupts via /proc/irq or uses
12169 * irqbalance to make the interrupts single-CPU.
12170 *
12171 * We will support full lowest-priority interrupt later.
12172 */
12173
12174 kvm_set_msi_irq(kvm, e, &irq);
12175 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
12176 /*
12177 * Make sure the IRTE is in remapped mode if
12178 * we don't handle it in posted mode.
12179 */
12180 ret = irq_set_vcpu_affinity(host_irq, NULL);
12181 if (ret < 0) {
12182 printk(KERN_INFO
12183 "failed to back to remapped mode, irq: %u\n",
12184 host_irq);
12185 goto out;
12186 }
12187
12188 continue;
12189 }
12190
12191 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
12192 vcpu_info.vector = irq.vector;
12193
12194 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
12195 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
12196
12197 if (set)
12198 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
12199 else
12200 ret = irq_set_vcpu_affinity(host_irq, NULL);
12201
12202 if (ret < 0) {
12203 printk(KERN_INFO "%s: failed to update PI IRTE\n",
12204 __func__);
12205 goto out;
12206 }
12207 }
12208
12209 ret = 0;
12210 out:
12211 srcu_read_unlock(&kvm->irq_srcu, idx);
12212 return ret;
12213 }
12214
12215 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
12216 {
12217 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
12218 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
12219 FEATURE_CONTROL_LMCE;
12220 else
12221 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
12222 ~FEATURE_CONTROL_LMCE;
12223 }
12224
12225 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
12226 {
12227 /* we need a nested vmexit to enter SMM, postpone if run is pending */
12228 if (to_vmx(vcpu)->nested.nested_run_pending)
12229 return 0;
12230 return 1;
12231 }
12232
12233 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
12234 {
12235 struct vcpu_vmx *vmx = to_vmx(vcpu);
12236
12237 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
12238 if (vmx->nested.smm.guest_mode)
12239 nested_vmx_vmexit(vcpu, -1, 0, 0);
12240
12241 vmx->nested.smm.vmxon = vmx->nested.vmxon;
12242 vmx->nested.vmxon = false;
12243 return 0;
12244 }
12245
12246 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
12247 {
12248 struct vcpu_vmx *vmx = to_vmx(vcpu);
12249 int ret;
12250
12251 if (vmx->nested.smm.vmxon) {
12252 vmx->nested.vmxon = true;
12253 vmx->nested.smm.vmxon = false;
12254 }
12255
12256 if (vmx->nested.smm.guest_mode) {
12257 vcpu->arch.hflags &= ~HF_SMM_MASK;
12258 ret = enter_vmx_non_root_mode(vcpu, false);
12259 vcpu->arch.hflags |= HF_SMM_MASK;
12260 if (ret)
12261 return ret;
12262
12263 vmx->nested.smm.guest_mode = false;
12264 }
12265 return 0;
12266 }
12267
12268 static int enable_smi_window(struct kvm_vcpu *vcpu)
12269 {
12270 return 0;
12271 }
12272
12273 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
12274 .cpu_has_kvm_support = cpu_has_kvm_support,
12275 .disabled_by_bios = vmx_disabled_by_bios,
12276 .hardware_setup = hardware_setup,
12277 .hardware_unsetup = hardware_unsetup,
12278 .check_processor_compatibility = vmx_check_processor_compat,
12279 .hardware_enable = hardware_enable,
12280 .hardware_disable = hardware_disable,
12281 .cpu_has_accelerated_tpr = report_flexpriority,
12282 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
12283
12284 .vcpu_create = vmx_create_vcpu,
12285 .vcpu_free = vmx_free_vcpu,
12286 .vcpu_reset = vmx_vcpu_reset,
12287
12288 .prepare_guest_switch = vmx_save_host_state,
12289 .vcpu_load = vmx_vcpu_load,
12290 .vcpu_put = vmx_vcpu_put,
12291
12292 .update_bp_intercept = update_exception_bitmap,
12293 .get_msr = vmx_get_msr,
12294 .set_msr = vmx_set_msr,
12295 .get_segment_base = vmx_get_segment_base,
12296 .get_segment = vmx_get_segment,
12297 .set_segment = vmx_set_segment,
12298 .get_cpl = vmx_get_cpl,
12299 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
12300 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
12301 .decache_cr3 = vmx_decache_cr3,
12302 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
12303 .set_cr0 = vmx_set_cr0,
12304 .set_cr3 = vmx_set_cr3,
12305 .set_cr4 = vmx_set_cr4,
12306 .set_efer = vmx_set_efer,
12307 .get_idt = vmx_get_idt,
12308 .set_idt = vmx_set_idt,
12309 .get_gdt = vmx_get_gdt,
12310 .set_gdt = vmx_set_gdt,
12311 .get_dr6 = vmx_get_dr6,
12312 .set_dr6 = vmx_set_dr6,
12313 .set_dr7 = vmx_set_dr7,
12314 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
12315 .cache_reg = vmx_cache_reg,
12316 .get_rflags = vmx_get_rflags,
12317 .set_rflags = vmx_set_rflags,
12318
12319 .tlb_flush = vmx_flush_tlb,
12320
12321 .run = vmx_vcpu_run,
12322 .handle_exit = vmx_handle_exit,
12323 .skip_emulated_instruction = skip_emulated_instruction,
12324 .set_interrupt_shadow = vmx_set_interrupt_shadow,
12325 .get_interrupt_shadow = vmx_get_interrupt_shadow,
12326 .patch_hypercall = vmx_patch_hypercall,
12327 .set_irq = vmx_inject_irq,
12328 .set_nmi = vmx_inject_nmi,
12329 .queue_exception = vmx_queue_exception,
12330 .cancel_injection = vmx_cancel_injection,
12331 .interrupt_allowed = vmx_interrupt_allowed,
12332 .nmi_allowed = vmx_nmi_allowed,
12333 .get_nmi_mask = vmx_get_nmi_mask,
12334 .set_nmi_mask = vmx_set_nmi_mask,
12335 .enable_nmi_window = enable_nmi_window,
12336 .enable_irq_window = enable_irq_window,
12337 .update_cr8_intercept = update_cr8_intercept,
12338 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
12339 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
12340 .get_enable_apicv = vmx_get_enable_apicv,
12341 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
12342 .load_eoi_exitmap = vmx_load_eoi_exitmap,
12343 .apicv_post_state_restore = vmx_apicv_post_state_restore,
12344 .hwapic_irr_update = vmx_hwapic_irr_update,
12345 .hwapic_isr_update = vmx_hwapic_isr_update,
12346 .sync_pir_to_irr = vmx_sync_pir_to_irr,
12347 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
12348
12349 .set_tss_addr = vmx_set_tss_addr,
12350 .get_tdp_level = get_ept_level,
12351 .get_mt_mask = vmx_get_mt_mask,
12352
12353 .get_exit_info = vmx_get_exit_info,
12354
12355 .get_lpage_level = vmx_get_lpage_level,
12356
12357 .cpuid_update = vmx_cpuid_update,
12358
12359 .rdtscp_supported = vmx_rdtscp_supported,
12360 .invpcid_supported = vmx_invpcid_supported,
12361
12362 .set_supported_cpuid = vmx_set_supported_cpuid,
12363
12364 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
12365
12366 .write_tsc_offset = vmx_write_tsc_offset,
12367
12368 .set_tdp_cr3 = vmx_set_cr3,
12369
12370 .check_intercept = vmx_check_intercept,
12371 .handle_external_intr = vmx_handle_external_intr,
12372 .mpx_supported = vmx_mpx_supported,
12373 .xsaves_supported = vmx_xsaves_supported,
12374 .umip_emulated = vmx_umip_emulated,
12375
12376 .check_nested_events = vmx_check_nested_events,
12377
12378 .sched_in = vmx_sched_in,
12379
12380 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
12381 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
12382 .flush_log_dirty = vmx_flush_log_dirty,
12383 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
12384 .write_log_dirty = vmx_write_pml_buffer,
12385
12386 .pre_block = vmx_pre_block,
12387 .post_block = vmx_post_block,
12388
12389 .pmu_ops = &intel_pmu_ops,
12390
12391 .update_pi_irte = vmx_update_pi_irte,
12392
12393 #ifdef CONFIG_X86_64
12394 .set_hv_timer = vmx_set_hv_timer,
12395 .cancel_hv_timer = vmx_cancel_hv_timer,
12396 #endif
12397
12398 .setup_mce = vmx_setup_mce,
12399
12400 .smi_allowed = vmx_smi_allowed,
12401 .pre_enter_smm = vmx_pre_enter_smm,
12402 .pre_leave_smm = vmx_pre_leave_smm,
12403 .enable_smi_window = enable_smi_window,
12404 };
12405
12406 static int __init vmx_init(void)
12407 {
12408 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
12409 __alignof__(struct vcpu_vmx), THIS_MODULE);
12410 if (r)
12411 return r;
12412
12413 #ifdef CONFIG_KEXEC_CORE
12414 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
12415 crash_vmclear_local_loaded_vmcss);
12416 #endif
12417
12418 return 0;
12419 }
12420
12421 static void __exit vmx_exit(void)
12422 {
12423 #ifdef CONFIG_KEXEC_CORE
12424 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
12425 synchronize_rcu();
12426 #endif
12427
12428 kvm_exit();
12429 }
12430
12431 module_init(vmx_init)
12432 module_exit(vmx_exit)
CRIS linux kernel tree