arch/tile/include/hv/drv_mpipe_intf.h

   1 /*
   2  * Copyright 2011 Tilera Corporation. All Rights Reserved.
   3  *
   4  *   This program is free software; you can redistribute it and/or
   5  *   modify it under the terms of the GNU General Public License
   6  *   as published by the Free Software Foundation, version 2.
   7  *
   8  *   This program is distributed in the hope that it will be useful, but
   9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  11  *   NON INFRINGEMENT.  See the GNU General Public License for
  12  *   more details.
  13  */
  14
  15 /**
  16  * Interface definitions for the mpipe driver.
  17  */
  18
  19 #ifndef _SYS_HV_DRV_MPIPE_INTF_H
  20 #define _SYS_HV_DRV_MPIPE_INTF_H
  21
  22 #include <arch/mpipe.h>
  23 #include <arch/mpipe_constants.h>
  24
  25
  26 /** Number of buffer stacks (32). */
  27 #define HV_MPIPE_NUM_BUFFER_STACKS \
  28   (MPIPE_MMIO_INIT_DAT_GX36_1__BUFFER_STACK_MASK_WIDTH)
  29
  30 /** Number of NotifRings (256). */
  31 #define HV_MPIPE_NUM_NOTIF_RINGS (MPIPE_NUM_NOTIF_RINGS)
  32
  33 /** Number of NotifGroups (32). */
  34 #define HV_MPIPE_NUM_NOTIF_GROUPS (MPIPE_NUM_NOTIF_GROUPS)
  35
  36 /** Number of buckets (4160). */
  37 #define HV_MPIPE_NUM_BUCKETS (MPIPE_NUM_BUCKETS)
  38
  39 /** Number of "lo" buckets (4096). */
  40 #define HV_MPIPE_NUM_LO_BUCKETS 4096
  41
  42 /** Number of "hi" buckets (64). */
  43 #define HV_MPIPE_NUM_HI_BUCKETS \
  44   (HV_MPIPE_NUM_BUCKETS - HV_MPIPE_NUM_LO_BUCKETS)
  45
  46 /** Number of edma rings (24). */
  47 #define HV_MPIPE_NUM_EDMA_RINGS \
  48   (MPIPE_MMIO_INIT_DAT_GX36_1__EDMA_POST_MASK_WIDTH)
  49
  50
  51
  52
  53 /** A flag bit indicating a fixed resource allocation. */
  54 #define HV_MPIPE_ALLOC_FIXED 0x01
  55
  56 /** Offset for the config register MMIO region. */
  57 #define HV_MPIPE_CONFIG_MMIO_OFFSET \
  58   (MPIPE_MMIO_ADDR__REGION_VAL_CFG << MPIPE_MMIO_ADDR__REGION_SHIFT)
  59
  60 /** Size of the config register MMIO region. */
  61 #define HV_MPIPE_CONFIG_MMIO_SIZE (64 * 1024)
  62
  63 /** Offset for the config register MMIO region. */
  64 #define HV_MPIPE_FAST_MMIO_OFFSET \
  65   (MPIPE_MMIO_ADDR__REGION_VAL_IDMA << MPIPE_MMIO_ADDR__REGION_SHIFT)
  66
  67 /** Size of the fast register MMIO region (IDMA, EDMA, buffer stack). */
  68 #define HV_MPIPE_FAST_MMIO_SIZE \
  69   ((MPIPE_MMIO_ADDR__REGION_VAL_BSM + 1 - MPIPE_MMIO_ADDR__REGION_VAL_IDMA) \
  70    << MPIPE_MMIO_ADDR__REGION_SHIFT)
  71
  72
  73 /*
  74  * Each type of resource allocation comes in quantized chunks, where
  75  * XXX_BITS is the number of chunks, and XXX_RES_PER_BIT is the number
  76  * of resources in each chunk.
  77  */
  78
  79 /** Number of buffer stack chunks available (32). */
  80 #define HV_MPIPE_ALLOC_BUFFER_STACKS_BITS \
  81   MPIPE_MMIO_INIT_DAT_GX36_1__BUFFER_STACK_MASK_WIDTH
  82
  83 /** Granularity of buffer stack allocation (1). */
  84 #define HV_MPIPE_ALLOC_BUFFER_STACKS_RES_PER_BIT \
  85   (HV_MPIPE_NUM_BUFFER_STACKS / HV_MPIPE_ALLOC_BUFFER_STACKS_BITS)
  86
  87 /** Number of NotifRing chunks available (32). */
  88 #define HV_MPIPE_ALLOC_NOTIF_RINGS_BITS \
  89   MPIPE_MMIO_INIT_DAT_GX36_0__NOTIF_RING_MASK_WIDTH
  90
  91 /** Granularity of NotifRing allocation (8). */
  92 #define HV_MPIPE_ALLOC_NOTIF_RINGS_RES_PER_BIT \
  93   (HV_MPIPE_NUM_NOTIF_RINGS / HV_MPIPE_ALLOC_NOTIF_RINGS_BITS)
  94
  95 /** Number of NotifGroup chunks available (32). */
  96 #define HV_MPIPE_ALLOC_NOTIF_GROUPS_BITS \
  97   HV_MPIPE_NUM_NOTIF_GROUPS
  98
  99 /** Granularity of NotifGroup allocation (1). */
 100 #define HV_MPIPE_ALLOC_NOTIF_GROUPS_RES_PER_BIT \
 101   (HV_MPIPE_NUM_NOTIF_GROUPS / HV_MPIPE_ALLOC_NOTIF_GROUPS_BITS)
 102
 103 /** Number of lo bucket chunks available (16). */
 104 #define HV_MPIPE_ALLOC_LO_BUCKETS_BITS \
 105   MPIPE_MMIO_INIT_DAT_GX36_0__BUCKET_RELEASE_MASK_LO_WIDTH
 106
 107 /** Granularity of lo bucket allocation (256). */
 108 #define HV_MPIPE_ALLOC_LO_BUCKETS_RES_PER_BIT \
 109   (HV_MPIPE_NUM_LO_BUCKETS / HV_MPIPE_ALLOC_LO_BUCKETS_BITS)
 110
 111 /** Number of hi bucket chunks available (16). */
 112 #define HV_MPIPE_ALLOC_HI_BUCKETS_BITS \
 113   MPIPE_MMIO_INIT_DAT_GX36_0__BUCKET_RELEASE_MASK_HI_WIDTH
 114
 115 /** Granularity of hi bucket allocation (4). */
 116 #define HV_MPIPE_ALLOC_HI_BUCKETS_RES_PER_BIT \
 117   (HV_MPIPE_NUM_HI_BUCKETS / HV_MPIPE_ALLOC_HI_BUCKETS_BITS)
 118
 119 /** Number of eDMA ring chunks available (24). */
 120 #define HV_MPIPE_ALLOC_EDMA_RINGS_BITS \
 121   MPIPE_MMIO_INIT_DAT_GX36_1__EDMA_POST_MASK_WIDTH
 122
 123 /** Granularity of eDMA ring allocation (1). */
 124 #define HV_MPIPE_ALLOC_EDMA_RINGS_RES_PER_BIT \
 125   (HV_MPIPE_NUM_EDMA_RINGS / HV_MPIPE_ALLOC_EDMA_RINGS_BITS)
 126
 127
 128
 129
 130 /** Bit vector encoding which NotifRings are in a NotifGroup. */
 131 typedef struct
 132 {
 133   /** The actual bits. */
 134   uint64_t ring_mask[4];
 135
 136 } gxio_mpipe_notif_group_bits_t;
 137
 138
 139 /** Another name for MPIPE_LBL_INIT_DAT_BSTS_TBL_t. */
 140 typedef MPIPE_LBL_INIT_DAT_BSTS_TBL_t gxio_mpipe_bucket_info_t;
 141
 142
 143
 144 /** Eight buffer stack ids. */
 145 typedef struct
 146 {
 147   /** The stacks. */
 148   uint8_t stacks[8];
 149
 150 } gxio_mpipe_rules_stacks_t;
 151
 152
 153 /** A destination mac address. */
 154 typedef struct
 155 {
 156   /** The octets. */
 157   uint8_t octets[6];
 158
 159 } gxio_mpipe_rules_dmac_t;
 160
 161
 162 /** A vlan. */
 163 typedef uint16_t gxio_mpipe_rules_vlan_t;
 164
 165
 166
 167 /** Maximum number of characters in a link name. */
 168 #define GXIO_MPIPE_LINK_NAME_LEN  32
 169
 170
 171 /** Structure holding a link name.  Only needed, and only typedef'ed,
 172  *  because the IORPC stub generator only handles types which are single
 173  *  words coming before the parameter name. */
 174 typedef struct
 175 {
 176   /** The name itself. */
 177   char name[GXIO_MPIPE_LINK_NAME_LEN];
 178 }
 179 _gxio_mpipe_link_name_t;
 180
 181 /** Maximum number of characters in a symbol name. */
 182 #define GXIO_MPIPE_SYMBOL_NAME_LEN  128
 183
 184
 185 /** Structure holding a symbol name.  Only needed, and only typedef'ed,
 186  *  because the IORPC stub generator only handles types which are single
 187  *  words coming before the parameter name. */
 188 typedef struct
 189 {
 190   /** The name itself. */
 191   char name[GXIO_MPIPE_SYMBOL_NAME_LEN];
 192 }
 193 _gxio_mpipe_symbol_name_t;
 194
 195
 196 /** Structure holding a MAC address. */
 197 typedef struct
 198 {
 199   /** The address. */
 200   uint8_t mac[6];
 201 }
 202 _gxio_mpipe_link_mac_t;
 203
 204
 205
 206 /** Request shared data permission -- that is, the ability to send and
 207  *  receive packets -- on the specified link.  Other processes may also
 208  *  request shared data permission on the same link.
 209  *
 210  *  No more than one of ::GXIO_MPIPE_LINK_DATA, ::GXIO_MPIPE_LINK_NO_DATA,
 211  *  or ::GXIO_MPIPE_LINK_EXCL_DATA may be specifed in a gxio_mpipe_link_open()
 212  *  call.  If none are specified, ::GXIO_MPIPE_LINK_DATA is assumed.
 213  */
 214 #define GXIO_MPIPE_LINK_DATA               0x00000001UL
 215
 216 /** Do not request data permission on the specified link.
 217  *
 218  *  No more than one of ::GXIO_MPIPE_LINK_DATA, ::GXIO_MPIPE_LINK_NO_DATA,
 219  *  or ::GXIO_MPIPE_LINK_EXCL_DATA may be specifed in a gxio_mpipe_link_open()
 220  *  call.  If none are specified, ::GXIO_MPIPE_LINK_DATA is assumed.
 221  */
 222 #define GXIO_MPIPE_LINK_NO_DATA            0x00000002UL
 223
 224 /** Request exclusive data permission -- that is, the ability to send and
 225  *  receive packets -- on the specified link.  No other processes may
 226  *  request data permission on this link, and if any process already has
 227  *  data permission on it, this open will fail.
 228  *
 229  *  No more than one of ::GXIO_MPIPE_LINK_DATA, ::GXIO_MPIPE_LINK_NO_DATA,
 230  *  or ::GXIO_MPIPE_LINK_EXCL_DATA may be specifed in a gxio_mpipe_link_open()
 231  *  call.  If none are specified, ::GXIO_MPIPE_LINK_DATA is assumed.
 232  */
 233 #define GXIO_MPIPE_LINK_EXCL_DATA          0x00000004UL
 234
 235 /** Request shared stats permission -- that is, the ability to read and write
 236  *  registers which contain link statistics, and to get link attributes --
 237  *  on the specified link.  Other processes may also request shared stats
 238  *  permission on the same link.
 239  *
 240  *  No more than one of ::GXIO_MPIPE_LINK_STATS, ::GXIO_MPIPE_LINK_NO_STATS,
 241  *  or ::GXIO_MPIPE_LINK_EXCL_STATS may be specifed in a gxio_mpipe_link_open()
 242  *  call.  If none are specified, ::GXIO_MPIPE_LINK_STATS is assumed.
 243  */
 244 #define GXIO_MPIPE_LINK_STATS              0x00000008UL
 245
 246 /** Do not request stats permission on the specified link.
 247  *
 248  *  No more than one of ::GXIO_MPIPE_LINK_STATS, ::GXIO_MPIPE_LINK_NO_STATS,
 249  *  or ::GXIO_MPIPE_LINK_EXCL_STATS may be specifed in a gxio_mpipe_link_open()
 250  *  call.  If none are specified, ::GXIO_MPIPE_LINK_STATS is assumed.
 251  */
 252 #define GXIO_MPIPE_LINK_NO_STATS           0x00000010UL
 253
 254 /** Request exclusive stats permission -- that is, the ability to read and
 255  *  write registers which contain link statistics, and to get link
 256  *  attributes -- on the specified link.  No other processes may request
 257  *  stats permission on this link, and if any process already
 258  *  has stats permission on it, this open will fail.
 259  *
 260  *  Requesting exclusive stats permission is normally a very bad idea, since
 261  *  it prevents programs like mpipe-stat from providing information on this
 262  *  link.  Applications should only do this if they use MAC statistics
 263  *  registers, and cannot tolerate any of the clear-on-read registers being
 264  *  reset by other statistics programs.
 265  *
 266  *  No more than one of ::GXIO_MPIPE_LINK_STATS, ::GXIO_MPIPE_LINK_NO_STATS,
 267  *  or ::GXIO_MPIPE_LINK_EXCL_STATS may be specifed in a gxio_mpipe_link_open()
 268  *  call.  If none are specified, ::GXIO_MPIPE_LINK_STATS is assumed.
 269  */
 270 #define GXIO_MPIPE_LINK_EXCL_STATS         0x00000020UL
 271
 272 /** Request shared control permission -- that is, the ability to modify link
 273  *  attributes, and read and write MAC and MDIO registers -- on the
 274  *  specified link.  Other processes may also request shared control
 275  *  permission on the same link.
 276  *
 277  *  No more than one of ::GXIO_MPIPE_LINK_CTL, ::GXIO_MPIPE_LINK_NO_CTL,
 278  *  or ::GXIO_MPIPE_LINK_EXCL_CTL may be specifed in a gxio_mpipe_link_open()
 279  *  call.  If none are specified, ::GXIO_MPIPE_LINK_CTL is assumed.
 280  */
 281 #define GXIO_MPIPE_LINK_CTL                0x00000040UL
 282
 283 /** Do not request control permission on the specified link.
 284  *
 285  *  No more than one of ::GXIO_MPIPE_LINK_CTL, ::GXIO_MPIPE_LINK_NO_CTL,
 286  *  or ::GXIO_MPIPE_LINK_EXCL_CTL may be specifed in a gxio_mpipe_link_open()
 287  *  call.  If none are specified, ::GXIO_MPIPE_LINK_CTL is assumed.
 288  */
 289 #define GXIO_MPIPE_LINK_NO_CTL             0x00000080UL
 290
 291 /** Request exclusive control permission -- that is, the ability to modify
 292  *  link attributes, and read and write MAC and MDIO registers -- on the
 293  *  specified link.  No other processes may request control permission on
 294  *  this link, and if any process already has control permission on it,
 295  *  this open will fail.
 296  *
 297  *  Requesting exclusive control permission is not always a good idea, since
 298  *  it prevents programs like mpipe-link from configuring the link.
 299  *
 300  *  No more than one of ::GXIO_MPIPE_LINK_CTL, ::GXIO_MPIPE_LINK_NO_CTL,
 301  *  or ::GXIO_MPIPE_LINK_EXCL_CTL may be specifed in a gxio_mpipe_link_open()
 302  *  call.  If none are specified, ::GXIO_MPIPE_LINK_CTL is assumed.
 303  */
 304 #define GXIO_MPIPE_LINK_EXCL_CTL           0x00000100UL
 305
 306 /** Set the desired state of the link to up, allowing any speeds which are
 307  *  supported by the link hardware, as part of this open operation; do not
 308  *  change the desired state of the link when it is closed or the process
 309  *  exits.  No more than one of ::GXIO_MPIPE_LINK_AUTO_UP,
 310  *  ::GXIO_MPIPE_LINK_AUTO_UPDOWN, ::GXIO_MPIPE_LINK_AUTO_DOWN, or
 311  *  ::GXIO_MPIPE_LINK_AUTO_NONE may be specifed in a gxio_mpipe_link_open()
 312  *  call.  If none are specified, ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed.
 313  */
 314 #define GXIO_MPIPE_LINK_AUTO_UP            0x00000200UL
 315
 316 /** Set the desired state of the link to up, allowing any speeds which are
 317  *  supported by the link hardware, as part of this open operation; when the
 318  *  link is closed or this process exits, if no other process has the link
 319  *  open, set the desired state of the link to down.  No more than one of
 320  *  ::GXIO_MPIPE_LINK_AUTO_UP, ::GXIO_MPIPE_LINK_AUTO_UPDOWN,
 321  *  ::GXIO_MPIPE_LINK_AUTO_DOWN, or ::GXIO_MPIPE_LINK_AUTO_NONE may be
 322  *  specifed in a gxio_mpipe_link_open() call.  If none are specified,
 323  *  ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed.
 324  */
 325 #define GXIO_MPIPE_LINK_AUTO_UPDOWN        0x00000400UL
 326
 327 /** Do not change the desired state of the link as part of the open
 328  *  operation; when the link is closed or this process exits, if no other
 329  *  process has the link open, set the desired state of the link to down.
 330  *  No more than one of ::GXIO_MPIPE_LINK_AUTO_UP,
 331  *  ::GXIO_MPIPE_LINK_AUTO_UPDOWN, ::GXIO_MPIPE_LINK_AUTO_DOWN, or
 332  *  ::GXIO_MPIPE_LINK_AUTO_NONE may be specifed in a gxio_mpipe_link_open()
 333  *  call.  If none are specified, ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed.
 334  */
 335 #define GXIO_MPIPE_LINK_AUTO_DOWN          0x00000800UL
 336
 337 /** Do not change the desired state of the link as part of the open
 338  *  operation; do not change the desired state of the link when it is
 339  *  closed or the process exits.  No more than one of
 340  *  ::GXIO_MPIPE_LINK_AUTO_UP, ::GXIO_MPIPE_LINK_AUTO_UPDOWN,
 341  *  ::GXIO_MPIPE_LINK_AUTO_DOWN, or ::GXIO_MPIPE_LINK_AUTO_NONE may be
 342  *  specifed in a gxio_mpipe_link_open() call.  If none are specified,
 343  *  ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed.
 344  */
 345 #define GXIO_MPIPE_LINK_AUTO_NONE          0x00001000UL
 346
 347 /** Request that this open call not complete until the network link is up.
 348  *  The process will wait as long as necessary for this to happen;
 349  *  applications which wish to abandon waiting for the link after a
 350  *  specific time period should not specify this flag when opening a link,
 351  *  but should instead call gxio_mpipe_link_wait() afterward.  The link
 352  *  must be opened with stats permission.  Note that this flag by itself
 353  *  does not change the desired link state; if other open flags or previous
 354  *  link state changes have not requested a desired state of up, the open
 355  *  call will never complete.  This flag is not available to kernel
 356  *  clients.
 357  */
 358 #define GXIO_MPIPE_LINK_WAIT               0x00002000UL
 359
 360
 361 /*
 362  * Note: link attributes must fit in 24 bits, since we use the top 8 bits
 363  * of the IORPC offset word for the channel number.
 364  */
 365
 366 /** Determine whether jumbo frames may be received.  If this attribute's
 367  *  value value is nonzero, the MAC will accept frames of up to 10240 bytes.
 368  *  If the value is zero, the MAC will only accept frames of up to 1544
 369  *  bytes.  The default value is zero. */
 370 #define GXIO_MPIPE_LINK_RECEIVE_JUMBO      0x010000
 371
 372 /** Determine whether to send pause frames on this link if the mPIPE packet
 373  *  FIFO is nearly full.  If the value is zero, pause frames are not sent.
 374  *  If the value is nonzero, it is the delay value which will be sent in any
 375  *  pause frames which are output, in units of 512 bit times.
 376  *
 377  *  Bear in mind that in almost all circumstances, the mPIPE packet FIFO
 378  *  will never fill up, since mPIPE will empty it as fast as or faster than
 379  *  the incoming data rate, by either delivering or dropping packets.  The
 380  *  only situation in which this is not true is if the memory and cache
 381  *  subsystem is extremely heavily loaded, and mPIPE cannot perform DMA of
 382  *  packet data to memory in a timely fashion.  In particular, pause frames
 383  *  will <em>not</em> be sent if packets cannot be delivered because
 384  *  NotifRings are full, buckets are full, or buffers are not available in
 385  *  a buffer stack. */
 386 #define GXIO_MPIPE_LINK_SEND_PAUSE         0x020000
 387
 388 /** Determine whether to suspend output on the receipt of pause frames.
 389  *  If the value is nonzero, mPIPE shim will suspend output on the link's
 390  *  channel when a pause frame is received.  If the value is zero, pause
 391  *  frames will be ignored.  The default value is zero. */
 392 #define GXIO_MPIPE_LINK_RECEIVE_PAUSE      0x030000
 393
 394 /** Interface MAC address.  The value is a 6-byte MAC address, in the least
 395  *  significant 48 bits of the value; in other words, an address which would
 396  *  be printed as '12:34:56:78:90:AB' in IEEE 802 canonical format would
 397  *  be returned as 0x12345678ab.
 398  *
 399  *  Depending upon the overall system design, a MAC address may or may not
 400  *  be available for each interface.  Note that the interface's MAC address
 401  *  does not limit the packets received on its channel, although the
 402  *  classifier's rules could be configured to do that.  Similarly, the MAC
 403  *  address is not used when transmitting packets, although applications
 404  *  could certainly decide to use the assigned address as a source MAC
 405  *  address when doing so.  This attribute may only be retrieved with
 406  *  gxio_mpipe_link_get_attr(); it may not be modified.
 407  */
 408 #define GXIO_MPIPE_LINK_MAC                0x040000
 409
 410 /** Determine whether to discard egress packets on link down. If this value
 411  *  is nonzero, packets sent on this link while the link is down will be
 412  *  discarded.  If this value is zero, no packets will be sent on this link
 413  *  while it is down.  The default value is one. */
 414 #define GXIO_MPIPE_LINK_DISCARD_IF_DOWN    0x050000
 415
 416 /** Possible link state.  The value is a combination of link state flags,
 417  *  ORed together, that indicate link modes which are actually supported by
 418  *  the hardware.  This attribute may only be retrieved with
 419  *  gxio_mpipe_link_get_attr(); it may not be modified. */
 420 #define GXIO_MPIPE_LINK_POSSIBLE_STATE     0x060000
 421
 422 /** Current link state.  The value is a combination of link state flags,
 423  *  ORed together, that indicate the current state of the hardware.  If the
 424  *  link is down, the value ANDed with ::GXIO_MPIPE_LINK_SPEED will be zero;
 425  *  if the link is up, the value ANDed with ::GXIO_MPIPE_LINK_SPEED will
 426  *  result in exactly one of the speed values, indicating the current speed.
 427  *  This attribute may only be retrieved with gxio_mpipe_link_get_attr(); it
 428  *  may not be modified. */
 429 #define GXIO_MPIPE_LINK_CURRENT_STATE      0x070000
 430
 431 /** Desired link state. The value is a conbination of flags, which specify
 432  *  the desired state for the link.  With gxio_mpipe_link_set_attr(), this
 433  *  will, in the background, attempt to bring up the link using whichever of
 434  *  the requested flags are reasonable, or take down the link if the flags
 435  *  are zero.  The actual link up or down operation may happen after this
 436  *  call completes.  If the link state changes in the future, the system
 437  *  will continue to try to get back to the desired link state; for
 438  *  instance, if the link is brought up successfully, and then the network
 439  *  cable is disconnected, the link will go down.  However, the desired
 440  *  state of the link is still up, so if the cable is reconnected, the link
 441  *  will be brought up again.
 442  *
 443  *  With gxio_mpipe_link_set_attr(), this will indicate the desired state
 444  *  for the link, as set with a previous gxio_mpipe_link_set_attr() call,
 445  *  or implicitly by a gxio_mpipe_link_open() or link close operation.
 446  *  This may not reflect the current state of the link; to get that, use
 447  *  ::GXIO_MPIPE_LINK_CURRENT_STATE.
 448  */
 449 #define GXIO_MPIPE_LINK_DESIRED_STATE      0x080000
 450
 451
 452
 453 /** Link can run, should run, or is running at 10 Mbps. */
 454 #define GXIO_MPIPE_LINK_10M        0x0000000000000001UL
 455
 456 /** Link can run, should run, or is running at 100 Mbps. */
 457 #define GXIO_MPIPE_LINK_100M       0x0000000000000002UL
 458
 459 /** Link can run, should run, or is running at 1 Gbps. */
 460 #define GXIO_MPIPE_LINK_1G         0x0000000000000004UL
 461
 462 /** Link can run, should run, or is running at 10 Gbps. */
 463 #define GXIO_MPIPE_LINK_10G        0x0000000000000008UL
 464
 465 /** Link can run, should run, or is running at 20 Gbps. */
 466 #define GXIO_MPIPE_LINK_20G        0x0000000000000010UL
 467
 468 /** Link can run, should run, or is running at 25 Gbps. */
 469 #define GXIO_MPIPE_LINK_25G        0x0000000000000020UL
 470
 471 /** Link can run, should run, or is running at 50 Gbps. */
 472 #define GXIO_MPIPE_LINK_50G        0x0000000000000040UL
 473
 474 /** Link should run at the highest speed supported by the link and by
 475  *  the device connected to the link.  Only usable as a value for
 476  *  the link's desired state; never returned as a value for the current
 477  *  or possible states. */
 478 #define GXIO_MPIPE_LINK_ANYSPEED   0x0000000000000800UL
 479
 480 /** All legal link speeds.  This value is provided for use in extracting
 481  *  the speed-related subset of the link state flags; it is not intended
 482  *  to be set directly as a value for one of the GXIO_MPIPE_LINK_xxx_STATE
 483  *  attributes.  A link is up or is requested to be up if its current or
 484  *  desired state, respectively, ANDED with this value, is nonzero. */
 485 #define GXIO_MPIPE_LINK_SPEED_MASK 0x0000000000000FFFUL
 486
 487 /** Link can run, should run, or is running in MAC loopback mode.  This
 488  *  loops transmitted packets back to the receiver, inside the Tile
 489  *  Processor. */
 490 #define GXIO_MPIPE_LINK_LOOP_MAC   0x0000000000001000UL
 491
 492 /** Link can run, should run, or is running in PHY loopback mode.  This
 493  *  loops transmitted packets back to the receiver, inside the external
 494  *  PHY chip. */
 495 #define GXIO_MPIPE_LINK_LOOP_PHY   0x0000000000002000UL
 496
 497 /** Link can run, should run, or is running in external loopback mode.
 498  *  This requires that an external loopback plug be installed on the
 499  *  Ethernet port.  Note that only some links require that this be
 500  *  configured via the gxio_mpipe_link routines; other links can do
 501  *  external loopack with the plug and no special configuration. */
 502 #define GXIO_MPIPE_LINK_LOOP_EXT   0x0000000000004000UL
 503
 504 /** All legal loopback types. */
 505 #define GXIO_MPIPE_LINK_LOOP_MASK  0x000000000000F000UL
 506
 507 /** Link can run, should run, or is running in full-duplex mode.
 508  *  If neither ::GXIO_MPIPE_LINK_FDX nor ::GXIO_MPIPE_LINK_HDX are
 509  *  specified in a set of desired state flags, both are assumed. */
 510 #define GXIO_MPIPE_LINK_FDX        0x0000000000010000UL
 511
 512 /** Link can run, should run, or is running in half-duplex mode.
 513  *  If neither ::GXIO_MPIPE_LINK_FDX nor ::GXIO_MPIPE_LINK_HDX are
 514  *  specified in a set of desired state flags, both are assumed. */
 515 #define GXIO_MPIPE_LINK_HDX        0x0000000000020000UL
 516
 517
 518 /** An individual rule. */
 519 typedef struct
 520 {
 521   /** The total size. */
 522   uint16_t size;
 523
 524   /** The priority. */
 525   int16_t priority;
 526
 527   /** The "headroom" in each buffer. */
 528   uint8_t headroom;
 529
 530   /** The "tailroom" in each buffer. */
 531   uint8_t tailroom;
 532
 533   /** The "capacity" of the largest buffer. */
 534   uint16_t capacity;
 535
 536   /** The mask for converting a flow hash into a bucket. */
 537   uint16_t bucket_mask;
 538
 539   /** The offset for converting a flow hash into a bucket. */
 540   uint16_t bucket_first;
 541
 542   /** The buffer stack ids. */
 543   gxio_mpipe_rules_stacks_t stacks;
 544
 545   /** The actual channels. */
 546   uint32_t channel_bits;
 547
 548   /** The number of dmacs. */
 549   uint16_t num_dmacs;
 550
 551   /** The number of vlans. */
 552   uint16_t num_vlans;
 553
 554   /** The actual dmacs and vlans. */
 555   uint8_t dmacs_and_vlans[];
 556
 557 } gxio_mpipe_rules_rule_t;
 558
 559
 560 /** A list of classifier rules. */
 561 typedef struct
 562 {
 563   /** The offset to the end of the current rule. */
 564   uint16_t tail;
 565
 566   /** The offset to the start of the current rule. */
 567   uint16_t head;
 568
 569   /** The actual rules. */
 570   uint8_t rules[4096 - 4];
 571
 572 } gxio_mpipe_rules_list_t;
 573
 574
 575
 576
 577 /** mPIPE statistics structure. These counters include all relevant
 578  *  events occurring on all links within the mPIPE shim. */
 579 typedef struct
 580 {
 581   /** Number of ingress packets dropped for any reason. */
 582   uint64_t ingress_drops;
 583   /** Number of ingress packets dropped because a buffer stack was empty. */
 584   uint64_t ingress_drops_no_buf;
 585   /** Number of ingress packets dropped or truncated due to lack of space in
 586    *  the iPkt buffer. */
 587   uint64_t ingress_drops_ipkt;
 588   /** Number of ingress packets dropped by the classifier or load balancer */
 589   uint64_t ingress_drops_cls_lb;
 590   /** Total number of ingress packets. */
 591   uint64_t ingress_packets;
 592   /** Total number of egress packets. */
 593   uint64_t egress_packets;
 594   /** Total number of ingress bytes. */
 595   uint64_t ingress_bytes;
 596   /** Total number of egress bytes. */
 597   uint64_t egress_bytes;
 598 }
 599 gxio_mpipe_stats_t;
 600
 601
 602 #endif /* _SYS_HV_DRV_MPIPE_INTF_H */