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Linux 3.11-rc3
[cris-mirror.git] / drivers / infiniband / hw / cxgb4 / iw_cxgb4.h
blob485183ad34cd7ab7b2db8c2e310974fb319bd616
1 /*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 * SOFTWARE.
30 */
31 #ifndef __IW_CXGB4_H__
32 #define __IW_CXGB4_H__
33
34 #include <linux/mutex.h>
35 #include <linux/list.h>
36 #include <linux/spinlock.h>
37 #include <linux/idr.h>
38 #include <linux/completion.h>
39 #include <linux/netdevice.h>
40 #include <linux/sched.h>
41 #include <linux/pci.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/inet.h>
44 #include <linux/wait.h>
45 #include <linux/kref.h>
46 #include <linux/timer.h>
47 #include <linux/io.h>
48
49 #include <asm/byteorder.h>
50
51 #include <net/net_namespace.h>
52
53 #include <rdma/ib_verbs.h>
54 #include <rdma/iw_cm.h>
55
56 #include "cxgb4.h"
57 #include "cxgb4_uld.h"
58 #include "l2t.h"
59 #include "user.h"
60
61 #define DRV_NAME "iw_cxgb4"
62 #define MOD DRV_NAME ":"
63
64 extern int c4iw_debug;
65 #define PDBG(fmt, args...) \
66 do { \
67 if (c4iw_debug) \
68 printk(MOD fmt, ## args); \
69 } while (0)
70
71 #include "t4.h"
72
73 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
74 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
75
76 static inline void *cplhdr(struct sk_buff *skb)
77 {
78 return skb->data;
79 }
80
81 #define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */
82 #define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */
83
84 struct c4iw_id_table {
85 u32 flags;
86 u32 start; /* logical minimal id */
87 u32 last; /* hint for find */
88 u32 max;
89 spinlock_t lock;
90 unsigned long *table;
91 };
92
93 struct c4iw_resource {
94 struct c4iw_id_table tpt_table;
95 struct c4iw_id_table qid_table;
96 struct c4iw_id_table pdid_table;
97 };
98
99 struct c4iw_qid_list {
100 struct list_head entry;
101 u32 qid;
102 };
103
104 struct c4iw_dev_ucontext {
105 struct list_head qpids;
106 struct list_head cqids;
107 struct mutex lock;
108 };
109
110 enum c4iw_rdev_flags {
111 T4_FATAL_ERROR = (1<<0),
112 };
113
114 struct c4iw_stat {
115 u64 total;
116 u64 cur;
117 u64 max;
118 u64 fail;
119 };
120
121 struct c4iw_stats {
122 struct mutex lock;
123 struct c4iw_stat qid;
124 struct c4iw_stat pd;
125 struct c4iw_stat stag;
126 struct c4iw_stat pbl;
127 struct c4iw_stat rqt;
128 struct c4iw_stat ocqp;
129 u64 db_full;
130 u64 db_empty;
131 u64 db_drop;
132 u64 db_state_transitions;
133 u64 tcam_full;
134 u64 act_ofld_conn_fails;
135 u64 pas_ofld_conn_fails;
136 };
137
138 struct c4iw_rdev {
139 struct c4iw_resource resource;
140 unsigned long qpshift;
141 u32 qpmask;
142 unsigned long cqshift;
143 u32 cqmask;
144 struct c4iw_dev_ucontext uctx;
145 struct gen_pool *pbl_pool;
146 struct gen_pool *rqt_pool;
147 struct gen_pool *ocqp_pool;
148 u32 flags;
149 struct cxgb4_lld_info lldi;
150 unsigned long oc_mw_pa;
151 void __iomem *oc_mw_kva;
152 struct c4iw_stats stats;
153 };
154
155 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
156 {
157 return rdev->flags & T4_FATAL_ERROR;
158 }
159
160 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
161 {
162 return min((int)T4_MAX_NUM_STAG, (int)(rdev->lldi.vr->stag.size >> 5));
163 }
164
165 #define C4IW_WR_TO (30*HZ)
166
167 struct c4iw_wr_wait {
168 struct completion completion;
169 int ret;
170 };
171
172 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
173 {
174 wr_waitp->ret = 0;
175 init_completion(&wr_waitp->completion);
176 }
177
178 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
179 {
180 wr_waitp->ret = ret;
181 complete(&wr_waitp->completion);
182 }
183
184 static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
185 struct c4iw_wr_wait *wr_waitp,
186 u32 hwtid, u32 qpid,
187 const char *func)
188 {
189 unsigned to = C4IW_WR_TO;
190 int ret;
191
192 do {
193 ret = wait_for_completion_timeout(&wr_waitp->completion, to);
194 if (!ret) {
195 printk(KERN_ERR MOD "%s - Device %s not responding - "
196 "tid %u qpid %u\n", func,
197 pci_name(rdev->lldi.pdev), hwtid, qpid);
198 if (c4iw_fatal_error(rdev)) {
199 wr_waitp->ret = -EIO;
200 break;
201 }
202 to = to << 2;
203 }
204 } while (!ret);
205 if (wr_waitp->ret)
206 PDBG("%s: FW reply %d tid %u qpid %u\n",
207 pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid);
208 return wr_waitp->ret;
209 }
210
211 enum db_state {
212 NORMAL = 0,
213 FLOW_CONTROL = 1,
214 RECOVERY = 2
215 };
216
217 struct c4iw_dev {
218 struct ib_device ibdev;
219 struct c4iw_rdev rdev;
220 u32 device_cap_flags;
221 struct idr cqidr;
222 struct idr qpidr;
223 struct idr mmidr;
224 spinlock_t lock;
225 struct mutex db_mutex;
226 struct dentry *debugfs_root;
227 enum db_state db_state;
228 int qpcnt;
229 struct idr hwtid_idr;
230 struct idr atid_idr;
231 struct idr stid_idr;
232 };
233
234 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
235 {
236 return container_of(ibdev, struct c4iw_dev, ibdev);
237 }
238
239 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
240 {
241 return container_of(rdev, struct c4iw_dev, rdev);
242 }
243
244 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
245 {
246 return idr_find(&rhp->cqidr, cqid);
247 }
248
249 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
250 {
251 return idr_find(&rhp->qpidr, qpid);
252 }
253
254 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
255 {
256 return idr_find(&rhp->mmidr, mmid);
257 }
258
259 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
260 void *handle, u32 id, int lock)
261 {
262 int ret;
263
264 if (lock) {
265 idr_preload(GFP_KERNEL);
266 spin_lock_irq(&rhp->lock);
267 }
268
269 ret = idr_alloc(idr, handle, id, id + 1, GFP_ATOMIC);
270
271 if (lock) {
272 spin_unlock_irq(&rhp->lock);
273 idr_preload_end();
274 }
275
276 BUG_ON(ret == -ENOSPC);
277 return ret < 0 ? ret : 0;
278 }
279
280 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
281 void *handle, u32 id)
282 {
283 return _insert_handle(rhp, idr, handle, id, 1);
284 }
285
286 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
287 void *handle, u32 id)
288 {
289 return _insert_handle(rhp, idr, handle, id, 0);
290 }
291
292 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
293 u32 id, int lock)
294 {
295 if (lock)
296 spin_lock_irq(&rhp->lock);
297 idr_remove(idr, id);
298 if (lock)
299 spin_unlock_irq(&rhp->lock);
300 }
301
302 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
303 {
304 _remove_handle(rhp, idr, id, 1);
305 }
306
307 static inline void remove_handle_nolock(struct c4iw_dev *rhp,
308 struct idr *idr, u32 id)
309 {
310 _remove_handle(rhp, idr, id, 0);
311 }
312
313 struct c4iw_pd {
314 struct ib_pd ibpd;
315 u32 pdid;
316 struct c4iw_dev *rhp;
317 };
318
319 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
320 {
321 return container_of(ibpd, struct c4iw_pd, ibpd);
322 }
323
324 struct tpt_attributes {
325 u64 len;
326 u64 va_fbo;
327 enum fw_ri_mem_perms perms;
328 u32 stag;
329 u32 pdid;
330 u32 qpid;
331 u32 pbl_addr;
332 u32 pbl_size;
333 u32 state:1;
334 u32 type:2;
335 u32 rsvd:1;
336 u32 remote_invaliate_disable:1;
337 u32 zbva:1;
338 u32 mw_bind_enable:1;
339 u32 page_size:5;
340 };
341
342 struct c4iw_mr {
343 struct ib_mr ibmr;
344 struct ib_umem *umem;
345 struct c4iw_dev *rhp;
346 u64 kva;
347 struct tpt_attributes attr;
348 };
349
350 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
351 {
352 return container_of(ibmr, struct c4iw_mr, ibmr);
353 }
354
355 struct c4iw_mw {
356 struct ib_mw ibmw;
357 struct c4iw_dev *rhp;
358 u64 kva;
359 struct tpt_attributes attr;
360 };
361
362 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
363 {
364 return container_of(ibmw, struct c4iw_mw, ibmw);
365 }
366
367 struct c4iw_fr_page_list {
368 struct ib_fast_reg_page_list ibpl;
369 DEFINE_DMA_UNMAP_ADDR(mapping);
370 dma_addr_t dma_addr;
371 struct c4iw_dev *dev;
372 };
373
374 static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
375 struct ib_fast_reg_page_list *ibpl)
376 {
377 return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
378 }
379
380 struct c4iw_cq {
381 struct ib_cq ibcq;
382 struct c4iw_dev *rhp;
383 struct t4_cq cq;
384 spinlock_t lock;
385 spinlock_t comp_handler_lock;
386 atomic_t refcnt;
387 wait_queue_head_t wait;
388 };
389
390 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
391 {
392 return container_of(ibcq, struct c4iw_cq, ibcq);
393 }
394
395 struct c4iw_mpa_attributes {
396 u8 initiator;
397 u8 recv_marker_enabled;
398 u8 xmit_marker_enabled;
399 u8 crc_enabled;
400 u8 enhanced_rdma_conn;
401 u8 version;
402 u8 p2p_type;
403 };
404
405 struct c4iw_qp_attributes {
406 u32 scq;
407 u32 rcq;
408 u32 sq_num_entries;
409 u32 rq_num_entries;
410 u32 sq_max_sges;
411 u32 sq_max_sges_rdma_write;
412 u32 rq_max_sges;
413 u32 state;
414 u8 enable_rdma_read;
415 u8 enable_rdma_write;
416 u8 enable_bind;
417 u8 enable_mmid0_fastreg;
418 u32 max_ord;
419 u32 max_ird;
420 u32 pd;
421 u32 next_state;
422 char terminate_buffer[52];
423 u32 terminate_msg_len;
424 u8 is_terminate_local;
425 struct c4iw_mpa_attributes mpa_attr;
426 struct c4iw_ep *llp_stream_handle;
427 u8 layer_etype;
428 u8 ecode;
429 u16 sq_db_inc;
430 u16 rq_db_inc;
431 };
432
433 struct c4iw_qp {
434 struct ib_qp ibqp;
435 struct c4iw_dev *rhp;
436 struct c4iw_ep *ep;
437 struct c4iw_qp_attributes attr;
438 struct t4_wq wq;
439 spinlock_t lock;
440 struct mutex mutex;
441 atomic_t refcnt;
442 wait_queue_head_t wait;
443 struct timer_list timer;
444 };
445
446 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
447 {
448 return container_of(ibqp, struct c4iw_qp, ibqp);
449 }
450
451 struct c4iw_ucontext {
452 struct ib_ucontext ibucontext;
453 struct c4iw_dev_ucontext uctx;
454 u32 key;
455 spinlock_t mmap_lock;
456 struct list_head mmaps;
457 };
458
459 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
460 {
461 return container_of(c, struct c4iw_ucontext, ibucontext);
462 }
463
464 struct c4iw_mm_entry {
465 struct list_head entry;
466 u64 addr;
467 u32 key;
468 unsigned len;
469 };
470
471 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
472 u32 key, unsigned len)
473 {
474 struct list_head *pos, *nxt;
475 struct c4iw_mm_entry *mm;
476
477 spin_lock(&ucontext->mmap_lock);
478 list_for_each_safe(pos, nxt, &ucontext->mmaps) {
479
480 mm = list_entry(pos, struct c4iw_mm_entry, entry);
481 if (mm->key == key && mm->len == len) {
482 list_del_init(&mm->entry);
483 spin_unlock(&ucontext->mmap_lock);
484 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
485 key, (unsigned long long) mm->addr, mm->len);
486 return mm;
487 }
488 }
489 spin_unlock(&ucontext->mmap_lock);
490 return NULL;
491 }
492
493 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
494 struct c4iw_mm_entry *mm)
495 {
496 spin_lock(&ucontext->mmap_lock);
497 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
498 mm->key, (unsigned long long) mm->addr, mm->len);
499 list_add_tail(&mm->entry, &ucontext->mmaps);
500 spin_unlock(&ucontext->mmap_lock);
501 }
502
503 enum c4iw_qp_attr_mask {
504 C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
505 C4IW_QP_ATTR_SQ_DB = 1<<1,
506 C4IW_QP_ATTR_RQ_DB = 1<<2,
507 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
508 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
509 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
510 C4IW_QP_ATTR_MAX_ORD = 1 << 11,
511 C4IW_QP_ATTR_MAX_IRD = 1 << 12,
512 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
513 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
514 C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
515 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
516 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
517 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
518 C4IW_QP_ATTR_MAX_ORD |
519 C4IW_QP_ATTR_MAX_IRD |
520 C4IW_QP_ATTR_LLP_STREAM_HANDLE |
521 C4IW_QP_ATTR_STREAM_MSG_BUFFER |
522 C4IW_QP_ATTR_MPA_ATTR |
523 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
524 };
525
526 int c4iw_modify_qp(struct c4iw_dev *rhp,
527 struct c4iw_qp *qhp,
528 enum c4iw_qp_attr_mask mask,
529 struct c4iw_qp_attributes *attrs,
530 int internal);
531
532 enum c4iw_qp_state {
533 C4IW_QP_STATE_IDLE,
534 C4IW_QP_STATE_RTS,
535 C4IW_QP_STATE_ERROR,
536 C4IW_QP_STATE_TERMINATE,
537 C4IW_QP_STATE_CLOSING,
538 C4IW_QP_STATE_TOT
539 };
540
541 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
542 {
543 switch (ib_state) {
544 case IB_QPS_RESET:
545 case IB_QPS_INIT:
546 return C4IW_QP_STATE_IDLE;
547 case IB_QPS_RTS:
548 return C4IW_QP_STATE_RTS;
549 case IB_QPS_SQD:
550 return C4IW_QP_STATE_CLOSING;
551 case IB_QPS_SQE:
552 return C4IW_QP_STATE_TERMINATE;
553 case IB_QPS_ERR:
554 return C4IW_QP_STATE_ERROR;
555 default:
556 return -1;
557 }
558 }
559
560 static inline int to_ib_qp_state(int c4iw_qp_state)
561 {
562 switch (c4iw_qp_state) {
563 case C4IW_QP_STATE_IDLE:
564 return IB_QPS_INIT;
565 case C4IW_QP_STATE_RTS:
566 return IB_QPS_RTS;
567 case C4IW_QP_STATE_CLOSING:
568 return IB_QPS_SQD;
569 case C4IW_QP_STATE_TERMINATE:
570 return IB_QPS_SQE;
571 case C4IW_QP_STATE_ERROR:
572 return IB_QPS_ERR;
573 }
574 return IB_QPS_ERR;
575 }
576
577 static inline u32 c4iw_ib_to_tpt_access(int a)
578 {
579 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
580 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
581 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
582 FW_RI_MEM_ACCESS_LOCAL_READ;
583 }
584
585 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
586 {
587 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
588 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
589 }
590
591 enum c4iw_mmid_state {
592 C4IW_STAG_STATE_VALID,
593 C4IW_STAG_STATE_INVALID
594 };
595
596 #define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
597
598 #define MPA_KEY_REQ "MPA ID Req Frame"
599 #define MPA_KEY_REP "MPA ID Rep Frame"
600
601 #define MPA_MAX_PRIVATE_DATA 256
602 #define MPA_ENHANCED_RDMA_CONN 0x10
603 #define MPA_REJECT 0x20
604 #define MPA_CRC 0x40
605 #define MPA_MARKERS 0x80
606 #define MPA_FLAGS_MASK 0xE0
607
608 #define MPA_V2_PEER2PEER_MODEL 0x8000
609 #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000
610 #define MPA_V2_RDMA_WRITE_RTR 0x8000
611 #define MPA_V2_RDMA_READ_RTR 0x4000
612 #define MPA_V2_IRD_ORD_MASK 0x3FFF
613
614 #define c4iw_put_ep(ep) { \
615 PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__, \
616 ep, atomic_read(&((ep)->kref.refcount))); \
617 WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \
618 kref_put(&((ep)->kref), _c4iw_free_ep); \
619 }
620
621 #define c4iw_get_ep(ep) { \
622 PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
623 ep, atomic_read(&((ep)->kref.refcount))); \
624 kref_get(&((ep)->kref)); \
625 }
626 void _c4iw_free_ep(struct kref *kref);
627
628 struct mpa_message {
629 u8 key[16];
630 u8 flags;
631 u8 revision;
632 __be16 private_data_size;
633 u8 private_data[0];
634 };
635
636 struct mpa_v2_conn_params {
637 __be16 ird;
638 __be16 ord;
639 };
640
641 struct terminate_message {
642 u8 layer_etype;
643 u8 ecode;
644 __be16 hdrct_rsvd;
645 u8 len_hdrs[0];
646 };
647
648 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
649
650 enum c4iw_layers_types {
651 LAYER_RDMAP = 0x00,
652 LAYER_DDP = 0x10,
653 LAYER_MPA = 0x20,
654 RDMAP_LOCAL_CATA = 0x00,
655 RDMAP_REMOTE_PROT = 0x01,
656 RDMAP_REMOTE_OP = 0x02,
657 DDP_LOCAL_CATA = 0x00,
658 DDP_TAGGED_ERR = 0x01,
659 DDP_UNTAGGED_ERR = 0x02,
660 DDP_LLP = 0x03
661 };
662
663 enum c4iw_rdma_ecodes {
664 RDMAP_INV_STAG = 0x00,
665 RDMAP_BASE_BOUNDS = 0x01,
666 RDMAP_ACC_VIOL = 0x02,
667 RDMAP_STAG_NOT_ASSOC = 0x03,
668 RDMAP_TO_WRAP = 0x04,
669 RDMAP_INV_VERS = 0x05,
670 RDMAP_INV_OPCODE = 0x06,
671 RDMAP_STREAM_CATA = 0x07,
672 RDMAP_GLOBAL_CATA = 0x08,
673 RDMAP_CANT_INV_STAG = 0x09,
674 RDMAP_UNSPECIFIED = 0xff
675 };
676
677 enum c4iw_ddp_ecodes {
678 DDPT_INV_STAG = 0x00,
679 DDPT_BASE_BOUNDS = 0x01,
680 DDPT_STAG_NOT_ASSOC = 0x02,
681 DDPT_TO_WRAP = 0x03,
682 DDPT_INV_VERS = 0x04,
683 DDPU_INV_QN = 0x01,
684 DDPU_INV_MSN_NOBUF = 0x02,
685 DDPU_INV_MSN_RANGE = 0x03,
686 DDPU_INV_MO = 0x04,
687 DDPU_MSG_TOOBIG = 0x05,
688 DDPU_INV_VERS = 0x06
689 };
690
691 enum c4iw_mpa_ecodes {
692 MPA_CRC_ERR = 0x02,
693 MPA_MARKER_ERR = 0x03,
694 MPA_LOCAL_CATA = 0x05,
695 MPA_INSUFF_IRD = 0x06,
696 MPA_NOMATCH_RTR = 0x07,
697 };
698
699 enum c4iw_ep_state {
700 IDLE = 0,
701 LISTEN,
702 CONNECTING,
703 MPA_REQ_WAIT,
704 MPA_REQ_SENT,
705 MPA_REQ_RCVD,
706 MPA_REP_SENT,
707 FPDU_MODE,
708 ABORTING,
709 CLOSING,
710 MORIBUND,
711 DEAD,
712 };
713
714 enum c4iw_ep_flags {
715 PEER_ABORT_IN_PROGRESS = 0,
716 ABORT_REQ_IN_PROGRESS = 1,
717 RELEASE_RESOURCES = 2,
718 CLOSE_SENT = 3,
719 TIMEOUT = 4,
720 QP_REFERENCED = 5,
721 };
722
723 enum c4iw_ep_history {
724 ACT_OPEN_REQ = 0,
725 ACT_OFLD_CONN = 1,
726 ACT_OPEN_RPL = 2,
727 ACT_ESTAB = 3,
728 PASS_ACCEPT_REQ = 4,
729 PASS_ESTAB = 5,
730 ABORT_UPCALL = 6,
731 ESTAB_UPCALL = 7,
732 CLOSE_UPCALL = 8,
733 ULP_ACCEPT = 9,
734 ULP_REJECT = 10,
735 TIMEDOUT = 11,
736 PEER_ABORT = 12,
737 PEER_CLOSE = 13,
738 CONNREQ_UPCALL = 14,
739 ABORT_CONN = 15,
740 DISCONN_UPCALL = 16,
741 EP_DISC_CLOSE = 17,
742 EP_DISC_ABORT = 18,
743 CONN_RPL_UPCALL = 19,
744 ACT_RETRY_NOMEM = 20,
745 ACT_RETRY_INUSE = 21
746 };
747
748 struct c4iw_ep_common {
749 struct iw_cm_id *cm_id;
750 struct c4iw_qp *qp;
751 struct c4iw_dev *dev;
752 enum c4iw_ep_state state;
753 struct kref kref;
754 struct mutex mutex;
755 struct sockaddr_in local_addr;
756 struct sockaddr_in remote_addr;
757 struct c4iw_wr_wait wr_wait;
758 unsigned long flags;
759 unsigned long history;
760 };
761
762 struct c4iw_listen_ep {
763 struct c4iw_ep_common com;
764 unsigned int stid;
765 int backlog;
766 };
767
768 struct c4iw_ep {
769 struct c4iw_ep_common com;
770 struct c4iw_ep *parent_ep;
771 struct timer_list timer;
772 struct list_head entry;
773 unsigned int atid;
774 u32 hwtid;
775 u32 snd_seq;
776 u32 rcv_seq;
777 struct l2t_entry *l2t;
778 struct dst_entry *dst;
779 struct sk_buff *mpa_skb;
780 struct c4iw_mpa_attributes mpa_attr;
781 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
782 unsigned int mpa_pkt_len;
783 u32 ird;
784 u32 ord;
785 u32 smac_idx;
786 u32 tx_chan;
787 u32 mtu;
788 u16 mss;
789 u16 emss;
790 u16 plen;
791 u16 rss_qid;
792 u16 txq_idx;
793 u16 ctrlq_idx;
794 u8 tos;
795 u8 retry_with_mpa_v1;
796 u8 tried_with_mpa_v1;
797 unsigned int retry_count;
798 };
799
800 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
801 {
802 return cm_id->provider_data;
803 }
804
805 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
806 {
807 return cm_id->provider_data;
808 }
809
810 static inline int compute_wscale(int win)
811 {
812 int wscale = 0;
813
814 while (wscale < 14 && (65535<<wscale) < win)
815 wscale++;
816 return wscale;
817 }
818
819 static inline int ocqp_supported(const struct cxgb4_lld_info *infop)
820 {
821 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
822 return infop->vr->ocq.size > 0;
823 #else
824 return 0;
825 #endif
826 }
827
828 u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
829 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
830 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
831 u32 reserved, u32 flags);
832 void c4iw_id_table_free(struct c4iw_id_table *alloc);
833
834 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);
835
836 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
837 struct l2t_entry *l2t);
838 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
839 struct c4iw_dev_ucontext *uctx);
840 u32 c4iw_get_resource(struct c4iw_id_table *id_table);
841 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
842 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
843 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
844 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
845 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
846 int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev);
847 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
848 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
849 void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev);
850 void c4iw_destroy_resource(struct c4iw_resource *rscp);
851 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
852 int c4iw_register_device(struct c4iw_dev *dev);
853 void c4iw_unregister_device(struct c4iw_dev *dev);
854 int __init c4iw_cm_init(void);
855 void __exit c4iw_cm_term(void);
856 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
857 struct c4iw_dev_ucontext *uctx);
858 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
859 struct c4iw_dev_ucontext *uctx);
860 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
861 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
862 struct ib_send_wr **bad_wr);
863 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
864 struct ib_recv_wr **bad_wr);
865 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
866 struct ib_mw_bind *mw_bind);
867 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
868 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
869 int c4iw_destroy_listen(struct iw_cm_id *cm_id);
870 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
871 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
872 void c4iw_qp_add_ref(struct ib_qp *qp);
873 void c4iw_qp_rem_ref(struct ib_qp *qp);
874 void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
875 struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
876 struct ib_device *device,
877 int page_list_len);
878 struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);
879 int c4iw_dealloc_mw(struct ib_mw *mw);
880 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type);
881 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
882 u64 length, u64 virt, int acc,
883 struct ib_udata *udata);
884 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
885 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
886 struct ib_phys_buf *buffer_list,
887 int num_phys_buf,
888 int acc,
889 u64 *iova_start);
890 int c4iw_reregister_phys_mem(struct ib_mr *mr,
891 int mr_rereg_mask,
892 struct ib_pd *pd,
893 struct ib_phys_buf *buffer_list,
894 int num_phys_buf,
895 int acc, u64 *iova_start);
896 int c4iw_dereg_mr(struct ib_mr *ib_mr);
897 int c4iw_destroy_cq(struct ib_cq *ib_cq);
898 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
899 int vector,
900 struct ib_ucontext *ib_context,
901 struct ib_udata *udata);
902 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
903 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
904 int c4iw_destroy_qp(struct ib_qp *ib_qp);
905 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
906 struct ib_qp_init_attr *attrs,
907 struct ib_udata *udata);
908 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
909 int attr_mask, struct ib_udata *udata);
910 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
911 int attr_mask, struct ib_qp_init_attr *init_attr);
912 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
913 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
914 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
915 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
916 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
917 u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size);
918 void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size);
919 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
920 void c4iw_flush_hw_cq(struct t4_cq *cq);
921 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
922 void c4iw_count_scqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
923 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
924 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
925 int c4iw_flush_sq(struct t4_wq *wq, struct t4_cq *cq, int count);
926 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
927 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
928 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
929 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
930 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
931 struct c4iw_dev_ucontext *uctx);
932 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
933 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
934 struct c4iw_dev_ucontext *uctx);
935 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
936
937 extern struct cxgb4_client t4c_client;
938 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
939 extern int c4iw_max_read_depth;
940 extern int db_fc_threshold;
941 extern int db_coalescing_threshold;
942 extern int use_dsgl;
943
944
945 #endif
CRIS linux kernel tree