| blob | 77f81cbb601a4b248f4018f76a3d6efbb94726bc |
1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/vmalloc.h>
36 #include <linux/pagemap.h>
37 #include <linux/delay.h>
38 #include <linux/netdevice.h>
39 #include <linux/interrupt.h>
40 #include <linux/tcp.h>
41 #include <linux/ipv6.h>
42 #include <linux/slab.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/ethtool.h>
46 #include <linux/if_vlan.h>
47 #include <linux/cpu.h>
48 #include <linux/smp.h>
49 #include <linux/pm_qos.h>
50 #include <linux/pm_runtime.h>
51 #include <linux/aer.h>
52 #include <linux/prefetch.h>
62 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
82 };
85 u32 ofs;
87 };
90 /* General Registers */
95 /* Interrupt Registers */
98 /* Rx Registers */
114 /* Tx Registers */
131 /* List Terminator */
133 };
135 /**
136 * e1000_regdump - register printout routine
137 * @hw: pointer to the HW structure
138 * @reginfo: pointer to the register info table
139 **/
141 {
163 }
167 }
171 {
183 }
184 }
185 }
187 /**
188 * e1000e_dump - Print registers, Tx-ring and Rx-ring
189 * @adapter: board private structure
190 **/
192 {
199 __le64 a;
200 __le64 b;
207 __le64 a;
208 __le64 b;
209 __le64 c;
210 __le64 d;
212 u32 staterr;
218 /* Print netdevice Info */
224 }
226 /* Print Registers */
232 }
234 /* Print Tx Ring Summary */
248 /* Print Tx Ring */
254 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
255 *
256 * Legacy Transmit Descriptor
257 * +--------------------------------------------------------------+
258 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
259 * +--------------------------------------------------------------+
260 * 8 | Special | CSS | Status | CMD | CSO | Length |
261 * +--------------------------------------------------------------+
262 * 63 48 47 36 35 32 31 24 23 16 15 0
263 *
264 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
265 * 63 48 47 40 39 32 31 16 15 8 7 0
266 * +----------------------------------------------------------------+
267 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
268 * +----------------------------------------------------------------+
269 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
270 * +----------------------------------------------------------------+
271 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
272 *
273 * Extended Data Descriptor (DTYP=0x1)
274 * +----------------------------------------------------------------+
275 * 0 | Buffer Address [63:0] |
276 * +----------------------------------------------------------------+
277 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
278 * +----------------------------------------------------------------+
279 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
280 */
281 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
282 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
283 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
295 else
300 i,
312 }
314 /* Print Rx Ring Summary */
315 rx_ring_summary:
321 /* Print Rx Ring */
330 /* [Extended] Packet Split Receive Descriptor Format
331 *
332 * +-----------------------------------------------------+
333 * 0 | Buffer Address 0 [63:0] |
334 * +-----------------------------------------------------+
335 * 8 | Buffer Address 1 [63:0] |
336 * +-----------------------------------------------------+
337 * 16 | Buffer Address 2 [63:0] |
338 * +-----------------------------------------------------+
339 * 24 | Buffer Address 3 [63:0] |
340 * +-----------------------------------------------------+
341 */
342 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
343 /* [Extended] Receive Descriptor (Write-Back) Format
344 *
345 * 63 48 47 32 31 13 12 8 7 4 3 0
346 * +------------------------------------------------------+
347 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
348 * | Checksum | Ident | | Queue | | Type |
349 * +------------------------------------------------------+
350 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
351 * +------------------------------------------------------+
352 * 63 48 47 32 31 20 19 0
353 */
354 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
360 staterr =
367 else
371 /* Descriptor Done */
391 buffer_info);
392 }
393 }
397 /* Extended Receive Descriptor (Read) Format
398 *
399 * +-----------------------------------------------------+
400 * 0 | Buffer Address [63:0] |
401 * +-----------------------------------------------------+
402 * 8 | Reserved |
403 * +-----------------------------------------------------+
404 */
405 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
406 /* Extended Receive Descriptor (Write-Back) Format
407 *
408 * 63 48 47 32 31 24 23 4 3 0
409 * +------------------------------------------------------+
410 * | RSS Hash | | | |
411 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
412 * | Packet | IP | | | Type |
413 * | Checksum | Ident | | | |
414 * +------------------------------------------------------+
415 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
416 * +------------------------------------------------------+
417 * 63 48 47 32 31 20 19 0
418 */
433 else
437 /* Descriptor Done */
459 }
460 }
461 }
462 }
464 /**
465 * e1000_desc_unused - calculate if we have unused descriptors
466 **/
468 {
473 }
475 /**
476 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
477 * @adapter: board private structure
478 * @hwtstamps: time stamp structure to update
479 * @systim: unsigned 64bit system time value.
480 *
481 * Convert the system time value stored in the RX/TXSTMP registers into a
482 * hwtstamp which can be used by the upper level time stamping functions.
483 *
484 * The 'systim_lock' spinlock is used to protect the consistency of the
485 * system time value. This is needed because reading the 64 bit time
486 * value involves reading two 32 bit registers. The first read latches the
487 * value.
488 **/
491 u64 systim)
492 {
493 u64 ns;
502 }
504 /**
505 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
506 * @adapter: board private structure
507 * @status: descriptor extended error and status field
508 * @skb: particular skb to include time stamp
509 *
510 * If the time stamp is valid, convert it into the timecounter ns value
511 * and store that result into the shhwtstamps structure which is passed
512 * up the network stack.
513 **/
516 {
518 u64 rxstmp;
525 /* The Rx time stamp registers contain the time stamp. No other
526 * received packet will be time stamped until the Rx time stamp
527 * registers are read. Because only one packet can be time stamped
528 * at a time, the register values must belong to this packet and
529 * therefore none of the other additional attributes need to be
530 * compared.
531 */
537 }
539 /**
540 * e1000_receive_skb - helper function to handle Rx indications
541 * @adapter: board private structure
542 * @staterr: descriptor extended error and status field as written by hardware
543 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
544 * @skb: pointer to sk_buff to be indicated to stack
545 **/
549 {
560 }
562 /**
563 * e1000_rx_checksum - Receive Checksum Offload
564 * @adapter: board private structure
565 * @status_err: receive descriptor status and error fields
566 * @csum: receive descriptor csum field
567 * @sk_buff: socket buffer with received data
568 **/
571 {
577 /* Rx checksum disabled */
581 /* Ignore Checksum bit is set */
585 /* TCP/UDP checksum error bit or IP checksum error bit is set */
587 /* let the stack verify checksum errors */
590 }
592 /* TCP/UDP Checksum has not been calculated */
596 /* It must be a TCP or UDP packet with a valid checksum */
599 }
602 {
614 }
615 }
618 {
630 }
631 }
633 /**
634 * e1000_alloc_rx_buffers - Replace used receive buffers
635 * @rx_ring: Rx descriptor ring
636 **/
639 {
657 }
661 /* Better luck next round */
664 }
667 map_skb:
670 DMA_FROM_DEVICE);
675 }
681 /* Force memory writes to complete before letting h/w
682 * know there are new descriptors to fetch. (Only
683 * applicable for weak-ordered memory model archs,
684 * such as IA-64).
685 */
689 else
691 }
692 i++;
696 }
699 }
701 /**
702 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
703 * @rx_ring: Rx descriptor ring
704 **/
707 {
726 /* all unused desc entries get hw null ptr */
730 }
736 }
740 DMA_FROM_DEVICE);
747 }
748 }
749 /* Refresh the desc even if buffer_addrs
750 * didn't change because each write-back
751 * erases this info.
752 */
755 }
758 gfp);
763 }
768 DMA_FROM_DEVICE);
772 /* cleanup skb */
776 }
781 /* Force memory writes to complete before letting h/w
782 * know there are new descriptors to fetch. (Only
783 * applicable for weak-ordered memory model archs,
784 * such as IA-64).
785 */
789 else
791 }
793 i++;
797 }
799 no_buffers:
801 }
803 /**
804 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
805 * @rx_ring: Rx descriptor ring
806 * @cleaned_count: number of buffers to allocate this pass
807 **/
811 {
829 }
833 /* Better luck next round */
836 }
839 check_page:
840 /* allocate a new page if necessary */
846 }
847 }
852 PAGE_SIZE,
853 DMA_FROM_DEVICE);
857 }
858 }
866 }
873 /* Force memory writes to complete before letting h/w
874 * know there are new descriptors to fetch. (Only
875 * applicable for weak-ordered memory model archs,
876 * such as IA-64).
877 */
881 else
883 }
884 }
888 {
891 }
893 /**
894 * e1000_clean_rx_irq - Send received data up the network stack
895 * @rx_ring: Rx descriptor ring
896 *
897 * the return value indicates whether actual cleaning was done, there
898 * is no guarantee that everything was cleaned
899 **/
902 {
933 i++;
942 cleaned_count++;
949 /* !EOP means multiple descriptors were used to store a single
950 * packet, if that's the case we need to toss it. In fact, we
951 * need to toss every packet with the EOP bit clear and the
952 * next frame that _does_ have the EOP bit set, as it is by
953 * definition only a frame fragment
954 */
959 /* All receives must fit into a single buffer */
961 /* recycle */
966 }
970 /* recycle */
973 }
975 /* adjust length to remove Ethernet CRC */
977 /* If configured to store CRC, don't subtract FCS,
978 * but keep the FCS bytes out of the total_rx_bytes
979 * counter
980 */
983 else
985 }
988 total_rx_packets++;
990 /* code added for copybreak, this should improve
991 * performance for small packets with large amounts
992 * of reassembly being done in the stack
993 */
1001 NET_IP_ALIGN),
1003 NET_IP_ALIGN));
1004 /* save the skb in buffer_info as good */
1007 }
1008 /* else just continue with the old one */
1009 }
1010 /* end copybreak code */
1013 /* Receive Checksum Offload */
1021 next_desc:
1024 /* return some buffers to hardware, one at a time is too slow */
1027 GFP_ATOMIC);
1029 }
1031 /* use prefetched values */
1036 }
1046 }
1050 {
1057 else
1061 }
1065 }
1067 }
1070 {
1073 print_hang_task);
1081 u16 pci_status;
1087 /* May be block on write-back, flush and detect again
1088 * flush pending descriptor writebacks to memory
1089 */
1091 /* execute the writes immediately */
1093 /* Due to rare timing issues, write to TIDV again to ensure
1094 * the write is successful
1095 */
1097 /* execute the writes immediately */
1101 }
1102 /* Real hang detected */
1112 /* detected Hardware unit hang */
1133 /* Suggest workaround for known h/w issue */
1136 }
1138 /**
1139 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1140 * @work: pointer to work struct
1141 *
1142 * This work function polls the TSYNCTXCTL valid bit to determine when a
1143 * timestamp has been taken for the current stored skb. The timestamp must
1144 * be for this skb because only one such packet is allowed in the queue.
1145 */
1147 {
1149 tx_hwtstamp_work);
1157 u64 txstmp;
1168 /* reschedule to check later */
1170 }
1171 }
1173 /**
1174 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1175 * @tx_ring: Tx descriptor ring
1176 *
1177 * the return value indicates whether actual cleaning was done, there
1178 * is no guarantee that everything was cleaned
1179 **/
1181 {
1210 pkts_compl++;
1211 }
1212 }
1217 i++;
1220 }
1226 }
1232 #define TX_WAKE_THRESHOLD 32
1235 /* Make sure that anybody stopping the queue after this
1236 * sees the new next_to_clean.
1237 */
1244 }
1245 }
1248 /* Detect a transmit hang in hardware, this serializes the
1249 * check with the clearing of time_stamp and movement of i
1250 */
1257 else
1259 }
1263 }
1265 /**
1266 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1267 * @rx_ring: Rx descriptor ring
1268 *
1269 * the return value indicates whether actual cleaning was done, there
1270 * is no guarantee that everything was cleaned
1271 **/
1274 {
1301 /* in the packet split case this is header only */
1304 i++;
1313 cleaned_count++;
1318 /* see !EOP comment in other Rx routine */
1328 }
1334 }
1342 }
1344 /* Good Receive */
1347 {
1348 /* this looks ugly, but it seems compiler issues make
1349 * it more efficient than reusing j
1350 */
1353 /* page alloc/put takes too long and effects small
1354 * packet throughput, so unsplit small packets and
1355 * save the alloc/put only valid in softirq (napi)
1356 * context to call kmap_*
1357 */
1364 /* there is no documentation about how to call
1365 * kmap_atomic, so we can't hold the mapping
1366 * very long
1367 */
1370 PAGE_SIZE,
1371 DMA_FROM_DEVICE);
1377 PAGE_SIZE,
1378 DMA_FROM_DEVICE);
1380 /* remove the CRC */
1384 }
1389 }
1398 DMA_FROM_DEVICE);
1405 }
1407 /* strip the ethernet crc, problem is we're using pages now so
1408 * this whole operation can get a little cpu intensive
1409 */
1413 }
1415 copydone:
1417 total_rx_packets++;
1430 next_desc:
1434 /* return some buffers to hardware, one at a time is too slow */
1437 GFP_ATOMIC);
1439 }
1441 /* use prefetched values */
1446 }
1456 }
1458 /**
1459 * e1000_consume_page - helper function
1460 **/
1462 u16 length)
1463 {
1468 }
1470 /**
1471 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1472 * @adapter: board private structure
1473 *
1474 * the return value indicates whether actual cleaning was done, there
1475 * is no guarantee that everything was cleaned
1476 **/
1479 {
1517 cleaned_count++;
1519 DMA_FROM_DEVICE);
1524 /* errors is only valid for DD + EOP descriptors */
1528 /* recycle both page and skb */
1530 /* an error means any chain goes out the window too */
1535 }
1536 #define rxtop (rx_ring->rx_skb_top)
1538 /* this descriptor is only the beginning (or middle) */
1540 /* this is the beginning of a chain */
1545 /* this is the middle of a chain */
1549 length);
1550 /* re-use the skb, only consumed the page */
1552 }
1557 /* end of the chain */
1561 length);
1562 /* re-use the current skb, we only consumed the
1563 * page
1564 */
1570 /* no chain, got EOP, this buf is the packet
1571 * copybreak to save the put_page/alloc_page
1572 */
1578 length);
1580 /* re-use the page, so don't erase
1581 * buffer_info->page
1582 */
1587 length);
1589 length);
1590 }
1591 }
1592 }
1594 /* Receive Checksum Offload */
1599 /* probably a little skewed due to removing CRC */
1601 total_rx_packets++;
1603 /* eth type trans needs skb->data to point to something */
1608 }
1613 next_desc:
1616 /* return some buffers to hardware, one at a time is too slow */
1619 GFP_ATOMIC);
1621 }
1623 /* use prefetched values */
1628 }
1638 }
1640 /**
1641 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1642 * @rx_ring: Rx descriptor ring
1643 **/
1645 {
1652 /* Free all the Rx ring sk_buffs */
1659 DMA_FROM_DEVICE);
1666 DMA_FROM_DEVICE);
1668 }
1673 }
1678 }
1685 DMA_FROM_DEVICE);
1689 }
1690 }
1692 /* there also may be some cached data from a chained receive */
1696 }
1698 /* Zero out the descriptor ring */
1708 else
1710 }
1713 {
1716 downshift_task);
1722 }
1724 /**
1725 * e1000_intr_msi - Interrupt Handler
1726 * @irq: interrupt number
1727 * @data: pointer to a network interface device structure
1728 **/
1730 {
1736 /* read ICR disables interrupts using IAM */
1739 /* ICH8 workaround-- Call gig speed drop workaround on cable
1740 * disconnect (LSC) before accessing any PHY registers
1741 */
1746 /* 80003ES2LAN workaround-- For packet buffer work-around on
1747 * link down event; disable receives here in the ISR and reset
1748 * adapter in watchdog
1749 */
1752 /* disable receives */
1756 }
1757 /* guard against interrupt when we're going down */
1760 }
1762 /* Reset on uncorrectable ECC error */
1770 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1772 /* Do the reset outside of interrupt context */
1775 /* return immediately since reset is imminent */
1777 }
1785 }
1788 }
1790 /**
1791 * e1000_intr - Interrupt Handler
1792 * @irq: interrupt number
1793 * @data: pointer to a network interface device structure
1794 **/
1796 {
1805 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1806 * not set, then the adapter didn't send an interrupt
1807 */
1811 /* Interrupt Auto-Mask...upon reading ICR,
1812 * interrupts are masked. No need for the
1813 * IMC write
1814 */
1818 /* ICH8 workaround-- Call gig speed drop workaround on cable
1819 * disconnect (LSC) before accessing any PHY registers
1820 */
1825 /* 80003ES2LAN workaround--
1826 * For packet buffer work-around on link down event;
1827 * disable receives here in the ISR and
1828 * reset adapter in watchdog
1829 */
1832 /* disable receives */
1836 }
1837 /* guard against interrupt when we're going down */
1840 }
1842 /* Reset on uncorrectable ECC error */
1850 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1852 /* Do the reset outside of interrupt context */
1855 /* return immediately since reset is imminent */
1857 }
1865 }
1868 }
1871 {
1881 }
1890 /* guard against interrupt when we're going down */
1893 }
1895 no_link_interrupt:
1900 }
1903 {
1913 /* Ring was not completely cleaned, so fire another interrupt */
1917 }
1920 {
1925 /* Write the ITR value calculated at the end of the
1926 * previous interrupt.
1927 */
1932 }
1938 }
1940 }
1942 /**
1943 * e1000_configure_msix - Configure MSI-X hardware
1944 *
1945 * e1000_configure_msix sets up the hardware to properly
1946 * generate MSI-X interrupts.
1947 **/
1949 {
1958 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1963 }
1965 /* Configure Rx vector */
1971 else
1975 /* Configure Tx vector */
1977 vector++;
1981 else
1986 /* set vector for Other Causes, e.g. link changes */
1987 vector++;
1992 else
1995 /* Cause Tx interrupts on every write back */
2000 /* enable MSI-X PBA support */
2004 /* Auto-Mask Other interrupts upon ICR read */
2009 }
2012 {
2020 }
2021 }
2023 /**
2024 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2025 *
2026 * Attempt to configure interrupts using the best available
2027 * capabilities of the hardware and kernel.
2028 **/
2030 {
2040 msix_entry),
2041 GFP_KERNEL);
2051 }
2052 /* MSI-X failed, so fall through and try MSI */
2055 }
2057 /* Fall through */
2064 }
2065 /* Fall through */
2067 /* Don't do anything; this is the system default */
2069 }
2071 /* store the number of vectors being used */
2073 }
2075 /**
2076 * e1000_request_msix - Initialize MSI-X interrupts
2077 *
2078 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2079 * kernel.
2080 **/
2082 {
2090 else
2094 netdev);
2100 vector++;
2106 else
2110 netdev);
2116 vector++;
2126 }
2128 /**
2129 * e1000_request_irq - initialize interrupts
2130 *
2131 * Attempts to configure interrupts using the best available
2132 * capabilities of the hardware and kernel.
2133 **/
2135 {
2143 /* fall back to MSI */
2147 }
2154 /* fall back to legacy interrupt */
2157 }
2165 }
2168 {
2175 vector++;
2178 vector++;
2180 /* Other Causes interrupt vector */
2183 }
2186 }
2188 /**
2189 * e1000_irq_disable - Mask off interrupt generation on the NIC
2190 **/
2192 {
2206 }
2207 }
2209 /**
2210 * e1000_irq_enable - Enable default interrupt generation settings
2211 **/
2213 {
2223 }
2225 }
2227 /**
2228 * e1000e_get_hw_control - get control of the h/w from f/w
2229 * @adapter: address of board private structure
2230 *
2231 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2232 * For ASF and Pass Through versions of f/w this means that
2233 * the driver is loaded. For AMT version (only with 82573)
2234 * of the f/w this means that the network i/f is open.
2235 **/
2237 {
2239 u32 ctrl_ext;
2240 u32 swsm;
2242 /* Let firmware know the driver has taken over */
2249 }
2250 }
2252 /**
2253 * e1000e_release_hw_control - release control of the h/w to f/w
2254 * @adapter: address of board private structure
2255 *
2256 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2257 * For ASF and Pass Through versions of f/w this means that the
2258 * driver is no longer loaded. For AMT version (only with 82573) i
2259 * of the f/w this means that the network i/f is closed.
2260 *
2261 **/
2263 {
2265 u32 ctrl_ext;
2266 u32 swsm;
2268 /* Let firmware taken over control of h/w */
2275 }
2276 }
2278 /**
2279 * e1000_alloc_ring_dma - allocate memory for a ring structure
2280 **/
2283 {
2287 GFP_KERNEL);
2292 }
2294 /**
2295 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2296 * @tx_ring: Tx descriptor ring
2297 *
2298 * Return 0 on success, negative on failure
2299 **/
2301 {
2310 /* round up to nearest 4K */
2322 err:
2326 }
2328 /**
2329 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2330 * @rx_ring: Rx descriptor ring
2331 *
2332 * Returns 0 on success, negative on failure
2333 **/
2335 {
2349 GFP_KERNEL);
2352 }
2356 /* Round up to nearest 4K */
2370 err_pages:
2374 }
2375 err:
2379 }
2381 /**
2382 * e1000_clean_tx_ring - Free Tx Buffers
2383 * @tx_ring: Tx descriptor ring
2384 **/
2386 {
2395 }
2409 else
2411 }
2413 /**
2414 * e1000e_free_tx_resources - Free Tx Resources per Queue
2415 * @tx_ring: Tx descriptor ring
2416 *
2417 * Free all transmit software resources
2418 **/
2420 {
2432 }
2434 /**
2435 * e1000e_free_rx_resources - Free Rx Resources
2436 * @rx_ring: Rx descriptor ring
2437 *
2438 * Free all receive software resources
2439 **/
2441 {
2457 }
2459 /**
2460 * e1000_update_itr - update the dynamic ITR value based on statistics
2461 * @adapter: pointer to adapter
2462 * @itr_setting: current adapter->itr
2463 * @packets: the number of packets during this measurement interval
2464 * @bytes: the number of bytes during this measurement interval
2465 *
2466 * Stores a new ITR value based on packets and byte
2467 * counts during the last interrupt. The advantage of per interrupt
2468 * computation is faster updates and more accurate ITR for the current
2469 * traffic pattern. Constants in this function were computed
2470 * based on theoretical maximum wire speed and thresholds were set based
2471 * on testing data as well as attempting to minimize response time
2472 * while increasing bulk throughput. This functionality is controlled
2473 * by the InterruptThrottleRate module parameter.
2474 **/
2476 {
2484 /* handle TSO and jumbo frames */
2492 /* this if handles the TSO accounting */
2503 }
2511 }
2513 }
2516 }
2519 {
2520 u16 current_itr;
2523 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2528 }
2533 }
2538 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2545 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2551 /* counts and packets in update_itr are dependent on these numbers */
2564 }
2566 set_itr_now:
2568 /* this attempts to bias the interrupt rate towards Bulk
2569 * by adding intermediate steps when interrupt rate is
2570 * increasing
2571 */
2578 else
2580 }
2581 }
2583 /**
2584 * e1000e_write_itr - write the ITR value to the appropriate registers
2585 * @adapter: address of board private structure
2586 * @itr: new ITR value to program
2587 *
2588 * e1000e_write_itr determines if the adapter is in MSI-X mode
2589 * and, if so, writes the EITR registers with the ITR value.
2590 * Otherwise, it writes the ITR value into the ITR register.
2591 **/
2593 {
2604 }
2605 }
2607 /**
2608 * e1000_alloc_queues - Allocate memory for all rings
2609 * @adapter: board private structure to initialize
2610 **/
2612 {
2628 err:
2633 }
2635 /**
2636 * e1000e_poll - NAPI Rx polling callback
2637 * @napi: struct associated with this polling callback
2638 * @weight: number of packets driver is allowed to process this poll
2639 **/
2641 {
2643 napi);
2659 /* If weight not fully consumed, exit the polling mode */
2667 else
2669 }
2670 }
2673 }
2677 {
2682 /* don't update vlan cookie if already programmed */
2684 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2688 /* add VID to filter table */
2694 }
2699 }
2703 {
2709 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2711 /* release control to f/w */
2714 }
2716 /* remove VID from filter table */
2722 }
2727 }
2729 /**
2730 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2731 * @adapter: board private structure to initialize
2732 **/
2734 {
2737 u32 rctl;
2740 /* disable VLAN receive filtering */
2749 }
2750 }
2751 }
2753 /**
2754 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2755 * @adapter: board private structure to initialize
2756 **/
2758 {
2760 u32 rctl;
2763 /* enable VLAN receive filtering */
2768 }
2769 }
2771 /**
2772 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2773 * @adapter: board private structure to initialize
2774 **/
2776 {
2778 u32 ctrl;
2780 /* disable VLAN tag insert/strip */
2784 }
2786 /**
2787 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2788 * @adapter: board private structure to initialize
2789 **/
2791 {
2793 u32 ctrl;
2795 /* enable VLAN tag insert/strip */
2799 }
2802 {
2810 }
2814 }
2817 {
2818 u16 vid;
2824 }
2827 {
2836 /* enable receiving management packets to the host. this will probably
2837 * generate destination unreachable messages from the host OS, but
2838 * the packets will be handled on SMBUS
2839 */
2849 /* Check if IPMI pass-through decision filter already exists;
2850 * if so, enable it.
2851 */
2855 /* Ignore filters with anything other than IPMI ports */
2859 /* Enable this decision filter in MANC2H */
2864 }
2869 /* Create new decision filter in an empty filter */
2873 E1000_MDEF_PORT_664));
2875 j++;
2877 }
2882 }
2886 }
2888 /**
2889 * e1000_configure_tx - Configure Transmit Unit after Reset
2890 * @adapter: board private structure
2891 *
2892 * Configure the Tx unit of the MAC after a reset.
2893 **/
2895 {
2898 u64 tdba;
2901 /* Setup the HW Tx Head and Tail descriptor pointers */
2912 /* Set the Tx Interrupt Delay register */
2914 /* Tx irq moderation */
2920 E1000_TXDCTL_WTHRESH);
2921 /* set up some performance related parameters to encourage the
2922 * hardware to use the bus more efficiently in bursts, depends
2923 * on the tx_int_delay to be enabled,
2924 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2925 * hthresh = 1 ==> prefetch when one or more available
2926 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2927 * BEWARE: this seems to work but should be considered first if
2928 * there are Tx hangs or other Tx related bugs
2929 */
2932 }
2933 /* erratum work around: set txdctl the same for both queues */
2938 /* set the speed mode bit, we'll clear it if we're not at
2939 * gigabit link later
2940 */
2941 #define SPEED_MODE_BIT (1 << 21)
2944 }
2946 /* errata: program both queues to unweighted RR */
2954 }
2956 /* Setup Transmit Descriptor Settings for eop descriptor */
2959 /* only set IDE if we are delaying interrupts using the timers */
2963 /* enable Report Status bit */
2967 }
2969 /**
2970 * e1000_setup_rctl - configure the receive control registers
2971 * @adapter: Board private structure
2972 **/
2973 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2974 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2976 {
2981 /* Workaround Si errata on PCHx - configure jumbo frame flow */
2983 s32 ret_val;
2987 else
2992 }
2994 /* Program MC offset vector base */
3001 /* Do not Store bad packets */
3004 /* Enable Long Packet receive */
3007 else
3010 /* Some systems expect that the CRC is included in SMBUS traffic. The
3011 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3012 * host memory when this is enabled
3013 */
3017 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3019 u16 phy_data;
3032 }
3034 /* Setup buffer sizes */
3052 }
3054 /* Enable Extended Status in all Receive Descriptors */
3059 /* 82571 and greater support packet-split where the protocol
3060 * header is placed in skb->data and the packet data is
3061 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3062 * In the case of a non-split, skb->data is linearly filled,
3063 * followed by the page buffers. Therefore, skb->data is
3064 * sized to hold the largest protocol header.
3065 *
3066 * allocations using alloc_page take too long for regular MTU
3067 * so only enable packet split for jumbo frames
3068 *
3069 * Using pages when the page size is greater than 16k wastes
3070 * a lot of memory, since we allocate 3 pages at all times
3071 * per packet.
3072 */
3076 else
3082 /* Enable Packet split descriptors */
3090 /* fall-through */
3093 /* fall-through */
3097 }
3100 }
3102 /* This is useful for sniffing bad packets. */
3104 /* UPE and MPE will be handled by normal PROMISC logic
3105 * in e1000e_set_rx_mode
3106 */
3114 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3115 * and that breaks VLANs.
3116 */
3117 }
3120 /* just started the receive unit, no need to restart */
3122 }
3124 /**
3125 * e1000_configure_rx - Configure Receive Unit after Reset
3126 * @adapter: board private structure
3127 *
3128 * Configure the Rx unit of the MAC after a reset.
3129 **/
3131 {
3134 u64 rdba;
3138 /* this is a 32 byte descriptor */
3151 }
3153 /* disable receives while setting up the descriptors */
3161 /* set the writeback threshold (only takes effect if the RDTR
3162 * is set). set GRAN=1 and write back up to 0x4 worth, and
3163 * enable prefetching of 0x20 Rx descriptors
3164 * granularity = 01
3165 * wthresh = 04,
3166 * hthresh = 04,
3167 * pthresh = 0x20
3168 */
3172 /* override the delay timers for enabling bursting, only if
3173 * the value was not set by the user via module options
3174 */
3179 }
3181 /* set the Receive Delay Timer Register */
3184 /* irq moderation */
3190 /* Auto-Mask interrupts upon ICR access */
3196 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3197 * the Base and Length of the Rx Descriptor Ring
3198 */
3208 /* Enable Receive Checksum Offload for TCP and UDP */
3212 else
3216 /* With jumbo frames, excessive C-state transition latencies result
3217 * in dropped transactions.
3218 */
3220 u32 lat =
3227 }
3232 PM_QOS_DEFAULT_VALUE);
3233 }
3235 /* Enable Receives */
3237 }
3239 /**
3240 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3241 * @netdev: network interface device structure
3242 *
3243 * Writes multicast address list to the MTA hash table.
3244 * Returns: -ENOMEM on failure
3245 * 0 on no addresses written
3246 * X on writing X addresses to MTA
3247 */
3249 {
3257 /* nothing to program, so clear mc list */
3260 }
3266 /* update_mc_addr_list expects a packed array of only addresses. */
3275 }
3277 /**
3278 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3279 * @netdev: network interface device structure
3280 *
3281 * Writes unicast address list to the RAR table.
3282 * Returns: -ENOMEM on failure/insufficient address space
3283 * 0 on no addresses written
3284 * X on writing X addresses to the RAR table
3285 **/
3287 {
3293 /* save a rar entry for our hardware address */
3294 rar_entries--;
3296 /* save a rar entry for the LAA workaround */
3298 rar_entries--;
3300 /* return ENOMEM indicating insufficient memory for addresses */
3307 /* write the addresses in reverse order to avoid write
3308 * combining
3309 */
3314 count++;
3315 }
3316 }
3318 /* zero out the remaining RAR entries not used above */
3322 }
3326 }
3328 /**
3329 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3330 * @netdev: network interface device structure
3331 *
3332 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3333 * address list or the network interface flags are updated. This routine is
3334 * responsible for configuring the hardware for proper unicast, multicast,
3335 * promiscuous mode, and all-multi behavior.
3336 **/
3338 {
3341 u32 rctl;
3343 /* Check for Promiscuous and All Multicast modes */
3346 /* clear the affected bits */
3351 /* Do not hardware filter VLANs in promisc mode */
3359 /* Write addresses to the MTA, if the attempt fails
3360 * then we should just turn on promiscuous mode so
3361 * that we can at least receive multicast traffic
3362 */
3366 }
3368 /* Write addresses to available RAR registers, if there is not
3369 * sufficient space to store all the addresses then enable
3370 * unicast promiscuous mode
3371 */
3375 }
3381 else
3383 }
3386 {
3393 };
3395 /* Fill out hash function seed */
3399 /* Direct all traffic to queue 0 */
3403 /* Disable raw packet checksumming so that RSS hash is placed in
3404 * descriptor on writeback.
3405 */
3412 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3413 E1000_MRQC_RSS_FIELD_IPV6 |
3414 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3415 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3418 }
3420 /**
3421 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3422 * @adapter: board private structure
3423 * @timinca: pointer to returned time increment attributes
3424 *
3425 * Get attributes for incrementing the System Time Register SYSTIML/H at
3426 * the default base frequency, and set the cyclecounter shift value.
3427 **/
3429 {
3433 /* Make sure clock is enabled on I217 before checking the frequency */
3442 }
3443 }
3448 /* On I217, the clock frequency is 25MHz or 96MHz as
3449 * indicated by the System Clock Frequency Indication
3450 */
3453 /* Stable 96MHz frequency */
3459 }
3460 /* fall-through */
3463 /* Stable 25MHz frequency */
3471 }
3477 }
3479 /**
3480 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3481 * @adapter: board private structure
3482 *
3483 * Outgoing time stamping can be enabled and disabled. Play nice and
3484 * disable it when requested, although it shouldn't cause any overhead
3485 * when no packet needs it. At most one packet in the queue may be
3486 * marked for time stamping, otherwise it would be impossible to tell
3487 * for sure to which packet the hardware time stamp belongs.
3488 *
3489 * Incoming time stamping has to be configured via the hardware filters.
3490 * Not all combinations are supported, in particular event type has to be
3491 * specified. Matching the kind of event packet is not supported, with the
3492 * exception of "all V2 events regardless of level 2 or 4".
3493 **/
3495 {
3504 u32 regval;
3505 s32 ret_val;
3510 /* flags reserved for future extensions - must be zero */
3522 }
3539 /* Also time stamps V2 L2 Path Delay Request/Response */
3545 /* Also time stamps V2 L2 Path Delay Request/Response. */
3551 /* Hardware cannot filter just V2 L4 Sync messages;
3552 * fall-through to V2 (both L2 and L4) Sync.
3553 */
3555 /* Also time stamps V2 Path Delay Request/Response. */
3562 /* Hardware cannot filter just V2 L4 Delay Request messages;
3563 * fall-through to V2 (both L2 and L4) Delay Request.
3564 */
3566 /* Also time stamps V2 Path Delay Request/Response. */
3574 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3575 * fall-through to all V2 (both L2 and L4) Events.
3576 */
3584 /* For V1, the hardware can only filter Sync messages or
3585 * Delay Request messages but not both so fall-through to
3586 * time stamp all packets.
3587 */
3596 }
3598 /* enable/disable Tx h/w time stamping */
3607 }
3609 /* enable/disable Rx h/w time stamping */
3615 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3617 E1000_TSYNCRXCTL_TYPE_MASK))) {
3620 }
3622 /* L2: define ethertype filter for time stamped packets */
3626 /* define which PTP packets get time stamped */
3629 /* Filter by destination port */
3633 }
3638 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3642 /* Get and set the System Time Register SYSTIM base frequency */
3648 /* reset the ns time counter */
3653 }
3655 /**
3656 * e1000_configure - configure the hardware for Rx and Tx
3657 * @adapter: private board structure
3658 **/
3660 {
3675 }
3677 /**
3678 * e1000e_power_up_phy - restore link in case the phy was powered down
3679 * @adapter: address of board private structure
3680 *
3681 * The phy may be powered down to save power and turn off link when the
3682 * driver is unloaded and wake on lan is not enabled (among others)
3683 * *** this routine MUST be followed by a call to e1000e_reset ***
3684 **/
3686 {
3691 }
3693 /**
3694 * e1000_power_down_phy - Power down the PHY
3695 *
3696 * Power down the PHY so no link is implied when interface is down.
3697 * The PHY cannot be powered down if management or WoL is active.
3698 */
3700 {
3701 /* WoL is enabled */
3707 }
3709 /**
3710 * e1000e_reset - bring the hardware into a known good state
3711 *
3712 * This function boots the hardware and enables some settings that
3713 * require a configuration cycle of the hardware - those cannot be
3714 * set/changed during runtime. After reset the device needs to be
3715 * properly configured for Rx, Tx etc.
3716 */
3718 {
3724 u16 hwm;
3726 /* reset Packet Buffer Allocation to default */
3730 /* To maintain wire speed transmits, the Tx FIFO should be
3731 * large enough to accommodate two full transmit packets,
3732 * rounded up to the next 1KB and expressed in KB. Likewise,
3733 * the Rx FIFO should be large enough to accommodate at least
3734 * one full receive packet and is similarly rounded up and
3735 * expressed in KB.
3736 */
3738 /* upper 16 bits has Tx packet buffer allocation size in KB */
3740 /* lower 16 bits has Rx packet buffer allocation size in KB */
3742 /* the Tx fifo also stores 16 bytes of information about the Tx
3743 * but don't include ethernet FCS because hardware appends it
3744 */
3749 /* software strips receive CRC, so leave room for it */
3754 /* If current Tx allocation is less than the min Tx FIFO size,
3755 * and the min Tx FIFO size is less than the current Rx FIFO
3756 * allocation, take space away from current Rx allocation
3757 */
3762 /* if short on Rx space, Rx wins and must trump Tx
3763 * adjustment
3764 */
3767 }
3770 }
3772 /* flow control settings
3773 *
3774 * The high water mark must be low enough to fit one full frame
3775 * (or the size used for early receive) above it in the Rx FIFO.
3776 * Set it to the lower of:
3777 * - 90% of the Rx FIFO size, and
3778 * - the full Rx FIFO size minus one full frame
3779 */
3782 else
3796 }
3797 /* fall-through */
3806 /* Workaround PCH LOM adapter hangs with certain network
3807 * loads. If hangs persist, try disabling Tx flow control.
3808 */
3815 }
3827 }
3832 }
3834 /* Alignment of Tx data is on an arbitrary byte boundary with the
3835 * maximum size per Tx descriptor limited only to the transmit
3836 * allocation of the packet buffer minus 96 bytes with an upper
3837 * limit of 24KB due to receive synchronization limitations.
3838 */
3842 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
3843 * fit in receive buffer.
3844 */
3852 }
3859 }
3860 }
3862 /* Allow time for pending master requests to run */
3865 /* For parts with AMT enabled, let the firmware know
3866 * that the network interface is in control
3867 */
3878 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3883 /* initialize systim and reset the ns time counter */
3886 /* Set EEE advertisement as appropriate */
3888 s32 ret_val;
3889 u16 adv_addr;
3902 }
3909 }
3916 }
3922 }
3929 /* speed up time to link by disabling smart power down, ignore
3930 * the return value of this function because there is nothing
3931 * different we would do if it failed
3932 */
3936 }
3937 }
3940 {
3943 /* hardware has been reset, we need to reload some things */
3954 /* fire a link change interrupt to start the watchdog */
3957 else
3961 }
3964 {
3970 /* flush pending descriptor writebacks to memory */
3974 /* execute the writes immediately */
3977 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
3978 * write is successful
3979 */
3983 /* execute the writes immediately */
3985 }
3990 {
3995 /* signal that we're down so the interrupt handler does not
3996 * reschedule our watchdog timer
3997 */
4000 /* disable receives in the hardware */
4004 /* flush and sleep below */
4008 /* disable transmits in the hardware */
4013 /* flush both disables and wait for them to finish */
4040 /* TODO: for power management, we could drop the link and
4041 * pci_disable_device here.
4042 */
4043 }
4046 {
4053 }
4055 /**
4056 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4057 * @cc: cyclecounter structure
4058 **/
4060 {
4062 cc);
4064 cycle_t systim;
4066 /* latch SYSTIMH on read of SYSTIML */
4071 }
4073 /**
4074 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4075 * @adapter: board private structure to initialize
4076 *
4077 * e1000_sw_init initializes the Adapter private data structure.
4078 * Fields are initialized based on PCI device information and
4079 * OS network device settings (MTU size).
4080 **/
4082 {
4099 /* Setup hardware time stamping cyclecounter */
4104 /* cc.shift set in e1000e_get_base_tininca() */
4108 }
4110 /* Explicitly disable IRQ since the NIC can be in any state. */
4115 }
4117 /**
4118 * e1000_intr_msi_test - Interrupt Handler
4119 * @irq: interrupt number
4120 * @data: pointer to a network interface device structure
4121 **/
4123 {
4132 /* Force memory writes to complete before acknowledging the
4133 * interrupt is handled.
4134 */
4136 }
4139 }
4141 /**
4142 * e1000_test_msi_interrupt - Returns 0 for successful test
4143 * @adapter: board private struct
4144 *
4145 * code flow taken from tg3.c
4146 **/
4148 {
4153 /* poll_enable hasn't been called yet, so don't need disable */
4154 /* clear any pending events */
4157 /* free the real vector and request a test handler */
4161 /* Assume that the test fails, if it succeeds then the test
4162 * MSI irq handler will unset this flag
4163 */
4175 }
4177 /* Force memory writes to complete before enabling and firing an
4178 * interrupt.
4179 */
4184 /* fire an unusual interrupt on the test handler */
4198 }
4203 msi_test_failed:
4206 }
4208 /**
4209 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4210 * @adapter: board private struct
4211 *
4212 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4213 **/
4215 {
4217 u16 pci_cmd;
4222 /* disable SERR in case the MSI write causes a master abort */
4230 /* re-enable SERR */
4235 }
4238 }
4240 /**
4241 * e1000_open - Called when a network interface is made active
4242 * @netdev: network interface device structure
4243 *
4244 * Returns 0 on success, negative value on failure
4245 *
4246 * The open entry point is called when a network interface is made
4247 * active by the system (IFF_UP). At this point all resources needed
4248 * for transmit and receive operations are allocated, the interrupt
4249 * handler is registered with the OS, the watchdog timer is started,
4250 * and the stack is notified that the interface is ready.
4251 **/
4253 {
4259 /* disallow open during test */
4267 /* allocate transmit descriptors */
4272 /* allocate receive descriptors */
4277 /* If AMT is enabled, let the firmware know that the network
4278 * interface is now open and reset the part to a known state.
4279 */
4283 }
4291 /* DMA latency requirement to workaround jumbo issue */
4293 PM_QOS_DEFAULT_VALUE);
4295 /* before we allocate an interrupt, we must be ready to handle it.
4296 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4297 * as soon as we call pci_request_irq, so we have to setup our
4298 * clean_rx handler before we do so.
4299 */
4306 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4307 * ignore e1000e MSI messages, which means we need to test our MSI
4308 * interrupt now
4309 */
4315 }
4316 }
4318 /* From here on the code is the same as e1000e_up() */
4332 /* fire a link status change interrupt to start the watchdog */
4335 else
4340 err_req_irq:
4344 err_setup_rx:
4346 err_setup_tx:
4351 }
4353 /**
4354 * e1000_close - Disables a network interface
4355 * @netdev: network interface device structure
4356 *
4357 * Returns 0, this is not allowed to fail
4358 *
4359 * The close entry point is called when an interface is de-activated
4360 * by the OS. The hardware is still under the drivers control, but
4361 * needs to be disabled. A global MAC reset is issued to stop the
4362 * hardware, and all transmit and receive resources are freed.
4363 **/
4365 {
4380 }
4389 /* kill manageability vlan ID if supported, but not if a vlan with
4390 * the same ID is registered on the host OS (let 8021q kill it)
4391 */
4396 /* If AMT is enabled, let the firmware know that the network
4397 * interface is now closed
4398 */
4408 }
4410 /**
4411 * e1000_set_mac - Change the Ethernet Address of the NIC
4412 * @netdev: network interface device structure
4413 * @p: pointer to an address structure
4414 *
4415 * Returns 0 on success, negative on failure
4416 **/
4418 {
4432 /* activate the work around */
4435 /* Hold a copy of the LAA in RAR[14] This is done so that
4436 * between the time RAR[0] gets clobbered and the time it
4437 * gets fixed (in e1000_watchdog), the actual LAA is in one
4438 * of the RARs and no incoming packets directed to this port
4439 * are dropped. Eventually the LAA will be in RAR[0] and
4440 * RAR[14]
4441 */
4444 }
4447 }
4449 /**
4450 * e1000e_update_phy_task - work thread to update phy
4451 * @work: pointer to our work struct
4452 *
4453 * this worker thread exists because we must acquire a
4454 * semaphore to read the phy, which we could msleep while
4455 * waiting for it, and we can't msleep in a timer.
4456 **/
4458 {
4461 update_phy_task);
4467 }
4469 /**
4470 * e1000_update_phy_info - timre call-back to update PHY info
4471 * @data: pointer to adapter cast into an unsigned long
4472 *
4473 * Need to wait a few seconds after link up to get diagnostic information from
4474 * the phy
4475 **/
4477 {
4484 }
4486 /**
4487 * e1000e_update_phy_stats - Update the PHY statistics counters
4488 * @adapter: board private structure
4489 *
4490 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4491 **/
4493 {
4495 s32 ret_val;
4496 u16 phy_data;
4502 /* A page set is expensive so check if already on desired page.
4503 * If not, set to the page with the PHY status registers.
4504 */
4515 }
4517 /* Single Collision Count */
4523 /* Excessive Collision Count */
4529 /* Multiple Collision Count */
4535 /* Late Collision Count */
4541 /* Collision Count - also used for adaptive IFS */
4547 /* Defer Count */
4553 /* Transmit with no CRS */
4559 release:
4561 }
4563 /**
4564 * e1000e_update_stats - Update the board statistics counters
4565 * @adapter: board private structure
4566 **/
4568 {
4573 /* Prevent stats update while adapter is being reset, or if the pci
4574 * connection is down.
4575 */
4591 /* Half-duplex statistics */
4607 }
4609 }
4624 /* used for adaptive IFS */
4635 /* Fill out the OS statistics structure */
4639 /* Rx Errors */
4641 /* RLEC on some newer hardware can be incorrect so build
4642 * our own version based on RUC and ROC
4643 */
4653 /* Tx Errors */
4659 /* Tx Dropped needs to be maintained elsewhere */
4661 /* Management Stats */
4666 /* Correctable ECC Errors */
4673 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4674 }
4675 }
4677 /**
4678 * e1000_phy_read_status - Update the PHY register status snapshot
4679 * @adapter: board private structure
4680 **/
4682 {
4703 /* Do not read PHY registers if link is not up
4704 * Set values to typical power-on defaults
4705 */
4709 BMSR_ERCAP);
4717 }
4718 }
4721 {
4725 /* Link status message must follow this format for user tools */
4732 }
4735 {
4740 /* get_link_status is set on LSC (link status) interrupt or
4741 * Rx sequence error interrupt. get_link_status will stay
4742 * false until the check_for_link establishes link
4743 * for copper adapters ONLY
4744 */
4752 }
4765 }
4769 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
4771 }
4774 }
4777 {
4778 /* make sure the receive unit is started */
4785 }
4786 }
4789 {
4792 /* With 82574 controllers, PHY needs to be checked periodically
4793 * for hung state and reset, if two calls return true
4794 */
4797 else
4803 }
4804 }
4806 /**
4807 * e1000_watchdog - Timer Call-back
4808 * @data: pointer to adapter cast into an unsigned long
4809 **/
4811 {
4814 /* Do the rest outside of interrupt context */
4817 /* TODO: make this use queue_delayed_work() */
4818 }
4821 {
4824 watchdog_task);
4837 /* Cancel scheduled suspend requests. */
4842 }
4852 /* Cancel scheduled suspend requests. */
4855 /* update snapshot of PHY registers on LSC */
4862 /* check if SmartSpeed worked */
4868 /* On supported PHYs, check for duplex mismatch only
4869 * if link has autonegotiated at 10/100 half
4870 */
4877 u16 autoneg_exp;
4882 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
4883 }
4885 /* adjust timeout factor according to speed/duplex */
4896 }
4898 /* workaround: re-program speed mode bit after
4899 * link-up event
4900 */
4903 u32 tarc0;
4907 }
4909 /* disable TSO for pcie and 10/100 speeds, to avoid
4910 * some hardware issues
4911 */
4925 /* oops */
4927 }
4928 }
4930 /* enable transmits in the hardware, need to do this
4931 * after setting TARC(0)
4932 */
4937 /* Perform any post-link-up configuration before
4938 * reporting link up.
4939 */
4948 }
4953 /* Link status message must follow this format */
4960 /* The link is lost so the controller stops DMA.
4961 * If there is queued Tx work that cannot be done
4962 * or if on an 8000ES2LAN which requires a Rx packet
4963 * buffer work-around on link down event, reset the
4964 * controller to flush the Tx/Rx packet buffers.
4965 * (Do the reset outside of interrupt context).
4966 */
4970 else
4972 LINK_TIMEOUT);
4973 }
4974 }
4976 link_up:
4993 /* return immediately since reset is imminent */
4995 }
4999 /* Simple mode for Interrupt Throttle Rate (ITR) */
5001 /* Symmetric Tx/Rx gets a reduced ITR=2000;
5002 * Total asymmetrical Tx or Rx gets ITR=8000;
5003 * everyone else is between 2000-8000.
5004 */
5012 }
5014 /* Cause software interrupt to ensure Rx ring is cleaned */
5017 else
5020 /* flush pending descriptors to memory before detecting Tx hang */
5023 /* Force detection of hung controller every watchdog period */
5026 /* With 82571 controllers, LAA may be overwritten due to controller
5027 * reset from the other port. Set the appropriate LAA in RAR[0]
5028 */
5035 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5043 }
5044 }
5046 /* Reset the timer */
5050 }
5052 #define E1000_TX_FLAGS_CSUM 0x00000001
5053 #define E1000_TX_FLAGS_VLAN 0x00000002
5054 #define E1000_TX_FLAGS_TSO 0x00000004
5055 #define E1000_TX_FLAGS_IPV4 0x00000008
5056 #define E1000_TX_FLAGS_NO_FCS 0x00000010
5057 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5058 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5059 #define E1000_TX_FLAGS_VLAN_SHIFT 16
5062 {
5078 }
5096 }
5122 i++;
5128 }
5131 {
5136 u8 css;
5138 __be16 protocol;
5145 else
5154 /* XXX not handling all IPV6 headers */
5163 }
5181 i++;
5187 }
5192 {
5218 count++;
5221 i++;
5224 }
5225 }
5235 i++;
5247 DMA_TO_DEVICE);
5254 count++;
5255 }
5256 }
5259 /* multiply data chunks by size of headers */
5269 dma_error:
5273 count--;
5278 i--;
5281 }
5284 }
5287 {
5296 E1000_TXD_CMD_TSE;
5301 }
5306 }
5311 }
5319 }
5331 i++;
5338 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5342 /* Force memory writes to complete before letting h/w
5343 * know there are new descriptors to fetch. (Only
5344 * applicable for weak-ordered memory model archs,
5345 * such as IA-64).
5346 */
5353 else
5356 /* we need this if more than one processor can write to our tail
5357 * at a time, it synchronizes IO on IA64/Altix systems
5358 */
5360 }
5362 #define MINIMUM_DHCP_PACKET_SIZE 282
5365 {
5372 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5381 {
5395 }
5398 }
5401 {
5405 /* Herbert's original patch had:
5406 * smp_mb__after_netif_stop_queue();
5407 * but since that doesn't exist yet, just open code it.
5408 */
5411 /* We need to check again in a case another CPU has just
5412 * made room available.
5413 */
5417 /* A reprieve! */
5421 }
5424 {
5430 }
5434 {
5449 }
5454 }
5456 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5457 * pad skb in order to meet this minimum size requirement
5458 */
5464 }
5468 u8 hdr_len;
5470 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5471 * points to just header, pull a few bytes of payload from
5472 * frags into skb->data
5473 */
5475 /* we do this workaround for ES2LAN, but it is un-necessary,
5476 * avoiding it could save a lot of cycles
5477 */
5486 }
5488 }
5489 }
5491 /* reserve a descriptor for the offload context */
5493 count++;
5494 count++;
5506 /* need: count + 2 desc gap to keep tail from touching
5507 * head, otherwise try next time
5508 */
5515 }
5523 }
5530 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5531 * 82571 hardware supports TSO capabilities for IPv6 as well...
5532 * no longer assume, we must.
5533 */
5540 /* if count is 0 then mapping error has occurred */
5542 nr_frags);
5552 }
5556 /* Make sure there is space in the ring for the next send. */
5565 }
5568 }
5570 /**
5571 * e1000_tx_timeout - Respond to a Tx Hang
5572 * @netdev: network interface device structure
5573 **/
5575 {
5578 /* Do the reset outside of interrupt context */
5581 }
5584 {
5588 /* don't run the task if already down */
5595 }
5597 }
5599 /**
5600 * e1000_get_stats64 - Get System Network Statistics
5601 * @netdev: network interface device structure
5602 * @stats: rtnl_link_stats64 pointer
5603 *
5604 * Returns the address of the device statistics structure.
5605 **/
5608 {
5614 /* Fill out the OS statistics structure */
5622 /* Rx Errors */
5624 /* RLEC on some newer hardware can be incorrect so build
5625 * our own version based on RUC and ROC
5626 */
5635 /* Tx Errors */
5641 /* Tx Dropped needs to be maintained elsewhere */
5645 }
5647 /**
5648 * e1000_change_mtu - Change the Maximum Transfer Unit
5649 * @netdev: network interface device structure
5650 * @new_mtu: new value for maximum frame size
5651 *
5652 * Returns 0 on success, negative on failure
5653 **/
5655 {
5659 /* Jumbo frame support */
5664 }
5666 /* Supported frame sizes */
5671 }
5673 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5679 }
5683 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
5690 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
5691 * means we reserve 2 more, this pushes us to allocate from the next
5692 * larger slab size.
5693 * i.e. RXBUFFER_2048 --> size-4096 slab
5694 * However with the new *_jumbo_rx* routines, jumbo receives will use
5695 * fragmented skbs
5696 */
5700 else
5703 /* adjust allocation if LPE protects us, and we aren't using SBP */
5711 else
5717 }
5721 {
5768 }
5773 }
5775 }
5777 /**
5778 * e1000e_hwtstamp_ioctl - control hardware time stamping
5779 * @netdev: network interface device structure
5780 * @ifreq: interface request
5781 *
5782 * Outgoing time stamping can be enabled and disabled. Play nice and
5783 * disable it when requested, although it shouldn't cause any overhead
5784 * when no packet needs it. At most one packet in the queue may be
5785 * marked for time stamping, otherwise it would be impossible to tell
5786 * for sure to which packet the hardware time stamp belongs.
5787 *
5788 * Incoming time stamping has to be configured via the hardware filters.
5789 * Not all combinations are supported, in particular event type has to be
5790 * specified. Matching the kind of event packet is not supported, with the
5791 * exception of "all V2 events regardless of level 2 or 4".
5792 **/
5794 {
5817 /* With V2 type filters which specify a Sync or Delay Request,
5818 * Path Delay Request/Response messages are also time stamped
5819 * by hardware so notify the caller the requested packets plus
5820 * some others are time stamped.
5821 */
5826 }
5830 }
5833 {
5843 }
5844 }
5847 {
5853 /* copy MAC RARs to PHY RARs */
5860 }
5862 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5867 /* copy MAC MTA to PHY MTA - only needed for pchlan */
5874 }
5876 /* configure PHY Rx Control register */
5896 /* enable PHY wakeup in MAC register */
5900 /* configure and enable PHY wakeup in PHY registers */
5904 /* activate PHY wakeup */
5909 release:
5913 }
5916 {
5921 /* Runtime suspend should only enable wakeup for link changes */
5936 }
5947 /* turn on all-multi mode if wake on multicast is enabled */
5952 }
5962 e1000_media_type_internal_serdes) {
5963 /* keep the laser running in D3 */
5967 }
5972 /* Allow time for pending master requests to run */
5976 /* enable wakeup by the PHY */
5981 /* enable wakeup by the MAC */
5984 }
5988 }
5993 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5994 * would have already happened in close and is redundant.
5995 */
5998 /* The pci-e switch on some quad port adapters will report a
5999 * correctable error when the MAC transitions from D0 to D3. To
6000 * prevent this we need to mask off the correctable errors on the
6001 * downstream port of the pci-e switch.
6002 */
6005 u16 devctl;
6015 }
6018 }
6020 #ifdef CONFIG_PCIEASPM
6022 {
6024 }
6025 #else
6027 {
6035 /* Both device and parent should have the same ASPM setting.
6036 * Disable ASPM in downstream component first and then upstream.
6037 */
6042 aspm_ctl);
6043 }
6044 #endif
6046 {
6052 }
6054 #ifdef CONFIG_PM
6056 {
6058 }
6061 {
6066 u32 err;
6082 }
6089 /* report the system wakeup cause from S3/S4 */
6091 u16 phy_data;
6102 }
6114 }
6116 }
6127 /* If the controller has AMT, do not set DRV_LOAD until the interface
6128 * is up. For all other cases, let the f/w know that the h/w is now
6129 * under the control of the driver.
6130 */
6135 }
6137 #ifdef CONFIG_PM_SLEEP
6139 {
6143 }
6146 {
6155 }
6158 #ifdef CONFIG_PM_RUNTIME
6160 {
6169 }
6172 {
6184 }
6187 }
6190 {
6200 }
6205 {
6207 }
6209 #ifdef CONFIG_NET_POLL_CONTROLLER
6212 {
6225 vector++;
6231 vector++;
6236 }
6239 }
6241 /**
6242 * e1000_netpoll
6243 * @netdev: network interface device structure
6244 *
6245 * Polling 'interrupt' - used by things like netconsole to send skbs
6246 * without having to re-enable interrupts. It's not called while
6247 * the interrupt routine is executing.
6248 */
6250 {
6267 }
6268 }
6269 #endif
6271 /**
6272 * e1000_io_error_detected - called when PCI error is detected
6273 * @pdev: Pointer to PCI device
6274 * @state: The current pci connection state
6275 *
6276 * This function is called after a PCI bus error affecting
6277 * this device has been detected.
6278 */
6280 pci_channel_state_t state)
6281 {
6294 /* Request a slot slot reset. */
6296 }
6298 /**
6299 * e1000_io_slot_reset - called after the pci bus has been reset.
6300 * @pdev: Pointer to PCI device
6301 *
6302 * Restart the card from scratch, as if from a cold-boot. Implementation
6303 * resembles the first-half of the e1000_resume routine.
6304 */
6306 {
6312 pci_ers_result_t result;
6337 }
6342 }
6344 /**
6345 * e1000_io_resume - called when traffic can start flowing again.
6346 * @pdev: Pointer to PCI device
6347 *
6348 * This callback is called when the error recovery driver tells us that
6349 * its OK to resume normal operation. Implementation resembles the
6350 * second-half of the e1000_resume routine.
6351 */
6353 {
6364 }
6365 }
6369 /* If the controller has AMT, do not set DRV_LOAD until the interface
6370 * is up. For all other cases, let the f/w know that the h/w is now
6371 * under the control of the driver.
6372 */
6375 }
6378 {
6381 u32 ret_val;
6384 /* print bus type/speed/width info */
6386 /* bus width */
6389 /* MAC address */
6394 E1000_PBANUM_LENGTH);
6399 }
6402 {
6413 /* Deep Smart Power Down (DSPD) */
6416 }
6417 }
6420 netdev_features_t features)
6421 {
6430 NETIF_F_RXALL)))
6437 /* We need to take it back to defaults, which might mean
6438 * stripping is still disabled at the adapter level.
6439 */
6442 else
6444 }
6445 }
6451 else
6455 }
6471 #ifdef CONFIG_NET_POLL_CONTROLLER
6473 #endif
6475 };
6477 /**
6478 * e1000_probe - Device Initialization Routine
6479 * @pdev: PCI device information struct
6480 * @ent: entry in e1000_pci_tbl
6481 *
6482 * Returns 0 on success, negative on failure
6483 *
6484 * e1000_probe initializes an adapter identified by a pci_dev structure.
6485 * The OS initialization, configuring of the adapter private structure,
6486 * and a hardware reset occur.
6487 **/
6489 {
6528 }
6529 }
6530 }
6534 e1000e_driver_name);
6538 /* AER (Advanced Error Reporting) hooks */
6542 /* PCI config space info */
6585 }
6587 /* Set default EEE advertisement */
6591 /* construct the net_device struct */
6605 /* setup adapter struct */
6626 /* Copper options */
6631 }
6637 /* Set initial default active device features */
6639 NETIF_F_HW_VLAN_CTAG_RX |
6640 NETIF_F_HW_VLAN_CTAG_TX |
6641 NETIF_F_TSO |
6642 NETIF_F_TSO6 |
6643 NETIF_F_RXHASH |
6644 NETIF_F_RXCSUM |
6645 NETIF_F_HW_CSUM);
6647 /* Set user-changeable features (subset of all device features) */
6657 NETIF_F_TSO |
6658 NETIF_F_TSO6 |
6659 NETIF_F_HW_CSUM);
6666 }
6671 /* before reading the NVM, reset the controller to
6672 * put the device in a known good starting state
6673 */
6676 /* systems with ASPM and others may see the checksum fail on the first
6677 * attempt. Let's give it a few tries
6678 */
6686 }
6687 }
6691 /* copy the MAC address */
6703 }
6719 /* Initialize link parameters. User can change them with ethtool */
6726 /* ring size defaults */
6730 /* Initial Wake on LAN setting - If APM wake is enabled in
6731 * the EEPROM, enable the ACPI Magic Packet filter
6732 */
6734 /* APME bit in EEPROM is mapped to WUC.APME */
6745 else
6748 }
6750 /* fetch WoL from EEPROM */
6754 /* now that we have the eeprom settings, apply the special cases
6755 * where the eeprom may be wrong or the board simply won't support
6756 * wake on lan on a particular port
6757 */
6761 /* initialize the wol settings based on the eeprom settings */
6764 /* make sure adapter isn't asleep if manageability is enabled */
6769 /* save off EEPROM version number */
6772 /* reset the hardware with the new settings */
6775 /* If the controller has AMT, do not set DRV_LOAD until the interface
6776 * is up. For all other cases, let the f/w know that the h/w is now
6777 * under the control of the driver.
6778 */
6787 /* carrier off reporting is important to ethtool even BEFORE open */
6790 /* init PTP hardware clock */
6800 err_register:
6803 err_eeprom:
6806 err_hw_init:
6809 err_sw_init:
6813 err_flashmap:
6815 err_ioremap:
6817 err_alloc_etherdev:
6820 err_pci_reg:
6821 err_dma:
6824 }
6826 /**
6827 * e1000_remove - Device Removal Routine
6828 * @pdev: PCI device information struct
6829 *
6830 * e1000_remove is called by the PCI subsystem to alert the driver
6831 * that it should release a PCI device. The could be caused by a
6832 * Hot-Plug event, or because the driver is going to be removed from
6833 * memory.
6834 **/
6836 {
6843 /* The timers may be rescheduled, so explicitly disable them
6844 * from being rescheduled.
6845 */
6862 }
6863 }
6868 /* Don't lie to e1000_close() down the road. */
6876 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6877 * would have already happened in close and is redundant.
6878 */
6893 /* AER disable */
6897 }
6899 /* PCI Error Recovery (ERS) */
6904 };
6911 board_82571 },
6932 board_80003es2lan },
6934 board_80003es2lan },
6936 board_80003es2lan },
6938 board_80003es2lan },
6981 };
6984 #ifdef CONFIG_PM
6988 e1000_idle)
6989 };
6990 #endif
6992 /* PCI Device API Driver */
6998 #ifdef CONFIG_PM
7001 },
7002 #endif
7005 };
7007 /**
7008 * e1000_init_module - Driver Registration Routine
7009 *
7010 * e1000_init_module is the first routine called when the driver is
7011 * loaded. All it does is register with the PCI subsystem.
7012 **/
7014 {
7017 e1000e_driver_version);
7022 }
7025 /**
7026 * e1000_exit_module - Driver Exit Cleanup Routine
7027 *
7028 * e1000_exit_module is called just before the driver is removed
7029 * from memory.
7030 **/
7032 {
7034 }
7042 /* netdev.c */