| blob | 6a0c1b66ce54116b88a8aaf33bcf0518a7ef7ca3 |
1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
30 #include <linux/module.h>
31 #include <linux/types.h>
32 #include <linux/init.h>
33 #include <linux/bitops.h>
34 #include <linux/vmalloc.h>
35 #include <linux/pagemap.h>
36 #include <linux/netdevice.h>
37 #include <linux/ipv6.h>
38 #include <linux/slab.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <linux/net_tstamp.h>
42 #include <linux/mii.h>
43 #include <linux/ethtool.h>
44 #include <linux/if.h>
45 #include <linux/if_vlan.h>
46 #include <linux/pci.h>
47 #include <linux/pci-aspm.h>
48 #include <linux/delay.h>
49 #include <linux/interrupt.h>
50 #include <linux/ip.h>
51 #include <linux/tcp.h>
52 #include <linux/sctp.h>
53 #include <linux/if_ether.h>
54 #include <linux/aer.h>
55 #include <linux/prefetch.h>
56 #include <linux/pm_runtime.h>
57 #ifdef CONFIG_IGB_DCA
58 #include <linux/dca.h>
59 #endif
60 #include <linux/i2c.h>
63 #define MAJ 5
64 #define MIN 0
65 #define BUILD 3
77 };
113 /* required last entry */
115 };
151 #ifdef CONFIG_IGB_DCA
181 #ifdef CONFIG_PCI_IOV
183 #endif
185 #ifdef CONFIG_PM
186 #ifdef CONFIG_PM_SLEEP
188 #endif
190 #ifdef CONFIG_PM_RUNTIME
194 #endif
198 igb_runtime_idle)
199 };
200 #endif
203 #ifdef CONFIG_IGB_DCA
209 };
210 #endif
211 #ifdef CONFIG_NET_POLL_CONTROLLER
212 /* for netdump / net console */
214 #endif
215 #ifdef CONFIG_PCI_IOV
223 pci_channel_state_t);
231 };
240 #ifdef CONFIG_PM
242 #endif
246 };
253 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
259 u32 ofs;
261 };
265 /* General Registers */
270 /* Interrupt Registers */
273 /* RX Registers */
282 /* TX Registers */
295 /* List Terminator */
296 {}
297 };
299 /* igb_regdump - register printout routine */
301 {
358 }
363 }
365 /* igb_dump - Print registers, Tx-rings and Rx-rings */
367 {
376 u32 staterr;
382 /* Print netdevice Info */
389 }
391 /* Print Registers */
397 }
399 /* Print TX Ring Summary */
415 }
417 /* Print TX Rings */
423 /* Transmit Descriptor Formats
424 *
425 * Advanced Transmit Descriptor
426 * +--------------------------------------------------------------+
427 * 0 | Buffer Address [63:0] |
428 * +--------------------------------------------------------------+
429 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
430 * +--------------------------------------------------------------+
431 * 63 46 45 40 39 38 36 35 32 31 24 15 0
432 */
440 "[bi->dma ] leng ntw timestamp "
456 else
471 DUMP_PREFIX_ADDRESS,
475 }
476 }
478 /* Print RX Rings Summary */
479 rx_ring_summary:
486 }
488 /* Print RX Rings */
494 /* Advanced Receive Descriptor (Read) Format
495 * 63 1 0
496 * +-----------------------------------------------------+
497 * 0 | Packet Buffer Address [63:1] |A0/NSE|
498 * +----------------------------------------------+------+
499 * 8 | Header Buffer Address [63:1] | DD |
500 * +-----------------------------------------------------+
501 *
502 *
503 * Advanced Receive Descriptor (Write-Back) Format
504 *
505 * 63 48 47 32 31 30 21 20 17 16 4 3 0
506 * +------------------------------------------------------+
507 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
508 * | Checksum Ident | | | | Type | Type |
509 * +------------------------------------------------------+
510 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
511 * +------------------------------------------------------+
512 * 63 48 47 32 31 20 19 0
513 */
537 else
541 /* Descriptor Done */
546 next_desc);
553 next_desc);
558 DUMP_PREFIX_ADDRESS,
563 }
564 }
565 }
566 }
568 exit:
570 }
572 /**
573 * igb_get_i2c_data - Reads the I2C SDA data bit
574 * @hw: pointer to hardware structure
575 * @i2cctl: Current value of I2CCTL register
576 *
577 * Returns the I2C data bit value
578 **/
580 {
586 }
588 /**
589 * igb_set_i2c_data - Sets the I2C data bit
590 * @data: pointer to hardware structure
591 * @state: I2C data value (0 or 1) to set
592 *
593 * Sets the I2C data bit
594 **/
596 {
603 else
611 }
613 /**
614 * igb_set_i2c_clk - Sets the I2C SCL clock
615 * @data: pointer to hardware structure
616 * @state: state to set clock
617 *
618 * Sets the I2C clock line to state
619 **/
621 {
632 }
635 }
637 /**
638 * igb_get_i2c_clk - Gets the I2C SCL clock state
639 * @data: pointer to hardware structure
640 *
641 * Gets the I2C clock state
642 **/
644 {
650 }
659 };
661 /**
662 * igb_get_hw_dev - return device
663 * @hw: pointer to hardware structure
664 *
665 * used by hardware layer to print debugging information
666 **/
668 {
671 }
673 /**
674 * igb_init_module - Driver Registration Routine
675 *
676 * igb_init_module is the first routine called when the driver is
677 * loaded. All it does is register with the PCI subsystem.
678 **/
680 {
687 #ifdef CONFIG_IGB_DCA
689 #endif
692 }
696 /**
697 * igb_exit_module - Driver Exit Cleanup Routine
698 *
699 * igb_exit_module is called just before the driver is removed
700 * from memory.
701 **/
703 {
704 #ifdef CONFIG_IGB_DCA
706 #endif
708 }
712 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
713 /**
714 * igb_cache_ring_register - Descriptor ring to register mapping
715 * @adapter: board private structure to initialize
716 *
717 * Once we know the feature-set enabled for the device, we'll cache
718 * the register offset the descriptor ring is assigned to.
719 **/
721 {
727 /* The queues are allocated for virtualization such that VF 0
728 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
729 * In order to avoid collision we start at the first free queue
730 * and continue consuming queues in the same sequence
731 */
736 }
749 }
750 }
752 /**
753 * igb_write_ivar - configure ivar for given MSI-X vector
754 * @hw: pointer to the HW structure
755 * @msix_vector: vector number we are allocating to a given ring
756 * @index: row index of IVAR register to write within IVAR table
757 * @offset: column offset of in IVAR, should be multiple of 8
758 *
759 * This function is intended to handle the writing of the IVAR register
760 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
761 * each containing an cause allocation for an Rx and Tx ring, and a
762 * variable number of rows depending on the number of queues supported.
763 **/
766 {
769 /* clear any bits that are currently set */
772 /* write vector and valid bit */
776 }
778 #define IGB_N0_QUEUE -1
780 {
794 /* The 82575 assigns vectors using a bitmask, which matches the
795 * bitmask for the EICR/EIMS/EIMC registers. To assign one
796 * or more queues to a vector, we write the appropriate bits
797 * into the MSIXBM register for that vector.
798 */
809 /* 82576 uses a table that essentially consists of 2 columns
810 * with 8 rows. The ordering is column-major so we use the
811 * lower 3 bits as the row index, and the 4th bit as the
812 * column offset.
813 */
829 /* On 82580 and newer adapters the scheme is similar to 82576
830 * however instead of ordering column-major we have things
831 * ordered row-major. So we traverse the table by using
832 * bit 0 as the column offset, and the remaining bits as the
833 * row index.
834 */
848 }
850 /* add q_vector eims value to global eims_enable_mask */
853 /* configure q_vector to set itr on first interrupt */
855 }
857 /**
858 * igb_configure_msix - Configure MSI-X hardware
859 * @adapter: board private structure to initialize
860 *
861 * igb_configure_msix sets up the hardware to properly
862 * generate MSI-X interrupts.
863 **/
865 {
866 u32 tmp;
872 /* set vector for other causes, i.e. link changes */
876 /* enable MSI-X PBA support*/
879 /* Auto-Mask interrupts upon ICR read. */
885 /* enable msix_other interrupt */
897 /* Turn on MSI-X capability first, or our settings
898 * won't stick. And it will take days to debug.
899 */
902 E1000_GPIE_NSICR);
904 /* enable msix_other interrupt */
911 /* do nothing, since nothing else supports MSI-X */
921 }
923 /**
924 * igb_request_msix - Initialize MSI-X interrupts
925 * @adapter: board private structure to initialize
926 *
927 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
928 * kernel.
929 **/
931 {
944 vector++;
957 else
962 q_vector);
965 }
970 err_free:
971 /* free already assigned IRQs */
974 vector--;
978 }
979 err_out:
981 }
984 {
991 }
992 }
994 /**
995 * igb_free_q_vector - Free memory allocated for specific interrupt vector
996 * @adapter: board private structure to initialize
997 * @v_idx: Index of vector to be freed
998 *
999 * This function frees the memory allocated to the q_vector. In addition if
1000 * NAPI is enabled it will delete any references to the NAPI struct prior
1001 * to freeing the q_vector.
1002 **/
1004 {
1016 /* ixgbe_get_stats64() might access the rings on this vector,
1017 * we must wait a grace period before freeing it.
1018 */
1020 }
1022 /**
1023 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1024 * @adapter: board private structure to initialize
1025 *
1026 * This function frees the memory allocated to the q_vectors. In addition if
1027 * NAPI is enabled it will delete any references to the NAPI struct prior
1028 * to freeing the q_vector.
1029 **/
1031 {
1040 }
1042 /**
1043 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1044 * @adapter: board private structure to initialize
1045 *
1046 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1047 * MSI-X interrupts allocated.
1048 */
1050 {
1053 }
1055 /**
1056 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1057 * @adapter: board private structure to initialize
1058 * @msix: boolean value of MSIX capability
1059 *
1060 * Attempt to configure interrupts using the best available
1061 * capabilities of the hardware and kernel.
1062 **/
1064 {
1071 /* Number of supported queues. */
1075 else
1078 /* start with one vector for every Rx queue */
1081 /* if Tx handler is separate add 1 for every Tx queue */
1085 /* store the number of vectors reserved for queues */
1088 /* add 1 vector for link status interrupts */
1089 numvecs++;
1091 GFP_KERNEL);
1101 numvecs);
1107 /* If we can't do MSI-X, try MSI */
1108 msi_only:
1109 #ifdef CONFIG_PCI_IOV
1110 /* disable SR-IOV for non MSI-X configurations */
1113 /* disable iov and allow time for transactions to clear */
1123 }
1124 #endif
1133 }
1137 {
1140 }
1142 /**
1143 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1144 * @adapter: board private structure to initialize
1145 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1146 * @v_idx: index of vector in adapter struct
1147 * @txr_count: total number of Tx rings to allocate
1148 * @txr_idx: index of first Tx ring to allocate
1149 * @rxr_count: total number of Rx rings to allocate
1150 * @rxr_idx: index of first Rx ring to allocate
1151 *
1152 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1153 **/
1158 {
1163 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1171 /* allocate q_vector and rings */
1176 /* initialize NAPI */
1180 /* tie q_vector and adapter together */
1184 /* initialize work limits */
1187 /* initialize ITR configuration */
1191 /* initialize pointer to rings */
1194 /* intialize ITR */
1196 /* rx or rx/tx vector */
1200 /* tx only vector */
1203 }
1206 /* assign generic ring traits */
1210 /* configure backlink on ring */
1213 /* update q_vector Tx values */
1216 /* For 82575, context index must be unique per ring. */
1220 /* apply Tx specific ring traits */
1224 /* assign ring to adapter */
1227 /* push pointer to next ring */
1228 ring++;
1229 }
1232 /* assign generic ring traits */
1236 /* configure backlink on ring */
1239 /* update q_vector Rx values */
1242 /* set flag indicating ring supports SCTP checksum offload */
1246 /*
1247 * On i350, i354, i210, and i211, loopback VLAN packets
1248 * have the tag byte-swapped.
1249 */
1253 /* apply Rx specific ring traits */
1257 /* assign ring to adapter */
1259 }
1262 }
1265 /**
1266 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1267 * @adapter: board private structure to initialize
1268 *
1269 * We allocate one q_vector per queue interrupt. If allocation fails we
1270 * return -ENOMEM.
1271 **/
1273 {
1288 /* update counts and index */
1289 rxr_remaining--;
1290 rxr_idx++;
1291 }
1292 }
1303 /* update counts and index */
1306 rxr_idx++;
1307 txr_idx++;
1308 }
1312 err_out:
1321 }
1323 /**
1324 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1325 * @adapter: board private structure to initialize
1326 * @msix: boolean value of MSIX capability
1327 *
1328 * This function initializes the interrupts and allocates all of the queues.
1329 **/
1331 {
1341 }
1347 err_alloc_q_vectors:
1350 }
1352 /**
1353 * igb_request_irq - initialize interrupts
1354 * @adapter: board private structure to initialize
1355 *
1356 * Attempts to configure interrupts using the best available
1357 * capabilities of the hardware and kernel.
1358 **/
1360 {
1369 /* fall back to MSI */
1381 }
1391 /* fall back to legacy interrupts */
1394 }
1401 err);
1403 request_done:
1405 }
1408 {
1419 }
1420 }
1422 /**
1423 * igb_irq_disable - Mask off interrupt generation on the NIC
1424 * @adapter: board private structure
1425 **/
1427 {
1430 /* we need to be careful when disabling interrupts. The VFs are also
1431 * mapped into these registers and so clearing the bits can cause
1432 * issues on the VF drivers so we only need to clear what we set
1433 */
1440 }
1451 }
1452 }
1454 /**
1455 * igb_irq_enable - Enable default interrupt generation settings
1456 * @adapter: board private structure
1457 **/
1459 {
1472 }
1476 E1000_IMS_DRSTA);
1478 E1000_IMS_DRSTA);
1479 }
1480 }
1483 {
1489 /* add VID to filter table */
1494 }
1499 /* remove VID from filter table */
1501 }
1502 }
1504 /**
1505 * igb_release_hw_control - release control of the h/w to f/w
1506 * @adapter: address of board private structure
1507 *
1508 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1509 * For ASF and Pass Through versions of f/w this means that the
1510 * driver is no longer loaded.
1511 **/
1513 {
1515 u32 ctrl_ext;
1517 /* Let firmware take over control of h/w */
1521 }
1523 /**
1524 * igb_get_hw_control - get control of the h/w from f/w
1525 * @adapter: address of board private structure
1526 *
1527 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1528 * For ASF and Pass Through versions of f/w this means that
1529 * the driver is loaded.
1530 **/
1532 {
1534 u32 ctrl_ext;
1536 /* Let firmware know the driver has taken over */
1540 }
1542 /**
1543 * igb_configure - configure the hardware for RX and TX
1544 * @adapter: private board structure
1545 **/
1547 {
1565 /* call igb_desc_unused which always leaves
1566 * at least 1 descriptor unused to make sure
1567 * next_to_use != next_to_clean
1568 */
1572 }
1573 }
1575 /**
1576 * igb_power_up_link - Power up the phy/serdes link
1577 * @adapter: address of board private structure
1578 **/
1580 {
1585 else
1587 }
1589 /**
1590 * igb_power_down_link - Power down the phy/serdes link
1591 * @adapter: address of board private structure
1592 */
1594 {
1597 else
1599 }
1601 /**
1602 * igb_up - Open the interface and prepare it to handle traffic
1603 * @adapter: board private structure
1604 **/
1606 {
1610 /* hardware has been reset, we need to reload some things */
1620 else
1623 /* Clear any pending interrupts. */
1627 /* notify VFs that reset has been completed */
1632 }
1636 /* start the watchdog. */
1641 }
1644 {
1650 /* signal that we're down so the interrupt handler does not
1651 * reschedule our watchdog timer
1652 */
1655 /* disable receives in the hardware */
1658 /* flush and sleep below */
1662 /* disable transmits in the hardware */
1666 /* flush both disables and wait for them to finish */
1675 }
1683 /* record the stats before reset*/
1695 #ifdef CONFIG_IGB_DCA
1697 /* since we reset the hardware DCA settings were cleared */
1699 #endif
1700 }
1703 {
1710 }
1713 {
1720 /* Repartition Pba for greater than 9k mtu
1721 * To take effect CTRL.RST is required.
1722 */
1740 }
1744 /* adjust PBA for jumbo frames */
1747 /* To maintain wire speed transmits, the Tx FIFO should be
1748 * large enough to accommodate two full transmit packets,
1749 * rounded up to the next 1KB and expressed in KB. Likewise,
1750 * the Rx FIFO should be large enough to accommodate at least
1751 * one full receive packet and is similarly rounded up and
1752 * expressed in KB.
1753 */
1755 /* upper 16 bits has Tx packet buffer allocation size in KB */
1757 /* lower 16 bits has Rx packet buffer allocation size in KB */
1759 /* the Tx fifo also stores 16 bytes of information about the Tx
1760 * but don't include ethernet FCS because hardware appends it
1761 */
1767 /* software strips receive CRC, so leave room for it */
1772 /* If current Tx allocation is less than the min Tx FIFO size,
1773 * and the min Tx FIFO size is less than the current Rx FIFO
1774 * allocation, take space away from current Rx allocation
1775 */
1780 /* if short on Rx space, Rx wins and must trump Tx
1781 * adjustment
1782 */
1785 }
1787 }
1789 /* flow control settings */
1790 /* The high water mark must be low enough to fit one full frame
1791 * (or the size used for early receive) above it in the Rx FIFO.
1792 * Set it to the lower of:
1793 * - 90% of the Rx FIFO size, or
1794 * - the full Rx FIFO size minus one full frame
1795 */
1805 /* disable receive for all VFs and wait one second */
1811 /* ping all the active vfs to let them know we are going down */
1814 /* disable transmits and receives */
1817 }
1819 /* Allow time for pending master requests to run */
1826 /* Flow control settings reset on hardware reset, so guarantee flow
1827 * control is off when forcing speed.
1828 */
1833 #ifdef CONFIG_IGB_HWMON
1834 /* Re-initialize the thermal sensor on i350 devices. */
1837 /* If present, re-initialize the external thermal sensor
1838 * interface.
1839 */
1842 }
1843 }
1844 #endif
1850 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1853 /* Re-enable PTP, where applicable. */
1857 }
1860 netdev_features_t features)
1861 {
1862 /* Since there is no support for separate Rx/Tx vlan accel
1863 * enable/disable make sure Tx flag is always in same state as Rx.
1864 */
1867 else
1871 }
1874 netdev_features_t features)
1875 {
1889 else
1893 }
1913 #ifdef CONFIG_NET_POLL_CONTROLLER
1915 #endif
1918 };
1920 /**
1921 * igb_set_fw_version - Configure version string for ethtool
1922 * @adapter: adapter struct
1923 **/
1925 {
1939 /* if option is rom valid, display its version too */
1946 /* no option rom */
1952 }
1954 }
1956 }
1958 /**
1959 * igb_init_i2c - Init I2C interface
1960 * @adapter: pointer to adapter structure
1961 **/
1963 {
1966 /* I2C interface supported on i350 devices */
1970 /* Initialize the i2c bus which is controlled by the registers.
1971 * This bus will use the i2c_algo_bit structue that implements
1972 * the protocol through toggling of the 4 bits in the register.
1973 */
1983 }
1985 /**
1986 * igb_probe - Device Initialization Routine
1987 * @pdev: PCI device information struct
1988 * @ent: entry in igb_pci_tbl
1989 *
1990 * Returns 0 on success, negative on failure
1991 *
1992 * igb_probe initializes an adapter identified by a pci_dev structure.
1993 * The OS initialization, configuring of the adapter private structure,
1994 * and a hardware reset occur.
1995 **/
1997 {
2002 s32 ret_val;
2009 /* Catch broken hardware that put the wrong VF device ID in
2010 * the PCIe SR-IOV capability.
2011 */
2016 }
2037 }
2038 }
2039 }
2042 IORESOURCE_MEM),
2043 igb_driver_name);
2054 IGB_MAX_TX_QUEUES);
2085 /* PCI config space info */
2092 /* Copy the default MAC, PHY and NVM function pointers */
2096 /* Initialize skew-specific constants */
2101 /* setup the private structure */
2110 /* Copper options */
2115 }
2121 /* features is initialized to 0 in allocation, it might have bits
2122 * set by igb_sw_init so we should use an or instead of an
2123 * assignment.
2124 */
2126 NETIF_F_IP_CSUM |
2127 NETIF_F_IPV6_CSUM |
2128 NETIF_F_TSO |
2129 NETIF_F_TSO6 |
2130 NETIF_F_RXHASH |
2131 NETIF_F_RXCSUM |
2132 NETIF_F_HW_VLAN_CTAG_RX |
2133 NETIF_F_HW_VLAN_CTAG_TX;
2135 /* copy netdev features into list of user selectable features */
2139 /* set this bit last since it cannot be part of hw_features */
2143 NETIF_F_TSO6 |
2144 NETIF_F_IP_CSUM |
2145 NETIF_F_IPV6_CSUM |
2146 NETIF_F_SG;
2153 }
2158 }
2164 /* before reading the NVM, reset the controller to put the device in a
2165 * known good starting state
2166 */
2169 /* make sure the NVM is good , i211 parts have special NVM that
2170 * doesn't contain a checksum
2171 */
2177 }
2178 }
2180 /* copy the MAC address out of the NVM */
2190 }
2192 /* get firmware version for ethtool -i */
2203 /* Initialize link properties that are user-changeable */
2213 /* By default, support wake on port A */
2217 /* Check the NVM for wake support on non-port A ports */
2228 /* now that we have the eeprom settings, apply the special cases where
2229 * the eeprom may be wrong or the board simply won't support wake on
2230 * lan on a particular port
2231 */
2239 /* Wake events only supported on port A for dual fiber
2240 * regardless of eeprom setting
2241 */
2247 /* if quad port adapter, disable WoL on all but port A */
2250 else
2252 /* Reset for multiple quad port adapters */
2257 /* If the device can't wake, don't set software support */
2260 }
2262 /* initialize the wol settings based on the eeprom settings */
2266 /* Some vendors want WoL disabled by default, but still supported */
2271 }
2276 /* reset the hardware with the new settings */
2279 /* Init the I2C interface */
2284 }
2286 /* let the f/w know that the h/w is now under the control of the
2287 * driver. */
2295 /* carrier off reporting is important to ethtool even BEFORE open */
2298 #ifdef CONFIG_IGB_DCA
2303 }
2305 #endif
2306 #ifdef CONFIG_IGB_HWMON
2307 /* Initialize the thermal sensor on i350 devices. */
2309 u16 ets_word;
2311 /* Read the NVM to determine if this i350 device supports an
2312 * external thermal sensor.
2313 */
2317 else
2324 }
2325 #endif
2326 /* do hw tstamp init after resetting */
2330 /* print bus type/speed/width info, not applicable to i354 */
2343 }
2363 E1000_CTRL_EXT_LINK_MODE_SGMII))
2365 }
2369 }
2374 err_register:
2377 err_eeprom:
2383 err_sw_init:
2386 err_ioremap:
2388 err_alloc_etherdev:
2391 err_pci_reg:
2392 err_dma:
2395 }
2397 #ifdef CONFIG_PCI_IOV
2399 {
2404 /* reclaim resources allocated to VFs */
2406 /* disable iov and allow time for transactions to clear */
2409 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2414 }
2424 /* Re-enable DMA Coalescing flag since IOV is turned off */
2426 }
2429 }
2432 {
2452 }
2459 /* if allocation failed then we do not support SR-IOV */
2466 }
2477 /* DMA Coalescing is not supported in IOV mode. */
2481 err_out:
2485 out:
2487 }
2489 #endif
2490 /**
2491 * igb_remove_i2c - Cleanup I2C interface
2492 * @adapter: pointer to adapter structure
2493 **/
2495 {
2496 /* free the adapter bus structure */
2498 }
2500 /**
2501 * igb_remove - Device Removal Routine
2502 * @pdev: PCI device information struct
2503 *
2504 * igb_remove is called by the PCI subsystem to alert the driver
2505 * that it should release a PCI device. The could be caused by a
2506 * Hot-Plug event, or because the driver is going to be removed from
2507 * memory.
2508 **/
2510 {
2516 #ifdef CONFIG_IGB_HWMON
2518 #endif
2521 /* The watchdog timer may be rescheduled, so explicitly
2522 * disable watchdog from being rescheduled.
2523 */
2531 #ifdef CONFIG_IGB_DCA
2537 }
2538 #endif
2540 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2541 * would have already happened in close and is redundant.
2542 */
2549 #ifdef CONFIG_PCI_IOV
2551 #endif
2565 }
2567 /**
2568 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2569 * @adapter: board private structure to initialize
2570 *
2571 * This function initializes the vf specific data storage and then attempts to
2572 * allocate the VFs. The reason for ordering it this way is because it is much
2573 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2574 * the memory for the VFs.
2575 **/
2577 {
2578 #ifdef CONFIG_PCI_IOV
2582 /* Virtualization features not supported on i210 family. */
2590 }
2593 {
2595 u32 max_rss_queues;
2597 /* Determine the maximum number of RSS queues supported. */
2607 /* I350 cannot do RSS and SR-IOV at the same time */
2611 }
2612 /* fall through */
2617 }
2618 /* fall through */
2624 }
2628 /* Determine if we need to pair queues. */
2632 /* Device supports enough interrupts without queue pairing. */
2635 /* If VFs are going to be allocated with RSS queues then we
2636 * should pair the queues in order to conserve interrupts due
2637 * to limited supply.
2638 */
2642 /* fall through */
2648 /* If rss_queues > half of max_rss_queues, pair the queues in
2649 * order to conserve interrupts due to limited supply.
2650 */
2654 }
2655 }
2657 /**
2658 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2659 * @adapter: board private structure to initialize
2660 *
2661 * igb_sw_init initializes the Adapter private data structure.
2662 * Fields are initialized based on PCI device information and
2663 * OS network device settings (MTU size).
2664 **/
2666 {
2673 /* set default ring sizes */
2677 /* set default ITR values */
2681 /* set default work limits */
2685 VLAN_HLEN;
2689 #ifdef CONFIG_PCI_IOV
2701 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2705 }
2710 /* Setup and initialize a copy of the hw vlan table array */
2712 GFP_ATOMIC);
2714 /* This call may decrease the number of queues */
2718 }
2722 /* Explicitly disable IRQ since the NIC can be in any state. */
2730 }
2732 /**
2733 * igb_open - Called when a network interface is made active
2734 * @netdev: network interface device structure
2735 *
2736 * Returns 0 on success, negative value on failure
2737 *
2738 * The open entry point is called when a network interface is made
2739 * active by the system (IFF_UP). At this point all resources needed
2740 * for transmit and receive operations are allocated, the interrupt
2741 * handler is registered with the OS, the watchdog timer is started,
2742 * and the stack is notified that the interface is ready.
2743 **/
2745 {
2752 /* disallow open during test */
2756 }
2763 /* allocate transmit descriptors */
2768 /* allocate receive descriptors */
2775 /* before we allocate an interrupt, we must be ready to handle it.
2776 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2777 * as soon as we call pci_request_irq, so we have to setup our
2778 * clean_rx handler before we do so.
2779 */
2786 /* Notify the stack of the actual queue counts. */
2797 /* From here on the code is the same as igb_up() */
2803 /* Clear any pending interrupts. */
2808 /* notify VFs that reset has been completed */
2813 }
2820 /* start the watchdog. */
2826 err_set_queues:
2828 err_req_irq:
2832 err_setup_rx:
2834 err_setup_tx:
2840 }
2843 {
2845 }
2847 /**
2848 * igb_close - Disables a network interface
2849 * @netdev: network interface device structure
2850 *
2851 * Returns 0, this is not allowed to fail
2852 *
2853 * The close entry point is called when an interface is de-activated
2854 * by the OS. The hardware is still under the driver's control, but
2855 * needs to be disabled. A global MAC reset is issued to stop the
2856 * hardware, and all transmit and receive resources are freed.
2857 **/
2859 {
2877 }
2880 {
2882 }
2884 /**
2885 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2886 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2887 *
2888 * Return 0 on success, negative on failure
2889 **/
2891 {
2901 /* round up to nearest 4K */
2915 err:
2920 }
2922 /**
2923 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2924 * (Descriptors) for all queues
2925 * @adapter: board private structure
2926 *
2927 * Return 0 on success, negative on failure
2928 **/
2930 {
2942 }
2943 }
2946 }
2948 /**
2949 * igb_setup_tctl - configure the transmit control registers
2950 * @adapter: Board private structure
2951 **/
2953 {
2955 u32 tctl;
2957 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2960 /* Program the Transmit Control Register */
2968 /* Enable transmits */
2972 }
2974 /**
2975 * igb_configure_tx_ring - Configure transmit ring after Reset
2976 * @adapter: board private structure
2977 * @ring: tx ring to configure
2978 *
2979 * Configure a transmit ring after a reset.
2980 **/
2983 {
2989 /* disable the queue */
3010 }
3012 /**
3013 * igb_configure_tx - Configure transmit Unit after Reset
3014 * @adapter: board private structure
3015 *
3016 * Configure the Tx unit of the MAC after a reset.
3017 **/
3019 {
3024 }
3026 /**
3027 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3028 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
3029 *
3030 * Returns 0 on success, negative on failure
3031 **/
3033 {
3043 /* Round up to nearest 4K */
3058 err:
3063 }
3065 /**
3066 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3067 * (Descriptors) for all queues
3068 * @adapter: board private structure
3069 *
3070 * Return 0 on success, negative on failure
3071 **/
3073 {
3085 }
3086 }
3089 }
3091 /**
3092 * igb_setup_mrqc - configure the multiple receive queue control registers
3093 * @adapter: Board private structure
3094 **/
3096 {
3105 /* Fill out hash function seeds */
3116 /* 82576 supports 2 RSS queues for SR-IOV */
3120 }
3124 }
3126 /* Populate the indirection table 4 entries at a time. To do this
3127 * we are generating the results for n and n+2 and then interleaving
3128 * those with the results with n+1 and n+3.
3129 */
3131 /* first pass generates n and n+2 */
3135 /* second pass generates n+1 and n+3 */
3140 }
3142 /* Disable raw packet checksumming so that RSS hash is placed in
3143 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3144 * offloads as they are enabled by default
3145 */
3150 /* Enable Receive Checksum Offload for SCTP */
3153 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3156 /* Generate RSS hash based on packet types, TCP/UDP
3157 * port numbers and/or IPv4/v6 src and dst addresses
3158 */
3160 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3161 E1000_MRQC_RSS_FIELD_IPV6 |
3162 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3163 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3170 /* If VMDq is enabled then we set the appropriate mode for that, else
3171 * we default to RSS so that an RSS hash is calculated per packet even
3172 * if we are only using one queue
3173 */
3176 /* Set the default pool for the PF's first queue */
3179 E1000_VT_CTL_DISABLE_DEF_POOL);
3181 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3183 }
3186 else
3191 }
3195 }
3197 /**
3198 * igb_setup_rctl - configure the receive control registers
3199 * @adapter: Board private structure
3200 **/
3202 {
3204 u32 rctl;
3214 /* enable stripping of CRC. It's unlikely this will break BMC
3215 * redirection as it did with e1000. Newer features require
3216 * that the HW strips the CRC.
3217 */
3220 /* disable store bad packets and clear size bits. */
3223 /* enable LPE to prevent packets larger than max_frame_size */
3226 /* disable queue 0 to prevent tail write w/o re-config */
3229 /* Attention!!! For SR-IOV PF driver operations you must enable
3230 * queue drop for all VF and PF queues to prevent head of line blocking
3231 * if an un-trusted VF does not provide descriptors to hardware.
3232 */
3234 /* set all queue drop enable bits */
3236 }
3238 /* This is useful for sniffing bad packets. */
3240 /* UPE and MPE will be handled by normal PROMISC logic
3241 * in e1000e_set_rx_mode
3242 */
3250 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3251 * and that breaks VLANs.
3252 */
3253 }
3256 }
3260 {
3262 u32 vmolr;
3264 /* if it isn't the PF check to see if VFs are enabled and
3265 * increase the size to support vlan tags
3266 */
3277 }
3279 /**
3280 * igb_rlpml_set - set maximum receive packet size
3281 * @adapter: board private structure
3282 *
3283 * Configure maximum receivable packet size.
3284 **/
3286 {
3293 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
3294 * to our max jumbo frame size, in case we need to enable
3295 * jumbo frames on one of the rings later.
3296 * This will not pass over-length frames into the default
3297 * queue because it's gated by the VMOLR.RLPML.
3298 */
3300 }
3303 }
3307 {
3309 u32 vmolr;
3311 /* This register exists only on 82576 and newer so if we are older then
3312 * we should exit and do nothing
3313 */
3321 else
3324 /* clear all bits that might not be set */
3329 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
3330 * multicast packets
3331 */
3336 }
3338 /**
3339 * igb_configure_rx_ring - Configure a receive ring after Reset
3340 * @adapter: board private structure
3341 * @ring: receive ring to be configured
3342 *
3343 * Configure the Rx unit of the MAC after a reset.
3344 **/
3347 {
3353 /* disable the queue */
3356 /* Set DMA base address registers */
3363 /* initialize head and tail */
3368 /* set descriptor configuration */
3374 /* Only set Drop Enable if we are supporting multiple queues */
3380 /* set filtering for VMDQ pools */
3387 /* enable receive descriptor fetching */
3390 }
3392 /**
3393 * igb_configure_rx - Configure receive Unit after Reset
3394 * @adapter: board private structure
3395 *
3396 * Configure the Rx unit of the MAC after a reset.
3397 **/
3399 {
3402 /* set UTA to appropriate mode */
3405 /* set the correct pool for the PF default MAC address in entry 0 */
3409 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3410 * the Base and Length of the Rx Descriptor Ring
3411 */
3414 }
3416 /**
3417 * igb_free_tx_resources - Free Tx Resources per Queue
3418 * @tx_ring: Tx descriptor ring for a specific queue
3419 *
3420 * Free all transmit software resources
3421 **/
3423 {
3429 /* if not set, then don't free */
3437 }
3439 /**
3440 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3441 * @adapter: board private structure
3442 *
3443 * Free all transmit software resources
3444 **/
3446 {
3451 }
3455 {
3462 DMA_TO_DEVICE);
3467 DMA_TO_DEVICE);
3468 }
3472 /* buffer_info must be completely set up in the transmit path */
3473 }
3475 /**
3476 * igb_clean_tx_ring - Free Tx Buffers
3477 * @tx_ring: ring to be cleaned
3478 **/
3480 {
3483 u16 i;
3487 /* Free all the Tx ring sk_buffs */
3492 }
3499 /* Zero out the descriptor ring */
3504 }
3506 /**
3507 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3508 * @adapter: board private structure
3509 **/
3511 {
3516 }
3518 /**
3519 * igb_free_rx_resources - Free Rx Resources
3520 * @rx_ring: ring to clean the resources from
3521 *
3522 * Free all receive software resources
3523 **/
3525 {
3531 /* if not set, then don't free */
3539 }
3541 /**
3542 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3543 * @adapter: board private structure
3544 *
3545 * Free all receive software resources
3546 **/
3548 {
3553 }
3555 /**
3556 * igb_clean_rx_ring - Free Rx Buffers per Queue
3557 * @rx_ring: ring to free buffers from
3558 **/
3560 {
3562 u16 i;
3571 /* Free all the Rx ring sk_buffs */
3580 PAGE_SIZE,
3581 DMA_FROM_DEVICE);
3585 }
3590 /* Zero out the descriptor ring */
3596 }
3598 /**
3599 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3600 * @adapter: board private structure
3601 **/
3603 {
3608 }
3610 /**
3611 * igb_set_mac - Change the Ethernet Address of the NIC
3612 * @netdev: network interface device structure
3613 * @p: pointer to an address structure
3614 *
3615 * Returns 0 on success, negative on failure
3616 **/
3618 {
3629 /* set the correct pool for the new PF MAC address in entry 0 */
3634 }
3636 /**
3637 * igb_write_mc_addr_list - write multicast addresses to MTA
3638 * @netdev: network interface device structure
3639 *
3640 * Writes multicast address list to the MTA hash table.
3641 * Returns: -ENOMEM on failure
3642 * 0 on no addresses written
3643 * X on writing X addresses to MTA
3644 **/
3646 {
3654 /* nothing to program, so clear mc list */
3658 }
3664 /* The shared function expects a packed array of only addresses. */
3673 }
3675 /**
3676 * igb_write_uc_addr_list - write unicast addresses to RAR table
3677 * @netdev: network interface device structure
3678 *
3679 * Writes unicast address list to the RAR table.
3680 * Returns: -ENOMEM on failure/insufficient address space
3681 * 0 on no addresses written
3682 * X on writing X addresses to the RAR table
3683 **/
3685 {
3692 /* return ENOMEM indicating insufficient memory for addresses */
3703 rar_entries--,
3704 vfn);
3705 count++;
3706 }
3707 }
3708 /* write the addresses in reverse order to avoid write combining */
3712 }
3716 }
3718 /**
3719 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3720 * @netdev: network interface device structure
3721 *
3722 * The set_rx_mode entry point is called whenever the unicast or multicast
3723 * address lists or the network interface flags are updated. This routine is
3724 * responsible for configuring the hardware for proper unicast, multicast,
3725 * promiscuous mode, and all-multi behavior.
3726 **/
3728 {
3735 /* Check for Promiscuous and All Multicast modes */
3738 /* clear the effected bits */
3743 /* retain VLAN HW filtering if in VT mode */
3753 /* Write addresses to the MTA, if the attempt fails
3754 * then we should just turn on promiscuous mode so
3755 * that we can at least receive multicast traffic
3756 */
3763 }
3764 }
3765 /* Write addresses to available RAR registers, if there is not
3766 * sufficient space to store all the addresses then enable
3767 * unicast promiscuous mode
3768 */
3773 }
3775 }
3778 /* In order to support SR-IOV and eventually VMDq it is necessary to set
3779 * the VMOLR to enable the appropriate modes. Without this workaround
3780 * we will have issues with VLAN tag stripping not being done for frames
3781 * that are only arriving because we are the default pool
3782 */
3790 }
3793 {
3805 }
3808 }
3810 #define IGB_STAGGERED_QUEUE_OFFSET 8
3813 {
3827 }
3828 }
3829 }
3831 /* Need to wait a few seconds after link up to get diagnostic information from
3832 * the phy
3833 */
3835 {
3838 }
3840 /**
3841 * igb_has_link - check shared code for link and determine up/down
3842 * @adapter: pointer to driver private info
3843 **/
3845 {
3850 /* get_link_status is set on LSC (link status) interrupt or
3851 * rx sequence error interrupt. get_link_status will stay
3852 * false until the e1000_check_for_link establishes link
3853 * for copper adapters ONLY
3854 */
3862 }
3871 }
3874 }
3877 {
3881 /* check for thermal sensor event on i350 copper only */
3889 }
3892 }
3894 /**
3895 * igb_watchdog - Timer Call-back
3896 * @data: pointer to adapter cast into an unsigned long
3897 **/
3899 {
3901 /* Do the rest outside of interrupt context */
3903 }
3906 {
3909 watchdog_task);
3913 u32 link;
3918 /* Cancel scheduled suspend requests. */
3922 u32 ctrl;
3928 /* Links status message must follow this format */
3940 /* check if SmartSpeed worked */
3945 /* check for thermal sensor event */
3947 E1000_THSTAT_LINK_THROTTLE)) {
3949 "speed was downshifted because it "
3951 }
3953 /* adjust timeout factor according to speed/duplex */
3960 /* maybe add some timeout factor ? */
3962 }
3969 /* link state has changed, schedule phy info update */
3973 }
3979 /* check for thermal sensor event */
3981 E1000_THSTAT_PWR_DOWN)) {
3984 }
3986 /* Links status message must follow this format */
3993 /* link state has changed, schedule phy info update */
4000 }
4001 }
4010 /* We've lost link, so the controller stops DMA,
4011 * but we've got queued Tx work that's never going
4012 * to get done, so reset controller to flush Tx.
4013 * (Do the reset outside of interrupt context).
4014 */
4018 /* return immediately since reset is imminent */
4020 }
4021 }
4023 /* Force detection of hung controller every watchdog period */
4025 }
4027 /* Cause software interrupt to ensure Rx ring is cleaned */
4035 }
4040 /* Reset the timer */
4044 }
4051 };
4053 /**
4054 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4055 * @q_vector: pointer to q_vector
4056 *
4057 * Stores a new ITR value based on strictly on packet size. This
4058 * algorithm is less sophisticated than that used in igb_update_itr,
4059 * due to the difficulty of synchronizing statistics across multiple
4060 * receive rings. The divisors and thresholds used by this function
4061 * were determined based on theoretical maximum wire speed and testing
4062 * data, in order to minimize response time while increasing bulk
4063 * throughput.
4064 * This functionality is controlled by the InterruptThrottleRate module
4065 * parameter (see igb_param.c)
4066 * NOTE: This function is called only when operating in a multiqueue
4067 * receive environment.
4068 **/
4070 {
4076 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4077 * ints/sec - ITR timer value of 120 ticks.
4078 */
4082 }
4093 /* if avg_wire_size isn't set no work was done */
4097 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4100 /* Don't starve jumbo frames */
4103 /* Give a little boost to mid-size frames */
4106 else
4109 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4115 set_itr_val:
4119 }
4120 clear_counts:
4125 }
4127 /**
4128 * igb_update_itr - update the dynamic ITR value based on statistics
4129 * @q_vector: pointer to q_vector
4130 * @ring_container: ring info to update the itr for
4131 *
4132 * Stores a new ITR value based on packets and byte
4133 * counts during the last interrupt. The advantage of per interrupt
4134 * computation is faster updates and more accurate ITR for the current
4135 * traffic pattern. Constants in this function were computed
4136 * based on theoretical maximum wire speed and thresholds were set based
4137 * on testing data as well as attempting to minimize response time
4138 * while increasing bulk throughput.
4139 * this functionality is controlled by the InterruptThrottleRate module
4140 * parameter (see igb_param.c)
4141 * NOTE: These calculations are only valid when operating in a single-
4142 * queue environment.
4143 **/
4146 {
4151 /* no packets, exit with status unchanged */
4157 /* handle TSO and jumbo frames */
4165 /* this if handles the TSO accounting */
4172 }
4177 }
4185 }
4187 }
4189 /* clear work counters since we have the values we need */
4193 /* write updated itr to ring container */
4195 }
4198 {
4203 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4208 }
4215 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4222 /* counts and packets in update_itr are dependent on these numbers */
4234 }
4236 set_itr_now:
4238 /* this attempts to bias the interrupt rate towards Bulk
4239 * by adding intermediate steps when interrupt rate is
4240 * increasing
4241 */
4246 /* Don't write the value here; it resets the adapter's
4247 * internal timer, and causes us to delay far longer than
4248 * we should between interrupts. Instead, we write the ITR
4249 * value at the beginning of the next interrupt so the timing
4250 * ends up being correct.
4251 */
4254 }
4255 }
4259 {
4265 i++;
4268 /* set bits to identify this as an advanced context descriptor */
4271 /* For 82575, context index must be unique per ring. */
4279 }
4284 {
4299 }
4301 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4310 IPPROTO_TCP,
4314 IGB_TX_FLAGS_CSUM |
4315 IGB_TX_FLAGS_IPV4;
4322 IGB_TX_FLAGS_CSUM;
4323 }
4325 /* compute header lengths */
4329 /* update gso size and bytecount with header size */
4333 /* MSS L4LEN IDX */
4337 /* VLAN MACLEN IPLEN */
4345 }
4348 {
4374 }
4376 }
4382 E1000_ADVTXD_L4LEN_SHIFT;
4387 E1000_ADVTXD_L4LEN_SHIFT;
4391 E1000_ADVTXD_L4LEN_SHIFT;
4397 l4_hdr);
4398 }
4400 }
4402 /* update TX checksum flag */
4404 }
4410 }
4412 #define IGB_SET_FLAG(_input, _flag, _result) \
4413 ((_flag <= _result) ? \
4414 ((u32)(_input & _flag) * (_result / _flag)) : \
4415 ((u32)(_input & _flag) / (_flag / _result)))
4418 {
4419 /* set type for advanced descriptor with frame checksum insertion */
4421 E1000_ADVTXD_DCMD_DEXT |
4422 E1000_ADVTXD_DCMD_IFCS;
4424 /* set HW vlan bit if vlan is present */
4428 /* set segmentation bits for TSO */
4432 /* set timestamp bit if present */
4436 /* insert frame checksum */
4440 }
4445 {
4448 /* 82575 requires a unique index per ring */
4452 /* insert L4 checksum */
4454 IGB_TX_FLAGS_CSUM,
4457 /* insert IPv4 checksum */
4459 IGB_TX_FLAGS_IPV4,
4463 }
4468 {
4473 dma_addr_t dma;
4494 /* record length, and DMA address */
4504 i++;
4505 tx_desc++;
4509 }
4516 }
4523 i++;
4524 tx_desc++;
4528 }
4538 }
4540 /* write last descriptor with RS and EOP bits */
4546 /* set the timestamp */
4549 /* Force memory writes to complete before letting h/w know there
4550 * are new descriptors to fetch. (Only applicable for weak-ordered
4551 * memory model archs, such as IA-64).
4552 *
4553 * We also need this memory barrier to make certain all of the
4554 * status bits have been updated before next_to_watch is written.
4555 */
4558 /* set next_to_watch value indicating a packet is present */
4561 i++;
4569 /* we need this if more than one processor can write to our tail
4570 * at a time, it synchronizes IO on IA64/Altix systems
4571 */
4576 dma_error:
4579 /* clear dma mappings for failed tx_buffer_info map */
4587 i--;
4588 }
4591 }
4594 {
4599 /* Herbert's original patch had:
4600 * smp_mb__after_netif_stop_queue();
4601 * but since that doesn't exist yet, just open code it.
4602 */
4605 /* We need to check again in a case another CPU has just
4606 * made room available.
4607 */
4611 /* A reprieve! */
4619 }
4622 {
4626 }
4630 {
4638 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4639 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
4640 * + 2 desc gap to keep tail from touching head,
4641 * + 1 desc for context descriptor,
4642 * otherwise try next time
4643 */
4650 }
4653 /* this is a hard error */
4655 }
4657 /* record the location of the first descriptor for this packet */
4676 }
4677 }
4682 }
4684 /* record initial flags and protocol */
4696 /* Make sure there is space in the ring for the next send. */
4701 out_drop:
4705 }
4709 {
4716 }
4720 {
4726 }
4731 }
4733 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
4734 * in order to meet this minimum size requirement.
4735 */
4741 }
4744 }
4746 /**
4747 * igb_tx_timeout - Respond to a Tx Hang
4748 * @netdev: network interface device structure
4749 **/
4751 {
4755 /* Do the reset outside of interrupt context */
4764 }
4767 {
4774 }
4776 /**
4777 * igb_get_stats64 - Get System Network Statistics
4778 * @netdev: network interface device structure
4779 * @stats: rtnl_link_stats64 pointer
4780 **/
4783 {
4792 }
4794 /**
4795 * igb_change_mtu - Change the Maximum Transfer Unit
4796 * @netdev: network interface device structure
4797 * @new_mtu: new value for maximum frame size
4798 *
4799 * Returns 0 on success, negative on failure
4800 **/
4802 {
4810 }
4812 #define MAX_STD_JUMBO_FRAME_SIZE 9238
4816 }
4821 /* igb_down has a dependency on max_frame_size */
4833 else
4839 }
4841 /**
4842 * igb_update_stats - Update the board statistics counters
4843 * @adapter: board private structure
4844 **/
4847 {
4851 u16 phy_tmp;
4857 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4859 /* Prevent stats update while adapter is being reset, or if the pci
4860 * connection is down.
4861 */
4876 }
4885 }
4901 }
4905 /* read stats registers */
4962 /* read internal phy specific stats */
4967 /* this stat has invalid values on i210/i211 */
4971 }
4986 /* Fill out the OS statistics structure */
4990 /* Rx Errors */
4992 /* RLEC on some newer hardware can be incorrect so build
4993 * our own version based on RUC and ROC
4994 */
5005 /* Tx Errors */
5012 /* Tx Dropped needs to be maintained elsewhere */
5014 /* Phy Stats */
5020 }
5021 }
5023 /* Management Stats */
5028 /* OS2BMC Stats */
5035 }
5036 }
5039 {
5043 /* reading ICR causes bit 31 of EICR to be cleared */
5049 /* HW is reporting DMA is out of sync */
5051 /* The DMA Out of Sync is also indication of a spoof event
5052 * in IOV mode. Check the Wrong VM Behavior register to
5053 * see if it is really a spoof event.
5054 */
5056 }
5058 /* Check for a mailbox event */
5064 /* guard against interrupt when we're going down */
5067 }
5073 /* acknowledge the interrupt */
5075 /* retrieve hardware timestamp */
5077 }
5078 }
5083 }
5086 {
5098 else
5103 }
5106 {
5109 /* Write the ITR value calculated from the previous interrupt. */
5115 }
5117 #ifdef CONFIG_IGB_DCA
5121 {
5128 /* We can enable relaxed ordering for reads, but not writes when
5129 * DCA is enabled. This is due to a known issue in some chipsets
5130 * which will cause the DCA tag to be cleared.
5131 */
5133 E1000_DCA_TXCTRL_DATA_RRO_EN |
5134 E1000_DCA_TXCTRL_DESC_DCA_EN;
5137 }
5142 {
5149 /* We can enable relaxed ordering for reads, but not writes when
5150 * DCA is enabled. This is due to a known issue in some chipsets
5151 * which will cause the DCA tag to be cleared.
5152 */
5154 E1000_DCA_RXCTRL_DESC_DCA_EN;
5157 }
5160 {
5174 out_no_update:
5176 }
5179 {
5186 /* Always use CB2 mode, difference is masked in the CB driver. */
5192 }
5193 }
5196 {
5205 /* if already enabled, don't do it again */
5213 }
5214 /* Fall Through since DCA is disabled. */
5217 /* without this a class_device is left
5218 * hanging around in the sysfs model
5219 */
5224 }
5226 }
5229 }
5233 {
5237 __igb_notify_dca);
5240 }
5243 #ifdef CONFIG_PCI_IOV
5245 {
5251 /* By default spoof check is enabled for all VFs */
5255 }
5257 #endif
5259 {
5261 u32 ping;
5269 }
5270 }
5273 {
5279 IGB_VF_FLAG_MULTI_PROMISC);
5287 /* if we have hashes and we are clearing a multicast promisc
5288 * flag we need to write the hashes to the MTA as this step
5289 * was previously skipped
5290 */
5298 }
5299 }
5303 /* there are flags left unprocessed, likely not supported */
5308 }
5312 {
5318 /* salt away the number of multicast addresses assigned
5319 * to this VF for later use to restore when the PF multi cast
5320 * list changes
5321 */
5324 /* only up to 30 hash values supported */
5328 /* store the hashes for later use */
5332 /* Flush and reset the mta with the new values */
5336 }
5339 {
5357 }
5359 }
5360 }
5363 {
5370 /* Find the vlan filter for this id */
5374 /* remove the vf from the pool */
5377 /* if pool is empty then remove entry from vfta */
5383 }
5386 }
5389 }
5392 {
5396 /* The vlvf table only exists on 82576 hardware and newer */
5400 /* we only need to do this if VMDq is enabled */
5404 /* Find the vlan filter for this id */
5410 }
5414 /* Did not find a matching VLAN ID entry that was
5415 * enabled. Search for a free filter entry, i.e.
5416 * one without the enable bit set
5417 */
5422 }
5423 }
5425 /* Found an enabled/available entry */
5428 /* if !enabled we need to set this up in vfta */
5430 /* add VID to filter table */
5433 }
5438 /* do not modify RLPML for PF devices */
5443 u32 size;
5450 }
5453 }
5456 /* remove vf from the pool */
5458 /* if pool is empty then remove entry from vfta */
5462 }
5465 /* do not modify RLPML for PF devices */
5471 u32 size;
5478 }
5479 }
5480 }
5482 }
5485 {
5490 else
5492 }
5496 {
5517 }
5525 }
5526 out:
5528 }
5531 {
5534 u32 reg;
5536 /* Find the vlan filter for this id */
5542 }
5548 }
5551 {
5557 /* If in promiscuous mode we need to make sure the PF also has
5558 * the VLAN filter set.
5559 */
5571 /* Go through all the checks to see if the VLAN filter should
5572 * be wiped completely.
5573 */
5580 /* See if any other pools are set for this VLAN filter
5581 * entry other than the PF.
5582 */
5586 /* If the filter was removed then ensure PF pool bit
5587 * is cleared if the PF only added itself to the pool
5588 * because the PF is in promiscuous mode.
5589 */
5595 }
5597 out:
5599 }
5602 {
5603 /* clear flags - except flag that indicates PF has set the MAC */
5607 /* reset offloads to defaults */
5610 /* reset vlans for device */
5616 else
5619 /* reset multicast table array for vf */
5622 /* Flush and reset the mta with the new values */
5624 }
5627 {
5630 /* clear mac address as we were hotplug removed/added */
5634 /* process remaining reset events */
5636 }
5639 {
5646 /* process all the same items cleared in a function level reset */
5649 /* set vf mac address */
5652 /* enable transmit and receive for vf */
5660 /* reply to reset with ack and vf mac address */
5664 }
5667 {
5668 /* The VF MAC Address is stored in a packed array of bytes
5669 * starting at the second 32 bit word of the msg array
5670 */
5678 }
5681 {
5686 /* if device isn't clear to send it shouldn't be reading either */
5691 }
5692 }
5695 {
5700 s32 retval;
5705 /* if receive failed revoke VF CTS stats and restart init */
5711 }
5713 /* this is a message we already processed, do nothing */
5717 /* until the vf completes a reset it should not be
5718 * allowed to start any configuration.
5719 */
5723 }
5730 }
5737 else
5739 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
5740 vf);
5755 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
5756 vf);
5757 else
5764 }
5767 out:
5768 /* notify the VF of the results of what it sent us */
5771 else
5775 }
5778 {
5780 u32 vf;
5783 /* process any reset requests */
5787 /* process any messages pending */
5791 /* process any acks */
5794 }
5795 }
5797 /**
5798 * igb_set_uta - Set unicast filter table address
5799 * @adapter: board private structure
5800 *
5801 * The unicast table address is a register array of 32-bit registers.
5802 * The table is meant to be used in a way similar to how the MTA is used
5803 * however due to certain limitations in the hardware it is necessary to
5804 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5805 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
5806 **/
5808 {
5812 /* The UTA table only exists on 82576 hardware and newer */
5816 /* we only need to do this if VMDq is enabled */
5822 }
5824 /**
5825 * igb_intr_msi - Interrupt Handler
5826 * @irq: interrupt number
5827 * @data: pointer to a network interface device structure
5828 **/
5830 {
5834 /* read ICR disables interrupts using IAM */
5843 /* HW is reporting DMA is out of sync */
5845 }
5851 }
5857 /* acknowledge the interrupt */
5859 /* retrieve hardware timestamp */
5861 }
5862 }
5867 }
5869 /**
5870 * igb_intr - Legacy Interrupt Handler
5871 * @irq: interrupt number
5872 * @data: pointer to a network interface device structure
5873 **/
5875 {
5879 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5880 * need for the IMC write
5881 */
5884 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5885 * not set, then the adapter didn't send an interrupt
5886 */
5896 /* HW is reporting DMA is out of sync */
5898 }
5902 /* guard against interrupt when we're going down */
5905 }
5911 /* acknowledge the interrupt */
5913 /* retrieve hardware timestamp */
5915 }
5916 }
5921 }
5924 {
5932 else
5934 }
5939 else
5941 }
5942 }
5944 /**
5945 * igb_poll - NAPI Rx polling callback
5946 * @napi: napi polling structure
5947 * @budget: count of how many packets we should handle
5948 **/
5950 {
5953 napi);
5956 #ifdef CONFIG_IGB_DCA
5959 #endif
5966 /* If all work not completed, return budget and keep polling */
5970 /* If not enough Rx work done, exit the polling mode */
5975 }
5977 /**
5978 * igb_clean_tx_irq - Reclaim resources after transmit completes
5979 * @q_vector: pointer to q_vector containing needed info
5980 *
5981 * returns true if ring is completely cleaned
5982 **/
5984 {
6003 /* if next_to_watch is not set then there is no work pending */
6007 /* prevent any other reads prior to eop_desc */
6010 /* if DD is not set pending work has not been completed */
6014 /* clear next_to_watch to prevent false hangs */
6017 /* update the statistics for this packet */
6021 /* free the skb */
6024 /* unmap skb header data */
6028 DMA_TO_DEVICE);
6030 /* clear tx_buffer data */
6034 /* clear last DMA location and unmap remaining buffers */
6036 tx_buffer++;
6037 tx_desc++;
6038 i++;
6043 }
6045 /* unmap any remaining paged data */
6050 DMA_TO_DEVICE);
6052 }
6053 }
6055 /* move us one more past the eop_desc for start of next pkt */
6056 tx_buffer++;
6057 tx_desc++;
6058 i++;
6063 }
6065 /* issue prefetch for next Tx descriptor */
6068 /* update budget accounting */
6069 budget--;
6086 /* Detect a transmit hang in hardware, this serializes the
6087 * check with the clearing of time_stamp and movement of i
6088 */
6095 /* detected Tx unit hang */
6115 jiffies,
6120 /* we are about to reset, no point in enabling stuff */
6122 }
6123 }
6125 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6129 /* Make sure that anybody stopping the queue after this
6130 * sees the new next_to_clean.
6131 */
6142 }
6143 }
6146 }
6148 /**
6149 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6150 * @rx_ring: rx descriptor ring to store buffers on
6151 * @old_buff: donor buffer to have page reused
6152 *
6153 * Synchronizes page for reuse by the adapter
6154 **/
6157 {
6163 /* update, and store next to alloc */
6164 nta++;
6167 /* transfer page from old buffer to new buffer */
6170 /* sync the buffer for use by the device */
6173 IGB_RX_BUFSZ,
6174 DMA_FROM_DEVICE);
6175 }
6180 {
6181 /* avoid re-using remote pages */
6185 #if (PAGE_SIZE < 8192)
6186 /* if we are only owner of page we can reuse it */
6190 /* flip page offset to other buffer */
6193 /* since we are the only owner of the page and we need to
6194 * increment it, just set the value to 2 in order to avoid
6195 * an unnecessary locked operation
6196 */
6198 #else
6199 /* move offset up to the next cache line */
6205 /* bump ref count on page before it is given to the stack */
6207 #endif
6210 }
6212 /**
6213 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6214 * @rx_ring: rx descriptor ring to transact packets on
6215 * @rx_buffer: buffer containing page to add
6216 * @rx_desc: descriptor containing length of buffer written by hardware
6217 * @skb: sk_buff to place the data into
6218 *
6219 * This function will add the data contained in rx_buffer->page to the skb.
6220 * This is done either through a direct copy if the data in the buffer is
6221 * less than the skb header size, otherwise it will just attach the page as
6222 * a frag to the skb.
6223 *
6224 * The function will then update the page offset if necessary and return
6225 * true if the buffer can be reused by the adapter.
6226 **/
6231 {
6234 #if (PAGE_SIZE < 8192)
6236 #else
6238 #endif
6247 }
6251 /* we can reuse buffer as-is, just make sure it is local */
6255 /* this page cannot be reused so discard it */
6258 }
6264 }
6269 {
6282 /* prefetch first cache line of first page */
6284 #if L1_CACHE_BYTES < 128
6286 #endif
6288 /* allocate a skb to store the frags */
6290 IGB_RX_HDR_LEN);
6294 }
6296 /* we will be copying header into skb->data in
6297 * pskb_may_pull so it is in our interest to prefetch
6298 * it now to avoid a possible cache miss
6299 */
6301 }
6303 /* we are reusing so sync this buffer for CPU use */
6307 IGB_RX_BUFSZ,
6308 DMA_FROM_DEVICE);
6310 /* pull page into skb */
6312 /* hand second half of page back to the ring */
6315 /* we are not reusing the buffer so unmap it */
6318 }
6320 /* clear contents of rx_buffer */
6324 }
6329 {
6332 /* Ignore Checksum bit is set */
6336 /* Rx checksum disabled via ethtool */
6340 /* TCP/UDP checksum error bit is set */
6342 E1000_RXDEXT_STATERR_TCPE |
6343 E1000_RXDEXT_STATERR_IPE)) {
6344 /* work around errata with sctp packets where the TCPE aka
6345 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6346 * packets, (aka let the stack check the crc32c)
6347 */
6353 }
6354 /* let the stack verify checksum errors */
6356 }
6357 /* It must be a TCP or UDP packet with a valid checksum */
6359 E1000_RXD_STAT_UDPCS))
6364 }
6369 {
6372 }
6374 /**
6375 * igb_is_non_eop - process handling of non-EOP buffers
6376 * @rx_ring: Rx ring being processed
6377 * @rx_desc: Rx descriptor for current buffer
6378 * @skb: current socket buffer containing buffer in progress
6379 *
6380 * This function updates next to clean. If the buffer is an EOP buffer
6381 * this function exits returning false, otherwise it will place the
6382 * sk_buff in the next buffer to be chained and return true indicating
6383 * that this is in fact a non-EOP buffer.
6384 **/
6387 {
6390 /* fetch, update, and store next to clean */
6400 }
6402 /**
6403 * igb_get_headlen - determine size of header for LRO/GRO
6404 * @data: pointer to the start of the headers
6405 * @max_len: total length of section to find headers in
6406 *
6407 * This function is meant to determine the length of headers that will
6408 * be recognized by hardware for LRO, and GRO offloads. The main
6409 * motivation of doing this is to only perform one pull for IPv4 TCP
6410 * packets so that we can do basic things like calculating the gso_size
6411 * based on the average data per packet.
6412 **/
6415 {
6418 /* l2 headers */
6421 /* l3 headers */
6425 __be16 protocol;
6427 u8 hlen;
6429 /* this should never happen, but better safe than sorry */
6433 /* initialize network frame pointer */
6436 /* set first protocol and move network header forward */
6440 /* handle any vlan tag if present */
6447 }
6449 /* handle L3 protocols */
6454 /* access ihl as a u8 to avoid unaligned access on ia64 */
6457 /* verify hlen meets minimum size requirements */
6461 /* record next protocol if header is present */
6468 /* record next protocol */
6473 }
6475 /* relocate pointer to start of L4 header */
6478 /* finally sort out TCP */
6483 /* access doff as a u8 to avoid unaligned access on ia64 */
6486 /* verify hlen meets minimum size requirements */
6496 }
6498 /* If everything has gone correctly hdr.network should be the
6499 * data section of the packet and will be the end of the header.
6500 * If not then it probably represents the end of the last recognized
6501 * header.
6502 */
6505 else
6507 }
6509 /**
6510 * igb_pull_tail - igb specific version of skb_pull_tail
6511 * @rx_ring: rx descriptor ring packet is being transacted on
6512 * @rx_desc: pointer to the EOP Rx descriptor
6513 * @skb: pointer to current skb being adjusted
6514 *
6515 * This function is an igb specific version of __pskb_pull_tail. The
6516 * main difference between this version and the original function is that
6517 * this function can make several assumptions about the state of things
6518 * that allow for significant optimizations versus the standard function.
6519 * As a result we can do things like drop a frag and maintain an accurate
6520 * truesize for the skb.
6521 */
6525 {
6530 /* it is valid to use page_address instead of kmap since we are
6531 * working with pages allocated out of the lomem pool per
6532 * alloc_page(GFP_ATOMIC)
6533 */
6537 /* retrieve timestamp from buffer */
6540 /* update pointers to remove timestamp header */
6546 /* move va to start of packet data */
6548 }
6550 /* we need the header to contain the greater of either ETH_HLEN or
6551 * 60 bytes if the skb->len is less than 60 for skb_pad.
6552 */
6555 /* align pull length to size of long to optimize memcpy performance */
6558 /* update all of the pointers */
6563 }
6565 /**
6566 * igb_cleanup_headers - Correct corrupted or empty headers
6567 * @rx_ring: rx descriptor ring packet is being transacted on
6568 * @rx_desc: pointer to the EOP Rx descriptor
6569 * @skb: pointer to current skb being fixed
6570 *
6571 * Address the case where we are pulling data in on pages only
6572 * and as such no data is present in the skb header.
6573 *
6574 * In addition if skb is not at least 60 bytes we need to pad it so that
6575 * it is large enough to qualify as a valid Ethernet frame.
6576 *
6577 * Returns true if an error was encountered and skb was freed.
6578 **/
6582 {
6584 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6589 }
6590 }
6592 /* place header in linear portion of buffer */
6596 /* if skb_pad returns an error the skb was freed */
6603 }
6606 }
6608 /**
6609 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6610 * @rx_ring: rx descriptor ring packet is being transacted on
6611 * @rx_desc: pointer to the EOP Rx descriptor
6612 * @skb: pointer to current skb being populated
6613 *
6614 * This function checks the ring, descriptor, and packet information in
6615 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6616 * other fields within the skb.
6617 **/
6621 {
6632 u16 vid;
6636 else
6640 }
6645 }
6648 {
6657 /* return some buffers to hardware, one at a time is too slow */
6661 }
6668 /* This memory barrier is needed to keep us from reading
6669 * any other fields out of the rx_desc until we know the
6670 * RXD_STAT_DD bit is set
6671 */
6674 /* retrieve a buffer from the ring */
6677 /* exit if we failed to retrieve a buffer */
6681 cleaned_count++;
6683 /* fetch next buffer in frame if non-eop */
6687 /* verify the packet layout is correct */
6691 }
6693 /* probably a little skewed due to removing CRC */
6696 /* populate checksum, timestamp, VLAN, and protocol */
6701 /* reset skb pointer */
6704 /* update budget accounting */
6705 total_packets++;
6708 /* place incomplete frames back on ring for completion */
6722 }
6726 {
6728 dma_addr_t dma;
6730 /* since we are recycling buffers we should seldom need to alloc */
6734 /* alloc new page for storage */
6739 }
6741 /* map page for use */
6744 /* if mapping failed free memory back to system since
6745 * there isn't much point in holding memory we can't use
6746 */
6752 }
6759 }
6761 /**
6762 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6763 * @adapter: address of board private structure
6764 **/
6766 {
6771 /* nothing to do */
6783 /* Refresh the desc even if buffer_addrs didn't change
6784 * because each write-back erases this info.
6785 */
6788 rx_desc++;
6789 bi++;
6790 i++;
6795 }
6797 /* clear the hdr_addr for the next_to_use descriptor */
6800 cleaned_count--;
6806 /* record the next descriptor to use */
6809 /* update next to alloc since we have filled the ring */
6812 /* Force memory writes to complete before letting h/w
6813 * know there are new descriptors to fetch. (Only
6814 * applicable for weak-ordered memory model archs,
6815 * such as IA-64).
6816 */
6819 }
6820 }
6822 /**
6823 * igb_mii_ioctl -
6824 * @netdev:
6825 * @ifreq:
6826 * @cmd:
6827 **/
6829 {
6848 }
6850 }
6852 /**
6853 * igb_ioctl -
6854 * @netdev:
6855 * @ifreq:
6856 * @cmd:
6857 **/
6859 {
6869 }
6870 }
6873 {
6880 }
6883 {
6890 }
6893 {
6900 /* enable VLAN tag insert/strip */
6905 /* Disable CFI check */
6910 /* disable VLAN tag insert/strip */
6914 }
6917 }
6921 {
6926 /* attempt to add filter to vlvf array */
6929 /* add the filter since PF can receive vlans w/o entry in vlvf */
6935 }
6939 {
6943 s32 err;
6945 /* remove vlan from VLVF table array */
6948 /* if vid was not present in VLVF just remove it from table */
6955 }
6958 {
6959 u16 vid;
6965 }
6968 {
6974 /* Make sure dplx is at most 1 bit and lsb of speed is not set
6975 * for the switch() below to work
6976 */
6980 /* Fiber NIC's only allow 1000 gbps Full duplex
6981 * and 100Mbps Full duplex for 100baseFx sfp
6982 */
6991 }
6992 }
7014 }
7016 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7021 err_inval:
7024 }
7028 {
7034 #ifdef CONFIG_PM
7036 #endif
7045 #ifdef CONFIG_PM
7049 #endif
7059 /* turn on all-multi mode if wake on multicast is enabled */
7064 }
7067 /* advertise wake from D3Cold */
7068 #define E1000_CTRL_ADVD3WUC 0x00100000
7069 /* phy power management enable */
7070 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7074 /* Allow time for pending master requests to run */
7082 }
7087 else
7090 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7091 * would have already happened in close and is redundant.
7092 */
7098 }
7100 #ifdef CONFIG_PM
7101 #ifdef CONFIG_PM_SLEEP
7103 {
7117 }
7120 }
7124 {
7129 u32 err;
7140 }
7149 }
7153 /* let the f/w know that the h/w is now under the control of the
7154 * driver.
7155 */
7166 }
7170 }
7172 #ifdef CONFIG_PM_RUNTIME
7174 {
7183 }
7186 {
7200 }
7203 }
7206 {
7208 }
7210 #endif
7213 {
7221 }
7222 }
7224 #ifdef CONFIG_PCI_IOV
7226 {
7243 }
7251 }
7254 {
7261 }
7264 {
7274 out:
7276 }
7278 #endif
7280 {
7281 #ifdef CONFIG_PCI_IOV
7284 else
7286 #endif
7288 }
7290 #ifdef CONFIG_NET_POLL_CONTROLLER
7291 /* Polling 'interrupt' - used by things like netconsole to send skbs
7292 * without having to re-enable interrupts. It's not called while
7293 * the interrupt routine is executing.
7294 */
7296 {
7306 else
7309 }
7310 }
7313 /**
7314 * igb_io_error_detected - called when PCI error is detected
7315 * @pdev: Pointer to PCI device
7316 * @state: The current pci connection state
7317 *
7318 * This function is called after a PCI bus error affecting
7319 * this device has been detected.
7320 **/
7322 pci_channel_state_t state)
7323 {
7336 /* Request a slot slot reset. */
7338 }
7340 /**
7341 * igb_io_slot_reset - called after the pci bus has been reset.
7342 * @pdev: Pointer to PCI device
7343 *
7344 * Restart the card from scratch, as if from a cold-boot. Implementation
7345 * resembles the first-half of the igb_resume routine.
7346 **/
7348 {
7352 pci_ers_result_t result;
7370 }
7376 err);
7377 /* non-fatal, continue */
7378 }
7381 }
7383 /**
7384 * igb_io_resume - called when traffic can start flowing again.
7385 * @pdev: Pointer to PCI device
7386 *
7387 * This callback is called when the error recovery driver tells us that
7388 * its OK to resume normal operation. Implementation resembles the
7389 * second-half of the igb_resume routine.
7390 */
7392 {
7400 }
7401 }
7405 /* let the f/w know that the h/w is now under the control of the
7406 * driver.
7407 */
7409 }
7412 u8 qsel)
7413 {
7417 /* HW expects these in little endian so we reverse the byte order
7418 * from network order (big endian) to little endian
7419 */
7424 /* Indicate to hardware the Address is Valid. */
7429 else
7436 }
7440 {
7442 /* VF MAC addresses start at end of receive addresses and moves
7443 * towards the first, as a result a collision should not be possible
7444 */
7452 }
7455 {
7468 }
7470 }
7473 {
7481 }
7482 }
7486 {
7488 u32 bcnrc_val;
7491 /* Calculate the rate factor values to set */
7495 tx_rate;
7499 E1000_RTTBCNRC_RF_INT_MASK);
7503 }
7506 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7507 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7508 */
7511 }
7514 {
7518 /* VF TX rate limit was not set or not supported */
7529 }
7537 actual_link_speed);
7538 }
7539 }
7542 {
7561 }
7565 {
7581 else
7588 }
7592 {
7603 }
7606 {
7608 u32 reg;
7616 /* replication is not supported for 82575 */
7619 /* notify HW that the MAC is adding vlan tags */
7624 /* enable replication vlan tag stripping */
7629 /* none of the above registers are supported by i350 */
7631 }
7641 }
7642 }
7645 {
7647 u32 dmac_thr;
7648 u16 hwm;
7652 u32 reg;
7654 /* force threshold to 0. */
7657 /* DMA Coalescing high water mark needs to be greater
7658 * than the Rx threshold. Set hwm to PBA - max frame
7659 * size in 16B units, capping it at PBA - 6KB.
7660 */
7670 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
7671 * frame size, capping it at PBA - 10KB.
7672 */
7681 /* transition to L0x or L1 if available..*/
7684 /* watchdog timer= +-1000 usec in 32usec intervals */
7687 /* Disable BMC-to-OS Watchdog Enable */
7693 /* no lower threshold to disable
7694 * coalescing(smart fifb)-UTRESH=0
7695 */
7702 /* free space in tx packet buffer to wake from
7703 * DMA coal
7704 */
7708 /* make low power state decision controlled
7709 * by DMA coal
7710 */
7719 }
7720 }
7722 /**
7723 * igb_read_i2c_byte - Reads 8 bit word over I2C
7724 * @hw: pointer to hardware structure
7725 * @byte_offset: byte offset to read
7726 * @dev_addr: device address
7727 * @data: value read
7728 *
7729 * Performs byte read operation over I2C interface at
7730 * a specified device address.
7731 **/
7734 {
7737 s32 status;
7757 }
7758 }
7760 /**
7761 * igb_write_i2c_byte - Writes 8 bit word over I2C
7762 * @hw: pointer to hardware structure
7763 * @byte_offset: byte offset to write
7764 * @dev_addr: device address
7765 * @data: value to write
7766 *
7767 * Performs byte write operation over I2C interface at
7768 * a specified device address.
7769 **/
7772 {
7775 s32 status;
7788 else
7791 }
7792 /* igb_main.c */