?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 3.8-rc7
[cris-mirror.git] / sound / soc / davinci / davinci-i2s.c
blob8218312071801bcafe3031fd308d70edd3bbd870
1 /*
2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/platform_data/davinci_asp.h>
20
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/initval.h>
25 #include <sound/soc.h>
26
27 #include "davinci-pcm.h"
28 #include "davinci-i2s.h"
29
30
31 /*
32 * NOTE: terminology here is confusing.
33 *
34 * - This driver supports the "Audio Serial Port" (ASP),
35 * found on dm6446, dm355, and other DaVinci chips.
36 *
37 * - But it labels it a "Multi-channel Buffered Serial Port"
38 * (McBSP) as on older chips like the dm642 ... which was
39 * backward-compatible, possibly explaining that confusion.
40 *
41 * - OMAP chips have a controller called McBSP, which is
42 * incompatible with the DaVinci flavor of McBSP.
43 *
44 * - Newer DaVinci chips have a controller called McASP,
45 * incompatible with ASP and with either McBSP.
46 *
47 * In short: this uses ASP to implement I2S, not McBSP.
48 * And it won't be the only DaVinci implemention of I2S.
49 */
50 #define DAVINCI_MCBSP_DRR_REG 0x00
51 #define DAVINCI_MCBSP_DXR_REG 0x04
52 #define DAVINCI_MCBSP_SPCR_REG 0x08
53 #define DAVINCI_MCBSP_RCR_REG 0x0c
54 #define DAVINCI_MCBSP_XCR_REG 0x10
55 #define DAVINCI_MCBSP_SRGR_REG 0x14
56 #define DAVINCI_MCBSP_PCR_REG 0x24
57
58 #define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
59 #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
60 #define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
61 #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
62 #define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
63 #define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
64 #define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
65
66 #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
67 #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
68 #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
69 #define DAVINCI_MCBSP_RCR_RFIG (1 << 18)
70 #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
71 #define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24)
72 #define DAVINCI_MCBSP_RCR_RPHASE BIT(31)
73
74 #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
75 #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
76 #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
77 #define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
78 #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
79 #define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24)
80 #define DAVINCI_MCBSP_XCR_XPHASE BIT(31)
81
82 #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
83 #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
84 #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
85 #define DAVINCI_MCBSP_SRGR_CLKSM BIT(29)
86
87 #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
88 #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
89 #define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
90 #define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
91 #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
92 #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
93 #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
94 #define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
95 #define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
96
97 enum {
98 DAVINCI_MCBSP_WORD_8 = 0,
99 DAVINCI_MCBSP_WORD_12,
100 DAVINCI_MCBSP_WORD_16,
101 DAVINCI_MCBSP_WORD_20,
102 DAVINCI_MCBSP_WORD_24,
103 DAVINCI_MCBSP_WORD_32,
104 };
105
106 static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = {
107 [SNDRV_PCM_FORMAT_S8] = 1,
108 [SNDRV_PCM_FORMAT_S16_LE] = 2,
109 [SNDRV_PCM_FORMAT_S32_LE] = 4,
110 };
111
112 static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = {
113 [SNDRV_PCM_FORMAT_S8] = DAVINCI_MCBSP_WORD_8,
114 [SNDRV_PCM_FORMAT_S16_LE] = DAVINCI_MCBSP_WORD_16,
115 [SNDRV_PCM_FORMAT_S32_LE] = DAVINCI_MCBSP_WORD_32,
116 };
117
118 static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = {
119 [SNDRV_PCM_FORMAT_S8] = SNDRV_PCM_FORMAT_S16_LE,
120 [SNDRV_PCM_FORMAT_S16_LE] = SNDRV_PCM_FORMAT_S32_LE,
121 };
122
123 struct davinci_mcbsp_dev {
124 struct device *dev;
125 struct davinci_pcm_dma_params dma_params[2];
126 void __iomem *base;
127 #define MOD_DSP_A 0
128 #define MOD_DSP_B 1
129 int mode;
130 u32 pcr;
131 struct clk *clk;
132 /*
133 * Combining both channels into 1 element will at least double the
134 * amount of time between servicing the dma channel, increase
135 * effiency, and reduce the chance of overrun/underrun. But,
136 * it will result in the left & right channels being swapped.
137 *
138 * If relabeling the left and right channels is not possible,
139 * you may want to let the codec know to swap them back.
140 *
141 * It may allow x10 the amount of time to service dma requests,
142 * if the codec is master and is using an unnecessarily fast bit clock
143 * (ie. tlvaic23b), independent of the sample rate. So, having an
144 * entire frame at once means it can be serviced at the sample rate
145 * instead of the bit clock rate.
146 *
147 * In the now unlikely case that an underrun still
148 * occurs, both the left and right samples will be repeated
149 * so that no pops are heard, and the left and right channels
150 * won't end up being swapped because of the underrun.
151 */
152 unsigned enable_channel_combine:1;
153
154 unsigned int fmt;
155 int clk_div;
156 int clk_input_pin;
157 bool i2s_accurate_sck;
158 };
159
160 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
161 int reg, u32 val)
162 {
163 __raw_writel(val, dev->base + reg);
164 }
165
166 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
167 {
168 return __raw_readl(dev->base + reg);
169 }
170
171 static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
172 {
173 u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
174 /* The clock needs to toggle to complete reset.
175 * So, fake it by toggling the clk polarity.
176 */
177 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
178 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
179 }
180
181 static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
182 struct snd_pcm_substream *substream)
183 {
184 struct snd_soc_pcm_runtime *rtd = substream->private_data;
185 struct snd_soc_platform *platform = rtd->platform;
186 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
187 u32 spcr;
188 u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
189 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
190 if (spcr & mask) {
191 /* start off disabled */
192 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
193 spcr & ~mask);
194 toggle_clock(dev, playback);
195 }
196 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
197 DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
198 /* Start the sample generator */
199 spcr |= DAVINCI_MCBSP_SPCR_GRST;
200 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
201 }
202
203 if (playback) {
204 /* Stop the DMA to avoid data loss */
205 /* while the transmitter is out of reset to handle XSYNCERR */
206 if (platform->driver->ops->trigger) {
207 int ret = platform->driver->ops->trigger(substream,
208 SNDRV_PCM_TRIGGER_STOP);
209 if (ret < 0)
210 printk(KERN_DEBUG "Playback DMA stop failed\n");
211 }
212
213 /* Enable the transmitter */
214 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
215 spcr |= DAVINCI_MCBSP_SPCR_XRST;
216 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
217
218 /* wait for any unexpected frame sync error to occur */
219 udelay(100);
220
221 /* Disable the transmitter to clear any outstanding XSYNCERR */
222 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
223 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
224 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
225 toggle_clock(dev, playback);
226
227 /* Restart the DMA */
228 if (platform->driver->ops->trigger) {
229 int ret = platform->driver->ops->trigger(substream,
230 SNDRV_PCM_TRIGGER_START);
231 if (ret < 0)
232 printk(KERN_DEBUG "Playback DMA start failed\n");
233 }
234 }
235
236 /* Enable transmitter or receiver */
237 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
238 spcr |= mask;
239
240 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
241 /* Start frame sync */
242 spcr |= DAVINCI_MCBSP_SPCR_FRST;
243 }
244 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
245 }
246
247 static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
248 {
249 u32 spcr;
250
251 /* Reset transmitter/receiver and sample rate/frame sync generators */
252 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
253 spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
254 spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
255 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
256 toggle_clock(dev, playback);
257 }
258
259 #define DEFAULT_BITPERSAMPLE 16
260
261 static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
262 unsigned int fmt)
263 {
264 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
265 unsigned int pcr;
266 unsigned int srgr;
267 bool inv_fs = false;
268 /* Attention srgr is updated by hw_params! */
269 srgr = DAVINCI_MCBSP_SRGR_FSGM |
270 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
271 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
272
273 dev->fmt = fmt;
274 /* set master/slave audio interface */
275 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
276 case SND_SOC_DAIFMT_CBS_CFS:
277 /* cpu is master */
278 pcr = DAVINCI_MCBSP_PCR_FSXM |
279 DAVINCI_MCBSP_PCR_FSRM |
280 DAVINCI_MCBSP_PCR_CLKXM |
281 DAVINCI_MCBSP_PCR_CLKRM;
282 break;
283 case SND_SOC_DAIFMT_CBM_CFS:
284 pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
285 /*
286 * Selection of the clock input pin that is the
287 * input for the Sample Rate Generator.
288 * McBSP FSR and FSX are driven by the Sample Rate
289 * Generator.
290 */
291 switch (dev->clk_input_pin) {
292 case MCBSP_CLKS:
293 pcr |= DAVINCI_MCBSP_PCR_CLKXM |
294 DAVINCI_MCBSP_PCR_CLKRM;
295 break;
296 case MCBSP_CLKR:
297 pcr |= DAVINCI_MCBSP_PCR_SCLKME;
298 break;
299 default:
300 dev_err(dev->dev, "bad clk_input_pin\n");
301 return -EINVAL;
302 }
303
304 break;
305 case SND_SOC_DAIFMT_CBM_CFM:
306 /* codec is master */
307 pcr = 0;
308 break;
309 default:
310 printk(KERN_ERR "%s:bad master\n", __func__);
311 return -EINVAL;
312 }
313
314 /* interface format */
315 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
316 case SND_SOC_DAIFMT_I2S:
317 /* Davinci doesn't support TRUE I2S, but some codecs will have
318 * the left and right channels contiguous. This allows
319 * dsp_a mode to be used with an inverted normal frame clk.
320 * If your codec is master and does not have contiguous
321 * channels, then you will have sound on only one channel.
322 * Try using a different mode, or codec as slave.
323 *
324 * The TLV320AIC33 is an example of a codec where this works.
325 * It has a variable bit clock frequency allowing it to have
326 * valid data on every bit clock.
327 *
328 * The TLV320AIC23 is an example of a codec where this does not
329 * work. It has a fixed bit clock frequency with progressively
330 * more empty bit clock slots between channels as the sample
331 * rate is lowered.
332 */
333 inv_fs = true;
334 case SND_SOC_DAIFMT_DSP_A:
335 dev->mode = MOD_DSP_A;
336 break;
337 case SND_SOC_DAIFMT_DSP_B:
338 dev->mode = MOD_DSP_B;
339 break;
340 default:
341 printk(KERN_ERR "%s:bad format\n", __func__);
342 return -EINVAL;
343 }
344
345 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
346 case SND_SOC_DAIFMT_NB_NF:
347 /* CLKRP Receive clock polarity,
348 * 1 - sampled on rising edge of CLKR
349 * valid on rising edge
350 * CLKXP Transmit clock polarity,
351 * 1 - clocked on falling edge of CLKX
352 * valid on rising edge
353 * FSRP Receive frame sync pol, 0 - active high
354 * FSXP Transmit frame sync pol, 0 - active high
355 */
356 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
357 break;
358 case SND_SOC_DAIFMT_IB_IF:
359 /* CLKRP Receive clock polarity,
360 * 0 - sampled on falling edge of CLKR
361 * valid on falling edge
362 * CLKXP Transmit clock polarity,
363 * 0 - clocked on rising edge of CLKX
364 * valid on falling edge
365 * FSRP Receive frame sync pol, 1 - active low
366 * FSXP Transmit frame sync pol, 1 - active low
367 */
368 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
369 break;
370 case SND_SOC_DAIFMT_NB_IF:
371 /* CLKRP Receive clock polarity,
372 * 1 - sampled on rising edge of CLKR
373 * valid on rising edge
374 * CLKXP Transmit clock polarity,
375 * 1 - clocked on falling edge of CLKX
376 * valid on rising edge
377 * FSRP Receive frame sync pol, 1 - active low
378 * FSXP Transmit frame sync pol, 1 - active low
379 */
380 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
381 DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
382 break;
383 case SND_SOC_DAIFMT_IB_NF:
384 /* CLKRP Receive clock polarity,
385 * 0 - sampled on falling edge of CLKR
386 * valid on falling edge
387 * CLKXP Transmit clock polarity,
388 * 0 - clocked on rising edge of CLKX
389 * valid on falling edge
390 * FSRP Receive frame sync pol, 0 - active high
391 * FSXP Transmit frame sync pol, 0 - active high
392 */
393 break;
394 default:
395 return -EINVAL;
396 }
397 if (inv_fs == true)
398 pcr ^= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
399 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
400 dev->pcr = pcr;
401 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
402 return 0;
403 }
404
405 static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
406 int div_id, int div)
407 {
408 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
409
410 if (div_id != DAVINCI_MCBSP_CLKGDV)
411 return -ENODEV;
412
413 dev->clk_div = div;
414 return 0;
415 }
416
417 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
418 struct snd_pcm_hw_params *params,
419 struct snd_soc_dai *dai)
420 {
421 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
422 struct davinci_pcm_dma_params *dma_params =
423 &dev->dma_params[substream->stream];
424 struct snd_interval *i = NULL;
425 int mcbsp_word_length, master;
426 unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
427 u32 spcr;
428 snd_pcm_format_t fmt;
429 unsigned element_cnt = 1;
430
431 /* general line settings */
432 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
433 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
434 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
435 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
436 } else {
437 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
438 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
439 }
440
441 master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
442 fmt = params_format(params);
443 mcbsp_word_length = asp_word_length[fmt];
444
445 switch (master) {
446 case SND_SOC_DAIFMT_CBS_CFS:
447 freq = clk_get_rate(dev->clk);
448 srgr = DAVINCI_MCBSP_SRGR_FSGM |
449 DAVINCI_MCBSP_SRGR_CLKSM;
450 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
451 8 - 1);
452 if (dev->i2s_accurate_sck) {
453 clk_div = 256;
454 do {
455 framesize = (freq / (--clk_div)) /
456 params->rate_num *
457 params->rate_den;
458 } while (((framesize < 33) || (framesize > 4095)) &&
459 (clk_div));
460 clk_div--;
461 srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
462 } else {
463 /* symmetric waveforms */
464 clk_div = freq / (mcbsp_word_length * 16) /
465 params->rate_num * params->rate_den;
466 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
467 16 - 1);
468 }
469 clk_div &= 0xFF;
470 srgr |= clk_div;
471 break;
472 case SND_SOC_DAIFMT_CBM_CFS:
473 srgr = DAVINCI_MCBSP_SRGR_FSGM;
474 clk_div = dev->clk_div - 1;
475 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
476 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1);
477 clk_div &= 0xFF;
478 srgr |= clk_div;
479 break;
480 case SND_SOC_DAIFMT_CBM_CFM:
481 /* Clock and frame sync given from external sources */
482 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
483 srgr = DAVINCI_MCBSP_SRGR_FSGM;
484 srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
485 pr_debug("%s - %d FWID set: re-read srgr = %X\n",
486 __func__, __LINE__, snd_interval_value(i) - 1);
487
488 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
489 srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
490 break;
491 default:
492 return -EINVAL;
493 }
494 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
495
496 rcr = DAVINCI_MCBSP_RCR_RFIG;
497 xcr = DAVINCI_MCBSP_XCR_XFIG;
498 if (dev->mode == MOD_DSP_B) {
499 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
500 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
501 } else {
502 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
503 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
504 }
505 /* Determine xfer data type */
506 fmt = params_format(params);
507 if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) {
508 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
509 return -EINVAL;
510 }
511
512 if (params_channels(params) == 2) {
513 element_cnt = 2;
514 if (double_fmt[fmt] && dev->enable_channel_combine) {
515 element_cnt = 1;
516 fmt = double_fmt[fmt];
517 }
518 switch (master) {
519 case SND_SOC_DAIFMT_CBS_CFS:
520 case SND_SOC_DAIFMT_CBS_CFM:
521 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0);
522 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0);
523 rcr |= DAVINCI_MCBSP_RCR_RPHASE;
524 xcr |= DAVINCI_MCBSP_XCR_XPHASE;
525 break;
526 case SND_SOC_DAIFMT_CBM_CFM:
527 case SND_SOC_DAIFMT_CBM_CFS:
528 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1);
529 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1);
530 break;
531 default:
532 return -EINVAL;
533 }
534 }
535 dma_params->acnt = dma_params->data_type = data_type[fmt];
536 dma_params->fifo_level = 0;
537 mcbsp_word_length = asp_word_length[fmt];
538
539 switch (master) {
540 case SND_SOC_DAIFMT_CBS_CFS:
541 case SND_SOC_DAIFMT_CBS_CFM:
542 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
543 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
544 break;
545 case SND_SOC_DAIFMT_CBM_CFM:
546 case SND_SOC_DAIFMT_CBM_CFS:
547 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
548 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
549 break;
550 default:
551 return -EINVAL;
552 }
553
554 rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
555 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
556 xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
557 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
558
559 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
560 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
561 else
562 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
563
564 pr_debug("%s - %d srgr=%X\n", __func__, __LINE__, srgr);
565 pr_debug("%s - %d xcr=%X\n", __func__, __LINE__, xcr);
566 pr_debug("%s - %d rcr=%X\n", __func__, __LINE__, rcr);
567 return 0;
568 }
569
570 static int davinci_i2s_prepare(struct snd_pcm_substream *substream,
571 struct snd_soc_dai *dai)
572 {
573 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
574 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
575 davinci_mcbsp_stop(dev, playback);
576 return 0;
577 }
578
579 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
580 struct snd_soc_dai *dai)
581 {
582 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
583 int ret = 0;
584 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
585
586 switch (cmd) {
587 case SNDRV_PCM_TRIGGER_START:
588 case SNDRV_PCM_TRIGGER_RESUME:
589 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
590 davinci_mcbsp_start(dev, substream);
591 break;
592 case SNDRV_PCM_TRIGGER_STOP:
593 case SNDRV_PCM_TRIGGER_SUSPEND:
594 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
595 davinci_mcbsp_stop(dev, playback);
596 break;
597 default:
598 ret = -EINVAL;
599 }
600 return ret;
601 }
602
603 static int davinci_i2s_startup(struct snd_pcm_substream *substream,
604 struct snd_soc_dai *dai)
605 {
606 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
607
608 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
609 return 0;
610 }
611
612 static void davinci_i2s_shutdown(struct snd_pcm_substream *substream,
613 struct snd_soc_dai *dai)
614 {
615 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
616 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
617 davinci_mcbsp_stop(dev, playback);
618 }
619
620 #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
621
622 static const struct snd_soc_dai_ops davinci_i2s_dai_ops = {
623 .startup = davinci_i2s_startup,
624 .shutdown = davinci_i2s_shutdown,
625 .prepare = davinci_i2s_prepare,
626 .trigger = davinci_i2s_trigger,
627 .hw_params = davinci_i2s_hw_params,
628 .set_fmt = davinci_i2s_set_dai_fmt,
629 .set_clkdiv = davinci_i2s_dai_set_clkdiv,
630
631 };
632
633 static struct snd_soc_dai_driver davinci_i2s_dai = {
634 .playback = {
635 .channels_min = 2,
636 .channels_max = 2,
637 .rates = DAVINCI_I2S_RATES,
638 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
639 .capture = {
640 .channels_min = 2,
641 .channels_max = 2,
642 .rates = DAVINCI_I2S_RATES,
643 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
644 .ops = &davinci_i2s_dai_ops,
645
646 };
647
648 static int davinci_i2s_probe(struct platform_device *pdev)
649 {
650 struct snd_platform_data *pdata = pdev->dev.platform_data;
651 struct davinci_mcbsp_dev *dev;
652 struct resource *mem, *ioarea, *res;
653 enum dma_event_q asp_chan_q = EVENTQ_0;
654 enum dma_event_q ram_chan_q = EVENTQ_1;
655 int ret;
656
657 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
658 if (!mem) {
659 dev_err(&pdev->dev, "no mem resource?\n");
660 return -ENODEV;
661 }
662
663 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
664 resource_size(mem),
665 pdev->name);
666 if (!ioarea) {
667 dev_err(&pdev->dev, "McBSP region already claimed\n");
668 return -EBUSY;
669 }
670
671 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcbsp_dev),
672 GFP_KERNEL);
673 if (!dev)
674 return -ENOMEM;
675 if (pdata) {
676 dev->enable_channel_combine = pdata->enable_channel_combine;
677 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].sram_size =
678 pdata->sram_size_playback;
679 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =
680 pdata->sram_size_capture;
681 dev->clk_input_pin = pdata->clk_input_pin;
682 dev->i2s_accurate_sck = pdata->i2s_accurate_sck;
683 asp_chan_q = pdata->asp_chan_q;
684 ram_chan_q = pdata->ram_chan_q;
685 }
686
687 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].asp_chan_q = asp_chan_q;
688 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].ram_chan_q = ram_chan_q;
689 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].asp_chan_q = asp_chan_q;
690 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].ram_chan_q = ram_chan_q;
691
692 dev->clk = clk_get(&pdev->dev, NULL);
693 if (IS_ERR(dev->clk))
694 return -ENODEV;
695 clk_enable(dev->clk);
696
697 dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
698 if (!dev->base) {
699 dev_err(&pdev->dev, "ioremap failed\n");
700 ret = -ENOMEM;
701 goto err_release_clk;
702 }
703
704 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].dma_addr =
705 (dma_addr_t)(mem->start + DAVINCI_MCBSP_DXR_REG);
706
707 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].dma_addr =
708 (dma_addr_t)(mem->start + DAVINCI_MCBSP_DRR_REG);
709
710 /* first TX, then RX */
711 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
712 if (!res) {
713 dev_err(&pdev->dev, "no DMA resource\n");
714 ret = -ENXIO;
715 goto err_release_clk;
716 }
717 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].channel = res->start;
718
719 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
720 if (!res) {
721 dev_err(&pdev->dev, "no DMA resource\n");
722 ret = -ENXIO;
723 goto err_release_clk;
724 }
725 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].channel = res->start;
726 dev->dev = &pdev->dev;
727
728 dev_set_drvdata(&pdev->dev, dev);
729
730 ret = snd_soc_register_dai(&pdev->dev, &davinci_i2s_dai);
731 if (ret != 0)
732 goto err_release_clk;
733
734 ret = davinci_soc_platform_register(&pdev->dev);
735 if (ret) {
736 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
737 goto err_unregister_dai;
738 }
739
740 return 0;
741
742 err_unregister_dai:
743 snd_soc_unregister_dai(&pdev->dev);
744 err_release_clk:
745 clk_disable(dev->clk);
746 clk_put(dev->clk);
747 return ret;
748 }
749
750 static int davinci_i2s_remove(struct platform_device *pdev)
751 {
752 struct davinci_mcbsp_dev *dev = dev_get_drvdata(&pdev->dev);
753
754 snd_soc_unregister_dai(&pdev->dev);
755 davinci_soc_platform_unregister(&pdev->dev);
756
757 clk_disable(dev->clk);
758 clk_put(dev->clk);
759 dev->clk = NULL;
760
761 return 0;
762 }
763
764 static struct platform_driver davinci_mcbsp_driver = {
765 .probe = davinci_i2s_probe,
766 .remove = davinci_i2s_remove,
767 .driver = {
768 .name = "davinci-mcbsp",
769 .owner = THIS_MODULE,
770 },
771 };
772
773 module_platform_driver(davinci_mcbsp_driver);
774
775 MODULE_AUTHOR("Vladimir Barinov");
776 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
777 MODULE_LICENSE("GPL");
CRIS linux kernel tree